Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
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simulators/gem5/src/cpu/base_dyn_inst_impl.hh
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simulators/gem5/src/cpu/base_dyn_inst_impl.hh
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/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include <iostream>
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#include <set>
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#include <sstream>
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#include <string>
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#include "base/cprintf.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/base_dyn_inst.hh"
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#include "cpu/exetrace.hh"
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#include "debug/DynInst.hh"
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#include "debug/IQ.hh"
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#include "mem/request.hh"
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#include "sim/faults.hh"
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template <class Impl>
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BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
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StaticInstPtr _macroop,
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TheISA::PCState _pc, TheISA::PCState _predPC,
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InstSeqNum seq_num, ImplCPU *cpu)
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: staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
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{
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seqNum = seq_num;
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pc = _pc;
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predPC = _predPC;
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initVars();
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}
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template <class Impl>
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BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
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StaticInstPtr _macroop)
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: staticInst(_staticInst), traceData(NULL), macroop(_macroop)
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{
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seqNum = 0;
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initVars();
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::initVars()
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{
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memData = NULL;
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effAddr = 0;
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physEffAddr = 0;
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readyRegs = 0;
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status.reset();
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instFlags.reset();
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instFlags[RecordResult] = true;
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instFlags[Predicate] = true;
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lqIdx = -1;
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sqIdx = -1;
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// Eventually make this a parameter.
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threadNumber = 0;
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// Also make this a parameter, or perhaps get it from xc or cpu.
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asid = 0;
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// Initialize the fault to be NoFault.
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fault = NoFault;
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#ifndef NDEBUG
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++cpu->instcount;
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if (cpu->instcount > 1500) {
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#ifdef DEBUG
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cpu->dumpInsts();
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dumpSNList();
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#endif
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assert(cpu->instcount <= 1500);
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}
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DPRINTF(DynInst,
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"DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
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seqNum, cpu->name(), cpu->instcount);
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#endif
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#ifdef DEBUG
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cpu->snList.insert(seqNum);
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#endif
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reqToVerify = NULL;
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}
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template <class Impl>
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BaseDynInst<Impl>::~BaseDynInst()
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{
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if (memData) {
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delete [] memData;
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}
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if (traceData) {
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delete traceData;
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}
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fault = NoFault;
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#ifndef NDEBUG
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--cpu->instcount;
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DPRINTF(DynInst,
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"DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
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seqNum, cpu->name(), cpu->instcount);
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#endif
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#ifdef DEBUG
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cpu->snList.erase(seqNum);
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#endif
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if (reqToVerify)
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delete reqToVerify;
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}
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#ifdef DEBUG
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template <class Impl>
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void
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BaseDynInst<Impl>::dumpSNList()
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{
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std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
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int count = 0;
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while (sn_it != cpu->snList.end()) {
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cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
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count++;
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sn_it++;
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}
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}
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#endif
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template <class Impl>
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void
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BaseDynInst<Impl>::dump()
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{
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cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
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std::cout << staticInst->disassemble(pc.instAddr());
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cprintf("'\n");
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::dump(std::string &outstring)
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{
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std::ostringstream s;
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s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
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<< staticInst->disassemble(pc.instAddr());
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outstring = s.str();
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::markSrcRegReady()
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{
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DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
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seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
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if (++readyRegs == numSrcRegs()) {
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setCanIssue();
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}
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}
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template <class Impl>
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void
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BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
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{
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_readySrcRegIdx[src_idx] = true;
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markSrcRegReady();
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}
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template <class Impl>
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bool
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BaseDynInst<Impl>::eaSrcsReady()
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{
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// For now I am assuming that src registers 1..n-1 are the ones that the
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// EA calc depends on. (i.e. src reg 0 is the source of the data to be
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// stored)
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for (int i = 1; i < numSrcRegs(); ++i) {
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if (!_readySrcRegIdx[i])
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return false;
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}
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return true;
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}
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