Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
171
simulators/gem5/src/cpu/SConscript
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171
simulators/gem5/src/cpu/SConscript
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# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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Import('*')
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if env['TARGET_ISA'] == 'no':
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Return()
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#################################################################
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#
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# Generate StaticInst execute() method signatures.
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#
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# There must be one signature for each CPU model compiled in.
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# Since the set of compiled-in models is flexible, we generate a
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# header containing the appropriate set of signatures on the fly.
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#
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#################################################################
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# Template for execute() signature.
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exec_sig_template = '''
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virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
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virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
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{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
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virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const
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{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN };
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virtual Fault completeAcc(Packet *pkt, %(type)s *xc,
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Trace::InstRecord *traceData) const
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{ panic("completeAcc not defined!"); M5_DUMMY_RETURN };
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'''
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mem_ini_sig_template = '''
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virtual Fault eaComp(%(type)s *xc, Trace::InstRecord *traceData) const
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{ panic("eaComp not defined!"); M5_DUMMY_RETURN };
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virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN };
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'''
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mem_comp_sig_template = '''
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virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN };
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'''
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# Generate a temporary CPU list, including the CheckerCPU if
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# it's enabled. This isn't used for anything else other than StaticInst
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# headers.
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temp_cpu_list = env['CPU_MODELS'][:]
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temp_cpu_list.append('CheckerCPU')
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SimObject('CheckerCPU.py')
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# Generate header.
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def gen_cpu_exec_signatures(target, source, env):
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f = open(str(target[0]), 'w')
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print >> f, '''
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#ifndef __CPU_STATIC_INST_EXEC_SIGS_HH__
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#define __CPU_STATIC_INST_EXEC_SIGS_HH__
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'''
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for cpu in temp_cpu_list:
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xc_type = CpuModel.dict[cpu].strings['CPU_exec_context']
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print >> f, exec_sig_template % { 'type' : xc_type }
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print >> f, '''
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#endif // __CPU_STATIC_INST_EXEC_SIGS_HH__
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'''
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# Generate string that gets printed when header is rebuilt
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def gen_sigs_string(target, source, env):
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return " [GENERATE] static_inst_exec_sigs.hh: " \
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+ ', '.join(temp_cpu_list)
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# Add command to generate header to environment.
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env.Command('static_inst_exec_sigs.hh', (),
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Action(gen_cpu_exec_signatures, gen_sigs_string,
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varlist = temp_cpu_list))
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env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
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SimObject('BaseCPU.py')
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SimObject('FuncUnit.py')
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SimObject('ExeTracer.py')
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SimObject('IntelTrace.py')
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SimObject('IntrControl.py')
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SimObject('NativeTrace.py')
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Source('activity.cc')
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Source('base.cc')
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Source('cpuevent.cc')
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Source('exetrace.cc')
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Source('func_unit.cc')
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Source('inteltrace.cc')
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Source('intr_control.cc')
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Source('nativetrace.cc')
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Source('pc_event.cc')
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Source('profile.cc')
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Source('quiesce_event.cc')
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Source('static_inst.cc')
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Source('simple_thread.cc')
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Source('thread_context.cc')
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Source('thread_state.cc')
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if env['TARGET_ISA'] == 'sparc':
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SimObject('LegionTrace.py')
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Source('legiontrace.cc')
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SimObject('DummyChecker.py')
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Source('checker/cpu.cc')
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Source('dummy_checker_builder.cc')
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DebugFlag('Checker')
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DebugFlag('Activity')
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DebugFlag('Commit')
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DebugFlag('Context')
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DebugFlag('Decode')
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DebugFlag('DynInst')
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DebugFlag('ExecEnable')
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DebugFlag('ExecCPSeq')
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DebugFlag('ExecEffAddr')
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DebugFlag('ExecFaulting', 'Trace faulting instructions')
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DebugFlag('ExecFetchSeq')
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DebugFlag('ExecOpClass')
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DebugFlag('ExecRegDelta')
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DebugFlag('ExecResult')
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DebugFlag('ExecSpeculative')
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DebugFlag('ExecSymbol')
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DebugFlag('ExecThread')
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DebugFlag('ExecTicks')
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DebugFlag('ExecMicro')
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DebugFlag('ExecMacro')
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DebugFlag('ExecUser')
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DebugFlag('ExecKernel')
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DebugFlag('ExecAsid')
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DebugFlag('Fetch')
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DebugFlag('IntrControl')
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DebugFlag('O3PipeView')
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DebugFlag('PCEvent')
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DebugFlag('Quiesce')
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CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
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'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
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'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
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'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
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'ExecAsid' ])
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CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
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'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting',
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'ExecUser', 'ExecKernel' ])
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CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
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'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecFaulting',
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'ExecUser', 'ExecKernel' ])
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