Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
458
simulators/gem5/src/arch/x86/bios/intelmp.cc
Normal file
458
simulators/gem5/src/arch/x86/bios/intelmp.cc
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@ -0,0 +1,458 @@
|
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/*
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||||
* Copyright (c) 2008 The Hewlett-Packard Development Company
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||||
* All rights reserved.
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
*
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||||
* Authors: Gabe Black
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*/
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#include "arch/x86/bios/intelmp.hh"
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#include "arch/x86/isa_traits.hh"
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "mem/port_proxy.hh"
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#include "sim/byteswap.hh"
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// Config entry types
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#include "params/X86IntelMPBaseConfigEntry.hh"
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#include "params/X86IntelMPExtConfigEntry.hh"
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// General table structures
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#include "params/X86IntelMPConfigTable.hh"
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#include "params/X86IntelMPFloatingPointer.hh"
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// Base entry types
|
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#include "params/X86IntelMPBus.hh"
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#include "params/X86IntelMPIOAPIC.hh"
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#include "params/X86IntelMPIOIntAssignment.hh"
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#include "params/X86IntelMPLocalIntAssignment.hh"
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#include "params/X86IntelMPProcessor.hh"
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// Extended entry types
|
||||
#include "params/X86IntelMPAddrSpaceMapping.hh"
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#include "params/X86IntelMPBusHierarchy.hh"
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#include "params/X86IntelMPCompatAddrSpaceMod.hh"
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using namespace std;
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const char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_";
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template<class T>
|
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uint8_t
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writeOutField(PortProxy& proxy, Addr addr, T val)
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{
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uint64_t guestVal = X86ISA::htog(val);
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proxy.writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
|
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|
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uint8_t checkSum = 0;
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while(guestVal) {
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checkSum += guestVal;
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guestVal >>= 8;
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}
|
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return checkSum;
|
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}
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||||
|
||||
uint8_t
|
||||
writeOutString(PortProxy& proxy, Addr addr, string str, int length)
|
||||
{
|
||||
char cleanedString[length + 1];
|
||||
cleanedString[length] = 0;
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|
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if (str.length() > length) {
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memcpy(cleanedString, str.c_str(), length);
|
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warn("Intel MP configuration table string \"%s\" "
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"will be truncated to \"%s\".\n", str, cleanedString);
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} else {
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memcpy(cleanedString, str.c_str(), str.length());
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memset(cleanedString + str.length(), 0, length - str.length());
|
||||
}
|
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proxy.writeBlob(addr, (uint8_t *)(&cleanedString), length);
|
||||
|
||||
uint8_t checkSum = 0;
|
||||
for (int i = 0; i < length; i++)
|
||||
checkSum += cleanedString[i];
|
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|
||||
return checkSum;
|
||||
}
|
||||
|
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Addr
|
||||
X86ISA::IntelMP::FloatingPointer::writeOut(PortProxy& proxy, Addr addr)
|
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{
|
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// Make sure that either a config table is present or a default
|
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// configuration was found but not both.
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if (!tableAddr && !defaultConfig)
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fatal("Either an MP configuration table or a default configuration "
|
||||
"must be used.");
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if (tableAddr && defaultConfig)
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fatal("Both an MP configuration table and a default configuration "
|
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"were set.");
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uint8_t checkSum = 0;
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proxy.writeBlob(addr, (uint8_t *)signature, 4);
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for (int i = 0; i < 4; i++)
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checkSum += signature[i];
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checkSum += writeOutField(proxy, addr + 4, tableAddr);
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|
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// The length of the structure in paragraphs, aka 16 byte chunks.
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uint8_t length = 1;
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proxy.writeBlob(addr + 8, &length, 1);
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checkSum += length;
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proxy.writeBlob(addr + 9, &specRev, 1);
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checkSum += specRev;
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|
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proxy.writeBlob(addr + 11, &defaultConfig, 1);
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checkSum += defaultConfig;
|
||||
|
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uint32_t features2_5 = imcrPresent ? (1 << 7) : 0;
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checkSum += writeOutField(proxy, addr + 12, features2_5);
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checkSum = -checkSum;
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proxy.writeBlob(addr + 10, &checkSum, 1);
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return 16;
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}
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X86ISA::IntelMP::FloatingPointer::FloatingPointer(Params * p) :
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SimObject(p), tableAddr(0), specRev(p->spec_rev),
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defaultConfig(p->default_config), imcrPresent(p->imcr_present)
|
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{}
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|
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X86ISA::IntelMP::FloatingPointer *
|
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X86IntelMPFloatingPointerParams::create()
|
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{
|
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return new X86ISA::IntelMP::FloatingPointer(this);
|
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}
|
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|
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Addr
|
||||
X86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy& proxy,
|
||||
Addr addr, uint8_t &checkSum)
|
||||
{
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proxy.writeBlob(addr, &type, 1);
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checkSum += type;
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return 1;
|
||||
}
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||||
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X86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(Params * p, uint8_t _type) :
|
||||
SimObject(p), type(_type)
|
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{}
|
||||
|
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Addr
|
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X86ISA::IntelMP::ExtConfigEntry::writeOut(PortProxy& proxy,
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Addr addr, uint8_t &checkSum)
|
||||
{
|
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proxy.writeBlob(addr, &type, 1);
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checkSum += type;
|
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proxy.writeBlob(addr + 1, &length, 1);
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checkSum += length;
|
||||
return 1;
|
||||
}
|
||||
|
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X86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(Params * p,
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||||
uint8_t _type, uint8_t _length) :
|
||||
SimObject(p), type(_type), length(_length)
|
||||
{}
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||||
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const char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP";
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|
||||
Addr
|
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X86ISA::IntelMP::ConfigTable::writeOut(PortProxy& proxy, Addr addr)
|
||||
{
|
||||
uint8_t checkSum = 0;
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||||
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||||
proxy.writeBlob(addr, (uint8_t *)signature, 4);
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for (int i = 0; i < 4; i++)
|
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checkSum += signature[i];
|
||||
|
||||
// Base table length goes here but will be calculated later.
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||||
|
||||
proxy.writeBlob(addr + 6, (uint8_t *)(&specRev), 1);
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checkSum += specRev;
|
||||
|
||||
// The checksum goes here but is still being calculated.
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|
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checkSum += writeOutString(proxy, addr + 8, oemID, 8);
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checkSum += writeOutString(proxy, addr + 16, productID, 12);
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checkSum += writeOutField(proxy, addr + 28, oemTableAddr);
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checkSum += writeOutField(proxy, addr + 32, oemTableSize);
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checkSum += writeOutField(proxy, addr + 34, (uint16_t)baseEntries.size());
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checkSum += writeOutField(proxy, addr + 36, localApic);
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|
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uint8_t reserved = 0;
|
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proxy.writeBlob(addr + 43, &reserved, 1);
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checkSum += reserved;
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vector<BaseConfigEntry *>::iterator baseEnt;
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uint16_t offset = 44;
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for (baseEnt = baseEntries.begin();
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baseEnt != baseEntries.end(); baseEnt++) {
|
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offset += (*baseEnt)->writeOut(proxy, addr + offset, checkSum);
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}
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||||
// We've found the end of the base table this point.
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checkSum += writeOutField(proxy, addr + 4, offset);
|
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vector<ExtConfigEntry *>::iterator extEnt;
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uint16_t extOffset = 0;
|
||||
uint8_t extCheckSum = 0;
|
||||
for (extEnt = extEntries.begin();
|
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extEnt != extEntries.end(); extEnt++) {
|
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extOffset += (*extEnt)->writeOut(proxy,
|
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addr + offset + extOffset, extCheckSum);
|
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}
|
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checkSum += writeOutField(proxy, addr + 40, extOffset);
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extCheckSum = -extCheckSum;
|
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checkSum += writeOutField(proxy, addr + 42, extCheckSum);
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// And now, we finally have the whole check sum completed.
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checkSum = -checkSum;
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writeOutField(proxy, addr + 7, checkSum);
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return offset + extOffset;
|
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};
|
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X86ISA::IntelMP::ConfigTable::ConfigTable(Params * p) : SimObject(p),
|
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specRev(p->spec_rev), oemID(p->oem_id), productID(p->product_id),
|
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oemTableAddr(p->oem_table_addr), oemTableSize(p->oem_table_size),
|
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localApic(p->local_apic),
|
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baseEntries(p->base_entries), extEntries(p->ext_entries)
|
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{}
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X86ISA::IntelMP::ConfigTable *
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X86IntelMPConfigTableParams::create()
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{
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return new X86ISA::IntelMP::ConfigTable(this);
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}
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Addr
|
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X86ISA::IntelMP::Processor::writeOut(
|
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PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
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{
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BaseConfigEntry::writeOut(proxy, addr, checkSum);
|
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checkSum += writeOutField(proxy, addr + 1, localApicID);
|
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checkSum += writeOutField(proxy, addr + 2, localApicVersion);
|
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checkSum += writeOutField(proxy, addr + 3, cpuFlags);
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checkSum += writeOutField(proxy, addr + 4, cpuSignature);
|
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checkSum += writeOutField(proxy, addr + 8, featureFlags);
|
||||
|
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uint32_t reserved = 0;
|
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proxy.writeBlob(addr + 12, (uint8_t *)(&reserved), 4);
|
||||
proxy.writeBlob(addr + 16, (uint8_t *)(&reserved), 4);
|
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return 20;
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}
|
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X86ISA::IntelMP::Processor::Processor(Params * p) : BaseConfigEntry(p, 0),
|
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localApicID(p->local_apic_id), localApicVersion(p->local_apic_version),
|
||||
cpuFlags(0), cpuSignature(0), featureFlags(p->feature_flags)
|
||||
{
|
||||
if (p->enable)
|
||||
cpuFlags |= (1 << 0);
|
||||
if (p->bootstrap)
|
||||
cpuFlags |= (1 << 1);
|
||||
|
||||
replaceBits(cpuSignature, 0, 3, p->stepping);
|
||||
replaceBits(cpuSignature, 4, 7, p->model);
|
||||
replaceBits(cpuSignature, 8, 11, p->family);
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::Processor *
|
||||
X86IntelMPProcessorParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::Processor(this);
|
||||
}
|
||||
|
||||
Addr
|
||||
X86ISA::IntelMP::Bus::writeOut(
|
||||
PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
||||
{
|
||||
BaseConfigEntry::writeOut(proxy, addr, checkSum);
|
||||
checkSum += writeOutField(proxy, addr + 1, busID);
|
||||
checkSum += writeOutString(proxy, addr + 2, busType, 6);
|
||||
return 8;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::Bus::Bus(Params * p) : BaseConfigEntry(p, 1),
|
||||
busID(p->bus_id), busType(p->bus_type)
|
||||
{}
|
||||
|
||||
X86ISA::IntelMP::Bus *
|
||||
X86IntelMPBusParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::Bus(this);
|
||||
}
|
||||
|
||||
Addr
|
||||
X86ISA::IntelMP::IOAPIC::writeOut(
|
||||
PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
||||
{
|
||||
BaseConfigEntry::writeOut(proxy, addr, checkSum);
|
||||
checkSum += writeOutField(proxy, addr + 1, id);
|
||||
checkSum += writeOutField(proxy, addr + 2, version);
|
||||
checkSum += writeOutField(proxy, addr + 3, flags);
|
||||
checkSum += writeOutField(proxy, addr + 4, address);
|
||||
return 8;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::IOAPIC::IOAPIC(Params * p) : BaseConfigEntry(p, 2),
|
||||
id(p->id), version(p->version), flags(0), address(p->address)
|
||||
{
|
||||
if (p->enable)
|
||||
flags |= 1;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::IOAPIC *
|
||||
X86IntelMPIOAPICParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::IOAPIC(this);
|
||||
}
|
||||
|
||||
Addr
|
||||
X86ISA::IntelMP::IntAssignment::writeOut(
|
||||
PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
||||
{
|
||||
BaseConfigEntry::writeOut(proxy, addr, checkSum);
|
||||
checkSum += writeOutField(proxy, addr + 1, interruptType);
|
||||
checkSum += writeOutField(proxy, addr + 2, flags);
|
||||
checkSum += writeOutField(proxy, addr + 4, sourceBusID);
|
||||
checkSum += writeOutField(proxy, addr + 5, sourceBusIRQ);
|
||||
checkSum += writeOutField(proxy, addr + 6, destApicID);
|
||||
checkSum += writeOutField(proxy, addr + 7, destApicIntIn);
|
||||
return 8;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(Params * p) :
|
||||
IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 3,
|
||||
p->source_bus_id, p->source_bus_irq,
|
||||
p->dest_io_apic_id, p->dest_io_apic_intin)
|
||||
{}
|
||||
|
||||
X86ISA::IntelMP::IOIntAssignment *
|
||||
X86IntelMPIOIntAssignmentParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::IOIntAssignment(this);
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(Params * p) :
|
||||
IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 4,
|
||||
p->source_bus_id, p->source_bus_irq,
|
||||
p->dest_local_apic_id, p->dest_local_apic_intin)
|
||||
{}
|
||||
|
||||
X86ISA::IntelMP::LocalIntAssignment *
|
||||
X86IntelMPLocalIntAssignmentParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::LocalIntAssignment(this);
|
||||
}
|
||||
|
||||
Addr
|
||||
X86ISA::IntelMP::AddrSpaceMapping::writeOut(
|
||||
PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
||||
{
|
||||
ExtConfigEntry::writeOut(proxy, addr, checkSum);
|
||||
checkSum += writeOutField(proxy, addr + 2, busID);
|
||||
checkSum += writeOutField(proxy, addr + 3, addrType);
|
||||
checkSum += writeOutField(proxy, addr + 4, addr);
|
||||
checkSum += writeOutField(proxy, addr + 12, addrLength);
|
||||
return length;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(Params * p) :
|
||||
ExtConfigEntry(p, 128, 20),
|
||||
busID(p->bus_id), addrType(p->address_type),
|
||||
addr(p->address), addrLength(p->length)
|
||||
{}
|
||||
|
||||
X86ISA::IntelMP::AddrSpaceMapping *
|
||||
X86IntelMPAddrSpaceMappingParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::AddrSpaceMapping(this);
|
||||
}
|
||||
|
||||
Addr
|
||||
X86ISA::IntelMP::BusHierarchy::writeOut(
|
||||
PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
||||
{
|
||||
ExtConfigEntry::writeOut(proxy, addr, checkSum);
|
||||
checkSum += writeOutField(proxy, addr + 2, busID);
|
||||
checkSum += writeOutField(proxy, addr + 3, info);
|
||||
checkSum += writeOutField(proxy, addr + 4, parentBus);
|
||||
|
||||
uint32_t reserved = 0;
|
||||
proxy.writeBlob(addr + 5, (uint8_t *)(&reserved), 3);
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::BusHierarchy::BusHierarchy(Params * p) :
|
||||
ExtConfigEntry(p, 129, 8),
|
||||
busID(p->bus_id), info(0), parentBus(p->parent_bus)
|
||||
{
|
||||
if (p->subtractive_decode)
|
||||
info |= 1;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::BusHierarchy *
|
||||
X86IntelMPBusHierarchyParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::BusHierarchy(this);
|
||||
}
|
||||
|
||||
Addr
|
||||
X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(
|
||||
PortProxy& proxy, Addr addr, uint8_t &checkSum)
|
||||
{
|
||||
ExtConfigEntry::writeOut(proxy, addr, checkSum);
|
||||
checkSum += writeOutField(proxy, addr + 2, busID);
|
||||
checkSum += writeOutField(proxy, addr + 3, mod);
|
||||
checkSum += writeOutField(proxy, addr + 4, rangeList);
|
||||
return length;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(Params * p) :
|
||||
ExtConfigEntry(p, 130, 8),
|
||||
busID(p->bus_id), mod(0), rangeList(p->range_list)
|
||||
{
|
||||
if (p->add)
|
||||
mod |= 1;
|
||||
}
|
||||
|
||||
X86ISA::IntelMP::CompatAddrSpaceMod *
|
||||
X86IntelMPCompatAddrSpaceModParams::create()
|
||||
{
|
||||
return new X86ISA::IntelMP::CompatAddrSpaceMod(this);
|
||||
}
|
||||
Reference in New Issue
Block a user