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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
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316
simulators/gem5/src/arch/x86/SConscript Normal file
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# -*- mode:python -*-
# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2005-2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
Import('*')
if env['TARGET_ISA'] == 'x86':
Source('cpuid.cc')
Source('decoder.cc')
Source('decoder_tables.cc')
Source('emulenv.cc')
Source('faults.cc')
Source('insts/badmicroop.cc')
Source('insts/microfpop.cc')
Source('insts/microldstop.cc')
Source('insts/micromediaop.cc')
Source('insts/microop.cc')
Source('insts/microregop.cc')
Source('insts/static_inst.cc')
Source('interrupts.cc')
Source('isa.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('linux/syscalls.cc')
Source('linux/system.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
Source('pagetable_walker.cc')
Source('process.cc')
Source('remote_gdb.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('tlb.cc')
Source('types.cc')
Source('utility.cc')
Source('vtophys.cc')
SimObject('X86LocalApic.py')
SimObject('X86NativeTrace.py')
SimObject('X86System.py')
SimObject('X86TLB.py')
DebugFlag('Faults', "Trace all faults/exceptions/traps")
DebugFlag('LocalApic', "Local APIC debugging")
DebugFlag('PageTableWalker', \
"Page table walker state machine debugging")
DebugFlag('Decoder', "Decoder debug output")
DebugFlag('X86', "Generic X86 ISA debugging")
python_files = (
'__init__.py',
'general_purpose/__init__.py',
'general_purpose/arithmetic/__init__.py',
'general_purpose/arithmetic/add_and_subtract.py',
'general_purpose/arithmetic/increment_and_decrement.py',
'general_purpose/arithmetic/multiply_and_divide.py',
'general_purpose/cache_and_memory_management.py',
'general_purpose/compare_and_test/__init__.py',
'general_purpose/compare_and_test/bit_scan.py',
'general_purpose/compare_and_test/bit_test.py',
'general_purpose/compare_and_test/bounds.py',
'general_purpose/compare_and_test/compare.py',
'general_purpose/compare_and_test/set_byte_on_condition.py',
'general_purpose/compare_and_test/test.py',
'general_purpose/control_transfer/__init__.py',
'general_purpose/control_transfer/call.py',
'general_purpose/control_transfer/conditional_jump.py',
'general_purpose/control_transfer/interrupts_and_exceptions.py',
'general_purpose/control_transfer/jump.py',
'general_purpose/control_transfer/loop.py',
'general_purpose/control_transfer/xreturn.py',
'general_purpose/data_conversion/__init__.py',
'general_purpose/data_conversion/ascii_adjust.py',
'general_purpose/data_conversion/bcd_adjust.py',
'general_purpose/data_conversion/endian_conversion.py',
'general_purpose/data_conversion/extract_sign_mask.py',
'general_purpose/data_conversion/sign_extension.py',
'general_purpose/data_conversion/translate.py',
'general_purpose/data_transfer/__init__.py',
'general_purpose/data_transfer/conditional_move.py',
'general_purpose/data_transfer/move.py',
'general_purpose/data_transfer/stack_operations.py',
'general_purpose/data_transfer/xchg.py',
'general_purpose/flags/__init__.py',
'general_purpose/flags/load_and_store.py',
'general_purpose/flags/push_and_pop.py',
'general_purpose/flags/set_and_clear.py',
'general_purpose/input_output/__init__.py',
'general_purpose/input_output/general_io.py',
'general_purpose/input_output/string_io.py',
'general_purpose/load_effective_address.py',
'general_purpose/load_segment_registers.py',
'general_purpose/logical.py',
'general_purpose/no_operation.py',
'general_purpose/rotate_and_shift/__init__.py',
'general_purpose/rotate_and_shift/rotate.py',
'general_purpose/rotate_and_shift/shift.py',
'general_purpose/semaphores.py',
'general_purpose/string/__init__.py',
'general_purpose/string/compare_strings.py',
'general_purpose/string/load_string.py',
'general_purpose/string/move_string.py',
'general_purpose/string/scan_string.py',
'general_purpose/string/store_string.py',
'general_purpose/system_calls.py',
'romutil.py',
'system/__init__.py',
'system/control_registers.py',
'system/halt.py',
'system/invlpg.py',
'system/undefined_operation.py',
'system/msrs.py',
'system/segmentation.py',
'simd128/__init__.py',
'simd128/integer/__init__.py',
'simd128/integer/data_transfer/__init__.py',
'simd128/integer/data_transfer/move.py',
'simd128/integer/data_transfer/move_non_temporal.py',
'simd128/integer/data_transfer/move_mask.py',
'simd128/integer/data_conversion/__init__.py',
'simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py',
'simd128/integer/data_conversion/convert_integer_to_floating_point.py',
'simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py',
'simd128/integer/data_reordering/__init__.py',
'simd128/integer/data_reordering/unpack_and_interleave.py',
'simd128/integer/data_reordering/pack_with_saturation.py',
'simd128/integer/data_reordering/extract_and_insert.py',
'simd128/integer/data_reordering/shuffle.py',
'simd128/integer/arithmetic/__init__.py',
'simd128/integer/arithmetic/subtraction.py',
'simd128/integer/arithmetic/addition.py',
'simd128/integer/arithmetic/multiplication.py',
'simd128/integer/arithmetic/multiply_add.py',
'simd128/integer/arithmetic/average.py',
'simd128/integer/arithmetic/sum_of_absolute_differences.py',
'simd128/integer/shift/__init__.py',
'simd128/integer/shift/right_arithmetic_shift.py',
'simd128/integer/shift/left_logical_shift.py',
'simd128/integer/shift/right_logical_shift.py',
'simd128/integer/compare/__init__.py',
'simd128/integer/compare/compare_and_write_mask.py',
'simd128/integer/compare/compare_and_write_minimum_or_maximum.py',
'simd128/integer/logical/__init__.py',
'simd128/integer/logical/pand.py',
'simd128/integer/logical/por.py',
'simd128/integer/logical/exclusive_or.py',
'simd128/integer/save_and_restore_state/__init__.py',
'simd128/integer/save_and_restore_state/save_and_restore_state.py',
'simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py',
'simd128/floating_point/__init__.py',
'simd128/floating_point/data_transfer/__init__.py',
'simd128/floating_point/data_transfer/move_mask.py',
'simd128/floating_point/data_transfer/move.py',
'simd128/floating_point/data_transfer/move_with_duplication.py',
'simd128/floating_point/data_transfer/move_non_temporal.py',
'simd128/floating_point/data_conversion/__init__.py',
'simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py',
'simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py',
'simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py',
'simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py',
'simd128/floating_point/data_reordering/__init__.py',
'simd128/floating_point/data_reordering/unpack_and_interleave.py',
'simd128/floating_point/data_reordering/shuffle.py',
'simd128/floating_point/arithmetic/__init__.py',
'simd128/floating_point/arithmetic/subtraction.py',
'simd128/floating_point/arithmetic/addition.py',
'simd128/floating_point/arithmetic/horizontal_subtraction.py',
'simd128/floating_point/arithmetic/horizontal_addition.py',
'simd128/floating_point/arithmetic/square_root.py',
'simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py',
'simd128/floating_point/arithmetic/multiplication.py',
'simd128/floating_point/arithmetic/division.py',
'simd128/floating_point/arithmetic/reciprocal_square_root.py',
'simd128/floating_point/arithmetic/reciprocal_estimation.py',
'simd128/floating_point/compare/__init__.py',
'simd128/floating_point/compare/compare_and_write_mask.py',
'simd128/floating_point/compare/compare_and_write_rflags.py',
'simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py',
'simd128/floating_point/logical/__init__.py',
'simd128/floating_point/logical/andp.py',
'simd128/floating_point/logical/orp.py',
'simd128/floating_point/logical/exclusive_or.py',
'simd64/__init__.py',
'simd64/integer/__init__.py',
'simd64/integer/data_transfer/__init__.py',
'simd64/integer/data_transfer/move_mask.py',
'simd64/integer/data_transfer/move.py',
'simd64/integer/data_transfer/move_non_temporal.py',
'simd64/integer/exit_media_state.py',
'simd64/integer/data_reordering/__init__.py',
'simd64/integer/data_reordering/unpack_and_interleave.py',
'simd64/integer/data_reordering/pack_with_saturation.py',
'simd64/integer/data_reordering/extract_and_insert.py',
'simd64/integer/data_reordering/shuffle_and_swap.py',
'simd64/integer/data_conversion.py',
'simd64/integer/arithmetic/__init__.py',
'simd64/integer/arithmetic/subtraction.py',
'simd64/integer/arithmetic/addition.py',
'simd64/integer/arithmetic/multiplication.py',
'simd64/integer/arithmetic/multiply_add.py',
'simd64/integer/arithmetic/average.py',
'simd64/integer/arithmetic/sum_of_absolute_differences.py',
'simd64/integer/shift/__init__.py',
'simd64/integer/shift/right_arithmetic_shift.py',
'simd64/integer/shift/left_logical_shift.py',
'simd64/integer/shift/right_logical_shift.py',
'simd64/integer/compare/__init__.py',
'simd64/integer/compare/compare_and_write_mask.py',
'simd64/integer/compare/compare_and_write_minimum_or_maximum.py',
'simd64/integer/logical/__init__.py',
'simd64/integer/logical/pand.py',
'simd64/integer/logical/por.py',
'simd64/integer/logical/exclusive_or.py',
'simd64/integer/save_and_restore_state.py',
'simd64/floating_point/__init__.py',
'simd64/floating_point/arithmetic/__init__.py',
'simd64/floating_point/arithmetic/subtraction.py',
'simd64/floating_point/arithmetic/addition.py',
'simd64/floating_point/arithmetic/reciprocal_estimation.py',
'simd64/floating_point/arithmetic/multiplication.py',
'simd64/floating_point/arithmetic/accumulation.py',
'simd64/floating_point/arithmetic/reciprocal_square_root.py',
'simd64/floating_point/data_conversion.py',
'simd64/floating_point/compare/__init__.py',
'simd64/floating_point/compare/compare_and_write_mask.py',
'simd64/floating_point/compare/compare_and_write_minimum_or_maximum.py',
'x87/__init__.py',
'x87/data_transfer_and_conversion/__init__.py',
'x87/data_transfer_and_conversion/convert_and_load_or_store_integer.py',
'x87/data_transfer_and_conversion/load_or_store_floating_point.py',
'x87/data_transfer_and_conversion/exchange.py',
'x87/data_transfer_and_conversion/convert_and_load_or_store_bcd.py',
'x87/data_transfer_and_conversion/conditional_move.py',
'x87/data_transfer_and_conversion/extract.py',
'x87/load_constants/__init__.py',
'x87/load_constants/load_0_1_or_pi.py',
'x87/load_constants/load_logarithm.py',
'x87/arithmetic/__init__.py',
'x87/arithmetic/subtraction.py',
'x87/arithmetic/addition.py',
'x87/arithmetic/partial_remainder.py',
'x87/arithmetic/multiplication.py',
'x87/arithmetic/division.py',
'x87/arithmetic/change_sign.py',
'x87/arithmetic/round.py',
'x87/arithmetic/square_root.py',
'x87/transcendental_functions/__init__.py',
'x87/transcendental_functions/trigonometric_functions.py',
'x87/transcendental_functions/logarithmic_functions.py',
'x87/compare_and_test/__init__.py',
'x87/compare_and_test/classify.py',
'x87/compare_and_test/test.py',
'x87/compare_and_test/floating_point_ordered_compare.py',
'x87/compare_and_test/floating_point_unordered_compare.py',
'x87/compare_and_test/integer_compare.py',
'x87/stack_management/__init__.py',
'x87/stack_management/stack_control.py',
'x87/stack_management/clear_state.py',
'x87/control/__init__.py',
'x87/control/clear_exceptions.py',
'x87/control/initialize.py',
'x87/control/wait_for_exceptions.py',
'x87/control/save_x87_status_word.py',
'x87/control/save_and_restore_x87_control_word.py',
'x87/control/save_and_restore_x87_environment.py',
'x87/no_operation.py'
)
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
for f in isa_desc_files:
# Add in python file dependencies that won't be caught otherwise
for pyfile in python_files:
env.Depends(f, "isa/insts/%s" % pyfile)
# Only non-header files need to be compiled.
if not f.path.endswith('.hh'):
Source(f)

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simulators/gem5/src/arch/x86/SConsopts Normal file
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# -*- mode:python -*-
# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
Import('*')
all_isa_list.append('x86')

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simulators/gem5/src/arch/x86/X86LocalApic.py Normal file
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# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
class X86LocalApic(BasicPioDevice):
type = 'X86LocalApic'
cxx_class = 'X86ISA::Interrupts'
pio_latency = Param.Latency('1ns', 'Programmed IO latency in simticks')
int_master = MasterPort("Port for sending interrupt messages")
int_slave = SlavePort("Port for receiving interrupt messages")
int_latency = Param.Latency('1ns', \
"Latency for an interrupt to propagate through this device.")

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simulators/gem5/src/arch/x86/X86NativeTrace.py Normal file
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# Copyright (c) 2009 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.SimObject import SimObject
from m5.params import *
from NativeTrace import NativeTrace
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
cxx_class = 'Trace::X86NativeTrace'

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simulators/gem5/src/arch/x86/X86System.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from E820 import X86E820Table, X86E820Entry
from SMBios import X86SMBiosSMBiosTable
from IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
from ACPI import X86ACPIRSDP
from System import System
class X86System(System):
type = 'X86System'
smbios_table = Param.X86SMBiosSMBiosTable(
X86SMBiosSMBiosTable(), 'table of smbios/dmi information')
intel_mp_pointer = Param.X86IntelMPFloatingPointer(
X86IntelMPFloatingPointer(),
'intel mp spec floating pointer structure')
intel_mp_table = Param.X86IntelMPConfigTable(
X86IntelMPConfigTable(),
'intel mp spec configuration table')
acpi_description_table_pointer = Param.X86ACPIRSDP(
X86ACPIRSDP(), 'ACPI root description pointer structure')
load_addr_mask = 0xffffffffffffffff
class LinuxX86System(X86System):
type = 'LinuxX86System'
e820_table = Param.X86E820Table(
X86E820Table(), 'E820 map of physical memory')

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simulators/gem5/src/arch/x86/X86TLB.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from m5.proxy import *
from BaseTLB import BaseTLB
from MemObject import MemObject
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
size = Param.Int(64, "TLB size")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")

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# Copyright (c) 2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.SimObject import SimObject
# ACPI description table header. Subclasses contain and handle the actual
# contents as appropriate for that type of table.
class X86ACPISysDescTable(SimObject):
type = 'X86ACPISysDescTable'
cxx_class = 'X86ISA::ACPI::SysDescTable'
abstract = True
oem_id = Param.String('', 'string identifying the oem')
oem_table_id = Param.String('', 'oem table ID')
oem_revision = Param.UInt32(0, 'oem revision number for the table')
creator_id = Param.String('',
'string identifying the generator of the table')
creator_revision = Param.UInt32(0,
'revision number for the creator of the table')
class X86ACPIRSDT(X86ACPISysDescTable):
type = 'X86ACPIRSDT'
cxx_class = 'X86ISA::ACPI::RSDT'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
class X86ACPIXSDT(X86ACPISysDescTable):
type = 'X86ACPIXSDT'
cxx_class = 'X86ISA::ACPI::XSDT'
entries = VectorParam.X86ACPISysDescTable([], 'system description tables')
# Root System Description Pointer Structure
class X86ACPIRSDP(SimObject):
type = 'X86ACPIRSDP'
cxx_class = 'X86ISA::ACPI::RSDP'
oem_id = Param.String('', 'string identifying the oem')
# Because 0 encodes ACPI 1.0, 2 encodes ACPI 3.0, the version implemented
# here.
revision = Param.UInt8(2, 'revision of ACPI being used, zero indexed')
rsdt = Param.X86ACPIRSDT(NULL, 'root system description table')
xsdt = Param.X86ACPIXSDT(X86ACPIXSDT(),
'extended system description table')

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# Copyright (c) 2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from m5.SimObject import SimObject
class X86E820Entry(SimObject):
type = 'X86E820Entry'
cxx_class = 'X86ISA::E820Entry'
addr = Param.Addr(0, 'address of the beginning of the region')
size = Param.MemorySize('0B', 'size of the region')
range_type = Param.UInt64('type of the region')
class X86E820Table(SimObject):
type = 'X86E820Table'
cxx_class = 'X86ISA::E820Table'
entries = VectorParam.X86E820Entry('entries for the e820 table')

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# Copyright (c) 2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from m5.SimObject import SimObject
class X86IntelMPFloatingPointer(SimObject):
type = 'X86IntelMPFloatingPointer'
cxx_class = 'X86ISA::IntelMP::FloatingPointer'
# The minor revision of the spec to support. The major version is assumed
# to be 1 in accordance with the spec.
spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
# If no default configuration is used, set this to 0.
default_config = Param.UInt8(0, 'which default configuration to use')
imcr_present = Param.Bool(True,
'whether the IMCR register is present in the APIC')
class X86IntelMPConfigTable(SimObject):
type = 'X86IntelMPConfigTable'
cxx_class = 'X86ISA::IntelMP::ConfigTable'
spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
oem_id = Param.String("", 'system manufacturer')
product_id = Param.String("", 'product family')
oem_table_addr = Param.UInt32(0,
'pointer to the optional oem configuration table')
oem_table_size = Param.UInt16(0, 'size of the oem configuration table')
local_apic = Param.UInt32(0xFEE00000, 'address of the local APIC')
base_entries = VectorParam.X86IntelMPBaseConfigEntry([],
'base configuration table entries')
ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
'extended configuration table entries')
def add_entry(self, entry):
if isinstance(entry, X86IntelMPBaseConfigEntry):
self.base_entries.append(entry)
elif isinstance(entry, X86IntelMPExtConfigEntry):
self.ext_entries.append(entry)
else:
panic("Don't know what type of Intel MP entry %s is." \
% entry.__class__.__name__)
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
abstract = True
class X86IntelMPExtConfigEntry(SimObject):
type = 'X86IntelMPExtConfigEntry'
cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
abstract = True
class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPProcessor'
cxx_class = 'X86ISA::IntelMP::Processor'
local_apic_id = Param.UInt8(0, 'local APIC id')
local_apic_version = Param.UInt8(0,
'bits 0-7 of the local APIC version register')
enable = Param.Bool(True, 'if this processor is usable')
bootstrap = Param.Bool(False, 'if this is the bootstrap processor')
stepping = Param.UInt8(0, 'Processor stepping')
model = Param.UInt8(0, 'Processor model')
family = Param.UInt8(0, 'Processor family')
feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction')
class X86IntelMPBus(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPBus'
cxx_class = 'X86ISA::IntelMP::Bus'
bus_id = Param.UInt8(0, 'bus id assigned by the bios')
bus_type = Param.String("", 'string that identify the bus type')
# Legal values for bus_type are:
#
# "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII",
# "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME",
# "XPRESS"
class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOAPIC'
cxx_class = 'X86ISA::IntelMP::IOAPIC'
id = Param.UInt8(0, 'id of this APIC')
version = Param.UInt8(0, 'bits 0-7 of the version register')
enable = Param.Bool(True, 'if this APIC is usable')
address = Param.UInt32(0xfec00000, 'address of this APIC')
class X86IntelMPInterruptType(Enum):
map = {'INT' : 0,
'NMI' : 1,
'SMI' : 2,
'ExtInt' : 3
}
class X86IntelMPPolarity(Enum):
map = {'ConformPolarity' : 0,
'ActiveHigh' : 1,
'ActiveLow' : 3
}
class X86IntelMPTriggerMode(Enum):
map = {'ConformTrigger' : 0,
'EdgeTrigger' : 1,
'LevelTrigger' : 3
}
class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPIOIntAssignment'
cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
source_bus_id = Param.UInt8(0,
'id of the bus from which the interrupt signal comes')
source_bus_irq = Param.UInt8(0,
'which interrupt signal from the source bus')
dest_io_apic_id = Param.UInt8(0,
'id of the IO APIC the interrupt is going to')
dest_io_apic_intin = Param.UInt8(0,
'the INTIN pin on the IO APIC the interrupt is connected to')
class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
type = 'X86IntelMPLocalIntAssignment'
cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
polarity = Param.X86IntelMPPolarity('ConformPolarity', 'polarity')
trigger = Param.X86IntelMPTriggerMode('ConformTrigger', 'trigger mode')
source_bus_id = Param.UInt8(0,
'id of the bus from which the interrupt signal comes')
source_bus_irq = Param.UInt8(0,
'which interrupt signal from the source bus')
dest_local_apic_id = Param.UInt8(0,
'id of the local APIC the interrupt is going to')
dest_local_apic_intin = Param.UInt8(0,
'the INTIN pin on the local APIC the interrupt is connected to')
class X86IntelMPAddressType(Enum):
map = {"IOAddress" : 0,
"MemoryAddress" : 1,
"PrefetchAddress" : 2
}
class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
type = 'X86IntelMPAddrSpaceMapping'
cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
address_type = Param.X86IntelMPAddressType('IOAddress',
'address type used to access bus')
address = Param.Addr(0, 'starting address of the mapping')
length = Param.UInt64(0, 'length of mapping in bytes')
class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
type = 'X86IntelMPBusHierarchy'
cxx_class = 'X86ISA::IntelMP::BusHierarchy'
bus_id = Param.UInt8(0, 'id of the bus being described')
subtractive_decode = Param.Bool(False,
'whether this bus contains all addresses not used by its children')
parent_bus = Param.UInt8(0, 'bus id of this busses parent')
class X86IntelMPRangeList(Enum):
map = {"ISACompatible" : 0,
"VGACompatible" : 1
}
class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
type = 'X86IntelMPCompatAddrSpaceMod'
cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
bus_id = Param.UInt8(0, 'id of the bus being described')
add = Param.Bool(False,
'if the range should be added to the original mapping')
range_list = Param.X86IntelMPRangeList('ISACompatible',
'which predefined range of addresses to use')

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# -*- mode:python -*-
# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
Import('*')
if env['TARGET_ISA'] == 'x86':
# The table generated by the bootloader using the BIOS and passed to
# the operating system which maps out physical memory.
SimObject('E820.py')
Source('e820.cc')
# The DMI tables.
SimObject('SMBios.py')
Source('smbios.cc')
# Intel Multiprocessor Specification Configuration Table
SimObject('IntelMP.py')
Source('intelmp.cc')
# ACPI system description tables
SimObject('ACPI.py')
Source('acpi.cc')

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# Copyright (c) 2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from m5.SimObject import SimObject
class X86SMBiosSMBiosStructure(SimObject):
type = 'X86SMBiosSMBiosStructure'
cxx_class = 'X86ISA::SMBios::SMBiosStructure'
abstract = True
class Characteristic(Enum):
map = {'Unknown' : 2,
'Unsupported' : 3,
'ISA' : 4,
'MCA' : 5,
'EISA' : 6,
'PCI' : 7,
'PCMCIA' : 8,
'PnP' : 9,
'APM' : 10,
'Flash' : 11,
'Shadow' : 12,
'VL_Vesa' : 13,
'ESCD' : 14,
'CDBoot' : 15,
'SelectBoot' : 16,
'Socketed' : 17,
'PCMCIABoot' : 18,
'EDD' : 19,
'NEC9800' : 20,
'Toshiba' : 21,
'Floppy_5_25_360KB' : 22,
'Floppy_5_25_1_2MB' : 23,
'Floppy_3_5_720KB' : 24,
'Floppy_3_5_2_88MB' : 25,
'PrintScreen' : 26,
'Keyboard8024' : 27,
'Serial' : 28,
'Printer' : 29,
'CGA_Mono' : 30,
'NEC_PC_98' : 31
}
class ExtCharacteristic(Enum):
map = {'ACPI' : 0,
'USBLegacy' : 1,
'AGP' : 2,
'I20Boot' : 3,
'LS_120Boot' : 4,
'ZIPBoot' : 5,
'FirewireBoot' : 6,
'SmartBattery' : 7,
'BootSpec' : 8,
'NetServiceBoot' : 9,
'TargetContent' : 10
}
class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure):
type = 'X86SMBiosBiosInformation'
cxx_class = 'X86ISA::SMBios::BiosInformation'
vendor = Param.String("", "vendor name string")
version = Param.String("", "version string")
starting_addr_segment = \
Param.UInt16(0, "segment location of bios starting address")
release_date = Param.String("06/08/2008", "release date")
rom_size = Param.UInt8(0, "rom size")
characteristics = VectorParam.Characteristic([],
"bios characteristic bit vector")
characteristic_ext_bytes = VectorParam.ExtCharacteristic([],
"extended bios characteristic bit vector")
major = Param.UInt8(0, "major version number")
minor = Param.UInt8(0, "minor version number")
emb_cont_firmware_major = Param.UInt8(0,
"embedded controller firmware major version number")
emb_cont_firmware_minor = Param.UInt8(0,
"embedded controller firmware minor version number")
class X86SMBiosSMBiosTable(SimObject):
type = 'X86SMBiosSMBiosTable'
cxx_class = 'X86ISA::SMBios::SMBiosTable'
major_version = Param.UInt8(2, "major version number")
minor_version = Param.UInt8(5, "minor version number")
structures = VectorParam.X86SMBiosSMBiosStructure([], "smbios structures")

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/bios/acpi.hh"
#include "mem/port.hh"
#include "params/X86ACPIRSDP.hh"
#include "params/X86ACPIRSDT.hh"
#include "params/X86ACPISysDescTable.hh"
#include "params/X86ACPIXSDT.hh"
#include "sim/byteswap.hh"
#include "sim/sim_object.hh"
using namespace std;
const char X86ISA::ACPI::RSDP::signature[] = "RSD PTR ";
X86ISA::ACPI::RSDP::RSDP(Params *p) : SimObject(p), oemID(p->oem_id),
revision(p->revision), rsdt(p->rsdt), xsdt(p->xsdt)
{}
X86ISA::ACPI::SysDescTable::SysDescTable(Params *p,
const char * _signature, uint8_t _revision) : SimObject(p),
signature(_signature), revision(_revision),
oemID(p->oem_id), oemTableID(p->oem_table_id),
oemRevision(p->oem_revision),
creatorID(p->creator_id), creatorRevision(p->creator_revision)
{}
X86ISA::ACPI::RSDT::RSDT(Params *p) :
SysDescTable(p, "RSDT", 1), entries(p->entries)
{}
X86ISA::ACPI::XSDT::XSDT(Params *p) :
SysDescTable(p, "XSDT", 1), entries(p->entries)
{}
X86ISA::ACPI::RSDP *
X86ACPIRSDPParams::create()
{
return new X86ISA::ACPI::RSDP(this);
}
X86ISA::ACPI::RSDT *
X86ACPIRSDTParams::create()
{
return new X86ISA::ACPI::RSDT(this);
}
X86ISA::ACPI::XSDT *
X86ACPIXSDTParams::create()
{
return new X86ISA::ACPI::XSDT(this);
}

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_BIOS_ACPI_HH__
#define __ARCH_X86_BIOS_ACPI_HH__
#include <string>
#include <vector>
#include "base/types.hh"
#include "sim/sim_object.hh"
class Port;
struct X86ACPIRSDPParams;
struct X86ACPISysDescTableParams;
struct X86ACPIRSDTParams;
struct X86ACPIXSDTParams;
namespace X86ISA
{
namespace ACPI
{
class RSDT;
class XSDT;
class SysDescTable;
class RSDP : public SimObject
{
protected:
typedef X86ACPIRSDPParams Params;
static const char signature[];
std::string oemID;
uint8_t revision;
RSDT * rsdt;
XSDT * xsdt;
public:
RSDP(Params *p);
};
class SysDescTable : public SimObject
{
protected:
typedef X86ACPISysDescTableParams Params;
const char * signature;
uint8_t revision;
std::string oemID;
std::string oemTableID;
uint32_t oemRevision;
std::string creatorID;
uint32_t creatorRevision;
public:
SysDescTable(Params *p, const char * _signature, uint8_t _revision);
};
class RSDT : public SysDescTable
{
protected:
typedef X86ACPIRSDTParams Params;
std::vector<SysDescTable *> entries;
public:
RSDT(Params *p);
};
class XSDT : public SysDescTable
{
protected:
typedef X86ACPIXSDTParams Params;
std::vector<SysDescTable *> entries;
public:
XSDT(Params *p);
};
} // namespace ACPI
} // namespace X86ISA
#endif // __ARCH_X86_BIOS_E820_HH__

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/bios/e820.hh"
#include "arch/x86/isa_traits.hh"
#include "mem/port_proxy.hh"
#include "sim/byteswap.hh"
using namespace std;
using namespace X86ISA;
template<class T>
void writeVal(T val, PortProxy& proxy, Addr &addr)
{
T guestVal = htog(val);
proxy.writeBlob(addr, (uint8_t *)&guestVal, sizeof(T));
addr += sizeof(T);
}
void X86ISA::E820Table::writeTo(PortProxy& proxy, Addr countAddr, Addr addr)
{
uint8_t e820Nr = entries.size();
// Make sure the number of entries isn't bigger than what the kernel
// would be capable of handling.
assert(e820Nr <= 128);
uint8_t guestE820Nr = htog(e820Nr);
proxy.writeBlob(countAddr, (uint8_t *)&guestE820Nr, sizeof(guestE820Nr));
for (int i = 0; i < e820Nr; i++) {
writeVal(entries[i]->addr, proxy, addr);
writeVal(entries[i]->size, proxy, addr);
writeVal(entries[i]->type, proxy, addr);
}
}
E820Table *
X86E820TableParams::create()
{
return new E820Table(this);
}
E820Entry *
X86E820EntryParams::create()
{
return new E820Entry(this);
}

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_BIOS_E820_HH__
#define __ARCH_X86_BIOS_E820_HH__
#include <vector>
#include "base/types.hh"
#include "params/X86E820Entry.hh"
#include "params/X86E820Table.hh"
#include "sim/sim_object.hh"
class PortProxy;
namespace X86ISA
{
class E820Entry : public SimObject
{
public:
Addr addr;
Addr size;
uint32_t type;
public:
typedef X86E820EntryParams Params;
E820Entry(Params *p) :
SimObject(p), addr(p->addr), size(p->size), type(p->range_type)
{}
};
class E820Table : public SimObject
{
public:
std::vector<E820Entry *> entries;
public:
typedef X86E820TableParams Params;
E820Table(Params *p) : SimObject(p), entries(p->entries)
{}
void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
};
}
#endif // __ARCH_X86_BIOS_E820_HH__

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/bios/intelmp.hh"
#include "arch/x86/isa_traits.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "mem/port_proxy.hh"
#include "sim/byteswap.hh"
// Config entry types
#include "params/X86IntelMPBaseConfigEntry.hh"
#include "params/X86IntelMPExtConfigEntry.hh"
// General table structures
#include "params/X86IntelMPConfigTable.hh"
#include "params/X86IntelMPFloatingPointer.hh"
// Base entry types
#include "params/X86IntelMPBus.hh"
#include "params/X86IntelMPIOAPIC.hh"
#include "params/X86IntelMPIOIntAssignment.hh"
#include "params/X86IntelMPLocalIntAssignment.hh"
#include "params/X86IntelMPProcessor.hh"
// Extended entry types
#include "params/X86IntelMPAddrSpaceMapping.hh"
#include "params/X86IntelMPBusHierarchy.hh"
#include "params/X86IntelMPCompatAddrSpaceMod.hh"
using namespace std;
const char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_";
template<class T>
uint8_t
writeOutField(PortProxy& proxy, Addr addr, T val)
{
uint64_t guestVal = X86ISA::htog(val);
proxy.writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
uint8_t checkSum = 0;
while(guestVal) {
checkSum += guestVal;
guestVal >>= 8;
}
return checkSum;
}
uint8_t
writeOutString(PortProxy& proxy, Addr addr, string str, int length)
{
char cleanedString[length + 1];
cleanedString[length] = 0;
if (str.length() > length) {
memcpy(cleanedString, str.c_str(), length);
warn("Intel MP configuration table string \"%s\" "
"will be truncated to \"%s\".\n", str, cleanedString);
} else {
memcpy(cleanedString, str.c_str(), str.length());
memset(cleanedString + str.length(), 0, length - str.length());
}
proxy.writeBlob(addr, (uint8_t *)(&cleanedString), length);
uint8_t checkSum = 0;
for (int i = 0; i < length; i++)
checkSum += cleanedString[i];
return checkSum;
}
Addr
X86ISA::IntelMP::FloatingPointer::writeOut(PortProxy& proxy, Addr addr)
{
// Make sure that either a config table is present or a default
// configuration was found but not both.
if (!tableAddr && !defaultConfig)
fatal("Either an MP configuration table or a default configuration "
"must be used.");
if (tableAddr && defaultConfig)
fatal("Both an MP configuration table and a default configuration "
"were set.");
uint8_t checkSum = 0;
proxy.writeBlob(addr, (uint8_t *)signature, 4);
for (int i = 0; i < 4; i++)
checkSum += signature[i];
checkSum += writeOutField(proxy, addr + 4, tableAddr);
// The length of the structure in paragraphs, aka 16 byte chunks.
uint8_t length = 1;
proxy.writeBlob(addr + 8, &length, 1);
checkSum += length;
proxy.writeBlob(addr + 9, &specRev, 1);
checkSum += specRev;
proxy.writeBlob(addr + 11, &defaultConfig, 1);
checkSum += defaultConfig;
uint32_t features2_5 = imcrPresent ? (1 << 7) : 0;
checkSum += writeOutField(proxy, addr + 12, features2_5);
checkSum = -checkSum;
proxy.writeBlob(addr + 10, &checkSum, 1);
return 16;
}
X86ISA::IntelMP::FloatingPointer::FloatingPointer(Params * p) :
SimObject(p), tableAddr(0), specRev(p->spec_rev),
defaultConfig(p->default_config), imcrPresent(p->imcr_present)
{}
X86ISA::IntelMP::FloatingPointer *
X86IntelMPFloatingPointerParams::create()
{
return new X86ISA::IntelMP::FloatingPointer(this);
}
Addr
X86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy& proxy,
Addr addr, uint8_t &checkSum)
{
proxy.writeBlob(addr, &type, 1);
checkSum += type;
return 1;
}
X86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(Params * p, uint8_t _type) :
SimObject(p), type(_type)
{}
Addr
X86ISA::IntelMP::ExtConfigEntry::writeOut(PortProxy& proxy,
Addr addr, uint8_t &checkSum)
{
proxy.writeBlob(addr, &type, 1);
checkSum += type;
proxy.writeBlob(addr + 1, &length, 1);
checkSum += length;
return 1;
}
X86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(Params * p,
uint8_t _type, uint8_t _length) :
SimObject(p), type(_type), length(_length)
{}
const char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP";
Addr
X86ISA::IntelMP::ConfigTable::writeOut(PortProxy& proxy, Addr addr)
{
uint8_t checkSum = 0;
proxy.writeBlob(addr, (uint8_t *)signature, 4);
for (int i = 0; i < 4; i++)
checkSum += signature[i];
// Base table length goes here but will be calculated later.
proxy.writeBlob(addr + 6, (uint8_t *)(&specRev), 1);
checkSum += specRev;
// The checksum goes here but is still being calculated.
checkSum += writeOutString(proxy, addr + 8, oemID, 8);
checkSum += writeOutString(proxy, addr + 16, productID, 12);
checkSum += writeOutField(proxy, addr + 28, oemTableAddr);
checkSum += writeOutField(proxy, addr + 32, oemTableSize);
checkSum += writeOutField(proxy, addr + 34, (uint16_t)baseEntries.size());
checkSum += writeOutField(proxy, addr + 36, localApic);
uint8_t reserved = 0;
proxy.writeBlob(addr + 43, &reserved, 1);
checkSum += reserved;
vector<BaseConfigEntry *>::iterator baseEnt;
uint16_t offset = 44;
for (baseEnt = baseEntries.begin();
baseEnt != baseEntries.end(); baseEnt++) {
offset += (*baseEnt)->writeOut(proxy, addr + offset, checkSum);
}
// We've found the end of the base table this point.
checkSum += writeOutField(proxy, addr + 4, offset);
vector<ExtConfigEntry *>::iterator extEnt;
uint16_t extOffset = 0;
uint8_t extCheckSum = 0;
for (extEnt = extEntries.begin();
extEnt != extEntries.end(); extEnt++) {
extOffset += (*extEnt)->writeOut(proxy,
addr + offset + extOffset, extCheckSum);
}
checkSum += writeOutField(proxy, addr + 40, extOffset);
extCheckSum = -extCheckSum;
checkSum += writeOutField(proxy, addr + 42, extCheckSum);
// And now, we finally have the whole check sum completed.
checkSum = -checkSum;
writeOutField(proxy, addr + 7, checkSum);
return offset + extOffset;
};
X86ISA::IntelMP::ConfigTable::ConfigTable(Params * p) : SimObject(p),
specRev(p->spec_rev), oemID(p->oem_id), productID(p->product_id),
oemTableAddr(p->oem_table_addr), oemTableSize(p->oem_table_size),
localApic(p->local_apic),
baseEntries(p->base_entries), extEntries(p->ext_entries)
{}
X86ISA::IntelMP::ConfigTable *
X86IntelMPConfigTableParams::create()
{
return new X86ISA::IntelMP::ConfigTable(this);
}
Addr
X86ISA::IntelMP::Processor::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
BaseConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 1, localApicID);
checkSum += writeOutField(proxy, addr + 2, localApicVersion);
checkSum += writeOutField(proxy, addr + 3, cpuFlags);
checkSum += writeOutField(proxy, addr + 4, cpuSignature);
checkSum += writeOutField(proxy, addr + 8, featureFlags);
uint32_t reserved = 0;
proxy.writeBlob(addr + 12, (uint8_t *)(&reserved), 4);
proxy.writeBlob(addr + 16, (uint8_t *)(&reserved), 4);
return 20;
}
X86ISA::IntelMP::Processor::Processor(Params * p) : BaseConfigEntry(p, 0),
localApicID(p->local_apic_id), localApicVersion(p->local_apic_version),
cpuFlags(0), cpuSignature(0), featureFlags(p->feature_flags)
{
if (p->enable)
cpuFlags |= (1 << 0);
if (p->bootstrap)
cpuFlags |= (1 << 1);
replaceBits(cpuSignature, 0, 3, p->stepping);
replaceBits(cpuSignature, 4, 7, p->model);
replaceBits(cpuSignature, 8, 11, p->family);
}
X86ISA::IntelMP::Processor *
X86IntelMPProcessorParams::create()
{
return new X86ISA::IntelMP::Processor(this);
}
Addr
X86ISA::IntelMP::Bus::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
BaseConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 1, busID);
checkSum += writeOutString(proxy, addr + 2, busType, 6);
return 8;
}
X86ISA::IntelMP::Bus::Bus(Params * p) : BaseConfigEntry(p, 1),
busID(p->bus_id), busType(p->bus_type)
{}
X86ISA::IntelMP::Bus *
X86IntelMPBusParams::create()
{
return new X86ISA::IntelMP::Bus(this);
}
Addr
X86ISA::IntelMP::IOAPIC::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
BaseConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 1, id);
checkSum += writeOutField(proxy, addr + 2, version);
checkSum += writeOutField(proxy, addr + 3, flags);
checkSum += writeOutField(proxy, addr + 4, address);
return 8;
}
X86ISA::IntelMP::IOAPIC::IOAPIC(Params * p) : BaseConfigEntry(p, 2),
id(p->id), version(p->version), flags(0), address(p->address)
{
if (p->enable)
flags |= 1;
}
X86ISA::IntelMP::IOAPIC *
X86IntelMPIOAPICParams::create()
{
return new X86ISA::IntelMP::IOAPIC(this);
}
Addr
X86ISA::IntelMP::IntAssignment::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
BaseConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 1, interruptType);
checkSum += writeOutField(proxy, addr + 2, flags);
checkSum += writeOutField(proxy, addr + 4, sourceBusID);
checkSum += writeOutField(proxy, addr + 5, sourceBusIRQ);
checkSum += writeOutField(proxy, addr + 6, destApicID);
checkSum += writeOutField(proxy, addr + 7, destApicIntIn);
return 8;
}
X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(Params * p) :
IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 3,
p->source_bus_id, p->source_bus_irq,
p->dest_io_apic_id, p->dest_io_apic_intin)
{}
X86ISA::IntelMP::IOIntAssignment *
X86IntelMPIOIntAssignmentParams::create()
{
return new X86ISA::IntelMP::IOIntAssignment(this);
}
X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(Params * p) :
IntAssignment(p, p->interrupt_type, p->polarity, p->trigger, 4,
p->source_bus_id, p->source_bus_irq,
p->dest_local_apic_id, p->dest_local_apic_intin)
{}
X86ISA::IntelMP::LocalIntAssignment *
X86IntelMPLocalIntAssignmentParams::create()
{
return new X86ISA::IntelMP::LocalIntAssignment(this);
}
Addr
X86ISA::IntelMP::AddrSpaceMapping::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
ExtConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 2, busID);
checkSum += writeOutField(proxy, addr + 3, addrType);
checkSum += writeOutField(proxy, addr + 4, addr);
checkSum += writeOutField(proxy, addr + 12, addrLength);
return length;
}
X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(Params * p) :
ExtConfigEntry(p, 128, 20),
busID(p->bus_id), addrType(p->address_type),
addr(p->address), addrLength(p->length)
{}
X86ISA::IntelMP::AddrSpaceMapping *
X86IntelMPAddrSpaceMappingParams::create()
{
return new X86ISA::IntelMP::AddrSpaceMapping(this);
}
Addr
X86ISA::IntelMP::BusHierarchy::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
ExtConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 2, busID);
checkSum += writeOutField(proxy, addr + 3, info);
checkSum += writeOutField(proxy, addr + 4, parentBus);
uint32_t reserved = 0;
proxy.writeBlob(addr + 5, (uint8_t *)(&reserved), 3);
return length;
}
X86ISA::IntelMP::BusHierarchy::BusHierarchy(Params * p) :
ExtConfigEntry(p, 129, 8),
busID(p->bus_id), info(0), parentBus(p->parent_bus)
{
if (p->subtractive_decode)
info |= 1;
}
X86ISA::IntelMP::BusHierarchy *
X86IntelMPBusHierarchyParams::create()
{
return new X86ISA::IntelMP::BusHierarchy(this);
}
Addr
X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(
PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
ExtConfigEntry::writeOut(proxy, addr, checkSum);
checkSum += writeOutField(proxy, addr + 2, busID);
checkSum += writeOutField(proxy, addr + 3, mod);
checkSum += writeOutField(proxy, addr + 4, rangeList);
return length;
}
X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(Params * p) :
ExtConfigEntry(p, 130, 8),
busID(p->bus_id), mod(0), rangeList(p->range_list)
{
if (p->add)
mod |= 1;
}
X86ISA::IntelMP::CompatAddrSpaceMod *
X86IntelMPCompatAddrSpaceModParams::create()
{
return new X86ISA::IntelMP::CompatAddrSpaceMod(this);
}

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_BIOS_INTELMP_HH__
#define __ARCH_X86_BIOS_INTELMP_HH__
#include <string>
#include <vector>
#include "base/bitfield.hh"
#include "enums/X86IntelMPAddressType.hh"
#include "enums/X86IntelMPInterruptType.hh"
#include "enums/X86IntelMPPolarity.hh"
#include "enums/X86IntelMPRangeList.hh"
#include "enums/X86IntelMPTriggerMode.hh"
#include "sim/sim_object.hh"
class PortProxy;
// Config entry types
struct X86IntelMPBaseConfigEntryParams;
struct X86IntelMPExtConfigEntryParams;
// General table structures
struct X86IntelMPConfigTableParams;
struct X86IntelMPFloatingPointerParams;
// Base entry types
struct X86IntelMPBusParams;
struct X86IntelMPIOAPICParams;
struct X86IntelMPIOIntAssignmentParams;
struct X86IntelMPLocalIntAssignmentParams;
struct X86IntelMPProcessorParams;
// Extended entry types
struct X86IntelMPAddrSpaceMappingParams;
struct X86IntelMPBusHierarchyParams;
struct X86IntelMPCompatAddrSpaceModParams;
namespace X86ISA
{
namespace IntelMP
{
class FloatingPointer : public SimObject
{
protected:
typedef X86IntelMPFloatingPointerParams Params;
uint32_t tableAddr;
uint8_t specRev;
uint8_t defaultConfig;
bool imcrPresent;
static const char signature[];
public:
Addr writeOut(PortProxy& proxy, Addr addr);
Addr getTableAddr()
{
return tableAddr;
}
void setTableAddr(Addr addr)
{
tableAddr = addr;
}
FloatingPointer(Params * p);
};
class BaseConfigEntry : public SimObject
{
protected:
typedef X86IntelMPBaseConfigEntryParams Params;
uint8_t type;
public:
virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
BaseConfigEntry(Params * p, uint8_t _type);
};
class ExtConfigEntry : public SimObject
{
protected:
typedef X86IntelMPExtConfigEntryParams Params;
uint8_t type;
uint8_t length;
public:
virtual Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
};
class ConfigTable : public SimObject
{
protected:
typedef X86IntelMPConfigTableParams Params;
static const char signature[];
uint8_t specRev;
std::string oemID;
std::string productID;
uint32_t oemTableAddr;
uint16_t oemTableSize;
uint32_t localApic;
std::vector<BaseConfigEntry *> baseEntries;
std::vector<ExtConfigEntry *> extEntries;
public:
Addr writeOut(PortProxy& proxy, Addr addr);
ConfigTable(Params * p);
};
class Processor : public BaseConfigEntry
{
protected:
typedef X86IntelMPProcessorParams Params;
uint8_t localApicID;
uint8_t localApicVersion;
uint8_t cpuFlags;
uint32_t cpuSignature;
uint32_t featureFlags;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
Processor(Params * p);
};
class Bus : public BaseConfigEntry
{
protected:
typedef X86IntelMPBusParams Params;
uint8_t busID;
std::string busType;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
Bus(Params * p);
};
class IOAPIC : public BaseConfigEntry
{
protected:
typedef X86IntelMPIOAPICParams Params;
uint8_t id;
uint8_t version;
uint8_t flags;
uint32_t address;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
IOAPIC(Params * p);
};
class IntAssignment : public BaseConfigEntry
{
protected:
uint8_t interruptType;
uint16_t flags;
uint8_t sourceBusID;
uint8_t sourceBusIRQ;
uint8_t destApicID;
uint8_t destApicIntIn;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
IntAssignment(X86IntelMPBaseConfigEntryParams * p,
Enums::X86IntelMPInterruptType _interruptType,
Enums::X86IntelMPPolarity polarity,
Enums::X86IntelMPTriggerMode trigger,
uint8_t _type,
uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
uint8_t _destApicID, uint8_t _destApicIntIn) :
BaseConfigEntry(p, _type),
interruptType(_interruptType), flags(0),
sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ),
destApicID(_destApicID), destApicIntIn(_destApicIntIn)
{
replaceBits(flags, 0, 1, polarity);
replaceBits(flags, 2, 3, trigger);
}
};
class IOIntAssignment : public IntAssignment
{
protected:
typedef X86IntelMPIOIntAssignmentParams Params;
public:
IOIntAssignment(Params * p);
};
class LocalIntAssignment : public IntAssignment
{
protected:
typedef X86IntelMPLocalIntAssignmentParams Params;
public:
LocalIntAssignment(Params * p);
};
class AddrSpaceMapping : public ExtConfigEntry
{
protected:
typedef X86IntelMPAddrSpaceMappingParams Params;
uint8_t busID;
uint8_t addrType;
uint64_t addr;
uint64_t addrLength;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
AddrSpaceMapping(Params * p);
};
class BusHierarchy : public ExtConfigEntry
{
protected:
typedef X86IntelMPBusHierarchyParams Params;
uint8_t busID;
uint8_t info;
uint8_t parentBus;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
BusHierarchy(Params * p);
};
class CompatAddrSpaceMod : public ExtConfigEntry
{
protected:
typedef X86IntelMPCompatAddrSpaceModParams Params;
uint8_t busID;
uint8_t mod;
uint32_t rangeList;
public:
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
CompatAddrSpaceMod(Params * p);
};
} //IntelMP
} //X86ISA
#endif

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/bios/smbios.hh"
#include "arch/x86/isa_traits.hh"
#include "base/types.hh"
#include "mem/port_proxy.hh"
#include "params/X86SMBiosBiosInformation.hh"
#include "params/X86SMBiosSMBiosStructure.hh"
#include "params/X86SMBiosSMBiosTable.hh"
#include "sim/byteswap.hh"
using namespace std;
const char X86ISA::SMBios::SMBiosTable::SMBiosHeader::anchorString[] = "_SM_";
const uint8_t X86ISA::SMBios::SMBiosTable::
SMBiosHeader::formattedArea[] = {0,0,0,0,0};
const uint8_t X86ISA::SMBios::SMBiosTable::
SMBiosHeader::entryPointLength = 0x1F;
const uint8_t X86ISA::SMBios::SMBiosTable::
SMBiosHeader::entryPointRevision = 0;
const char X86ISA::SMBios::SMBiosTable::
SMBiosHeader::IntermediateHeader::anchorString[] = "_DMI_";
template <class T>
uint64_t
composeBitVector(T vec)
{
uint64_t val = 0;
typename T::iterator vecIt;
for (vecIt = vec.begin(); vecIt != vec.end(); vecIt++) {
val |= (1 << (*vecIt));
}
return val;
}
uint16_t
X86ISA::SMBios::SMBiosStructure::writeOut(PortProxy& proxy, Addr addr)
{
proxy.writeBlob(addr, (uint8_t *)(&type), 1);
uint8_t length = getLength();
proxy.writeBlob(addr + 1, (uint8_t *)(&length), 1);
uint16_t handleGuest = X86ISA::htog(handle);
proxy.writeBlob(addr + 2, (uint8_t *)(&handleGuest), 2);
return length + getStringLength();
}
X86ISA::SMBios::SMBiosStructure::SMBiosStructure(Params * p, uint8_t _type) :
SimObject(p), type(_type), handle(0), stringFields(false)
{}
void
X86ISA::SMBios::SMBiosStructure::writeOutStrings(
PortProxy& proxy, Addr addr)
{
std::vector<std::string>::iterator it;
Addr offset = 0;
const uint8_t nullTerminator = 0;
// If there are string fields but none of them are used, that's a
// special case which is handled by this if.
if (strings.size() == 0 && stringFields) {
proxy.writeBlob(addr + offset, (uint8_t *)(&nullTerminator), 1);
offset++;
} else {
for (it = strings.begin(); it != strings.end(); it++) {
proxy.writeBlob(addr + offset,
(uint8_t *)it->c_str(), it->length() + 1);
offset += it->length() + 1;
}
}
proxy.writeBlob(addr + offset, (uint8_t *)(&nullTerminator), 1);
}
int
X86ISA::SMBios::SMBiosStructure::getStringLength()
{
int size = 0;
std::vector<std::string>::iterator it;
for (it = strings.begin(); it != strings.end(); it++) {
size += it->length() + 1;
}
return size + 1;
}
int
X86ISA::SMBios::SMBiosStructure::addString(string & newString)
{
stringFields = true;
// If a string is empty, treat it as not existing. The index for empty
// strings is 0.
if (newString.length() == 0)
return 0;
strings.push_back(newString);
return strings.size();
}
string
X86ISA::SMBios::SMBiosStructure::readString(int n)
{
assert(n > 0 && n <= strings.size());
return strings[n - 1];
}
void
X86ISA::SMBios::SMBiosStructure::setString(int n, std::string & newString)
{
assert(n > 0 && n <= strings.size());
strings[n - 1] = newString;
}
X86ISA::SMBios::BiosInformation::BiosInformation(Params * p) :
SMBiosStructure(p, Type),
startingAddrSegment(p->starting_addr_segment),
romSize(p->rom_size),
majorVer(p->major), minorVer(p->minor),
embContFirmwareMajor(p->emb_cont_firmware_major),
embContFirmwareMinor(p->emb_cont_firmware_minor)
{
vendor = addString(p->vendor);
version = addString(p->version);
releaseDate = addString(p->release_date);
characteristics = composeBitVector(p->characteristics);
characteristicExtBytes =
composeBitVector(p->characteristic_ext_bytes);
}
uint16_t
X86ISA::SMBios::BiosInformation::writeOut(PortProxy& proxy, Addr addr)
{
uint8_t size = SMBiosStructure::writeOut(proxy, addr);
proxy.writeBlob(addr + 0x4, (uint8_t *)(&vendor), 1);
proxy.writeBlob(addr + 0x5, (uint8_t *)(&version), 1);
uint16_t startingAddrSegmentGuest = X86ISA::htog(startingAddrSegment);
proxy.writeBlob(addr + 0x6, (uint8_t *)(&startingAddrSegmentGuest), 2);
proxy.writeBlob(addr + 0x8, (uint8_t *)(&releaseDate), 1);
proxy.writeBlob(addr + 0x9, (uint8_t *)(&romSize), 1);
uint64_t characteristicsGuest = X86ISA::htog(characteristics);
proxy.writeBlob(addr + 0xA, (uint8_t *)(&characteristicsGuest), 8);
uint16_t characteristicExtBytesGuest =
X86ISA::htog(characteristicExtBytes);
proxy.writeBlob(addr + 0x12, (uint8_t *)(&characteristicExtBytesGuest), 2);
proxy.writeBlob(addr + 0x14, (uint8_t *)(&majorVer), 1);
proxy.writeBlob(addr + 0x15, (uint8_t *)(&minorVer), 1);
proxy.writeBlob(addr + 0x16, (uint8_t *)(&embContFirmwareMajor), 1);
proxy.writeBlob(addr + 0x17, (uint8_t *)(&embContFirmwareMinor), 1);
writeOutStrings(proxy, addr + getLength());
return size;
}
X86ISA::SMBios::SMBiosTable::SMBiosTable(Params * p) :
SimObject(p), structures(p->structures)
{
smbiosHeader.majorVersion = p->major_version;
smbiosHeader.minorVersion = p->minor_version;
assert(p->major_version <= 9);
assert(p->minor_version <= 9);
smbiosHeader.intermediateHeader.smbiosBCDRevision =
(p->major_version << 4) | p->minor_version;
}
void
X86ISA::SMBios::SMBiosTable::writeOut(PortProxy& proxy, Addr addr,
Addr &headerSize, Addr &structSize)
{
headerSize = 0x1F;
/*
* The main header
*/
uint8_t mainChecksum = 0;
proxy.writeBlob(addr, (uint8_t *)smbiosHeader.anchorString, 4);
for (int i = 0; i < 4; i++)
mainChecksum += smbiosHeader.anchorString[i];
// The checksum goes here, but we're figuring it out as we go.
proxy.writeBlob(addr + 0x5,
(uint8_t *)(&smbiosHeader.entryPointLength), 1);
mainChecksum += smbiosHeader.entryPointLength;
proxy.writeBlob(addr + 0x6,
(uint8_t *)(&smbiosHeader.majorVersion), 1);
mainChecksum += smbiosHeader.majorVersion;
proxy.writeBlob(addr + 0x7,
(uint8_t *)(&smbiosHeader.minorVersion), 1);
mainChecksum += smbiosHeader.minorVersion;
// Maximum structure size goes here, but we'll figure it out later.
proxy.writeBlob(addr + 0xA,
(uint8_t *)(&smbiosHeader.entryPointRevision), 1);
mainChecksum += smbiosHeader.entryPointRevision;
proxy.writeBlob(addr + 0xB,
(uint8_t *)(&smbiosHeader.formattedArea), 5);
for (int i = 0; i < 5; i++)
mainChecksum += smbiosHeader.formattedArea[i];
/*
* The intermediate header
*/
uint8_t intChecksum = 0;
proxy.writeBlob(addr + 0x10,
(uint8_t *)smbiosHeader.intermediateHeader.anchorString, 5);
for (int i = 0; i < 5; i++)
intChecksum += smbiosHeader.intermediateHeader.anchorString[i];
// The checksum goes here, but we're figuring it out as we go.
// Then the length of the structure table which we'll find later
uint32_t tableAddrGuest =
X86ISA::htog(smbiosHeader.intermediateHeader.tableAddr);
proxy.writeBlob(addr + 0x18, (uint8_t *)(&tableAddrGuest), 4);
for (int i = 0; i < 4; i++) {
intChecksum += tableAddrGuest;
tableAddrGuest >>= 8;
}
uint16_t numStructs = X86ISA::gtoh(structures.size());
proxy.writeBlob(addr + 0x1C, (uint8_t *)(&numStructs), 2);
for (int i = 0; i < 2; i++) {
intChecksum += numStructs;
numStructs >>= 8;
}
proxy.writeBlob(addr + 0x1E,
(uint8_t *)(&smbiosHeader.intermediateHeader.smbiosBCDRevision),
1);
intChecksum += smbiosHeader.intermediateHeader.smbiosBCDRevision;
/*
* Structure table
*/
Addr base = smbiosHeader.intermediateHeader.tableAddr;
Addr offset = 0;
uint16_t maxSize = 0;
std::vector<SMBiosStructure *>::iterator it;
for (it = structures.begin(); it != structures.end(); it++) {
uint16_t size = (*it)->writeOut(proxy, base + offset);
if (size > maxSize)
maxSize = size;
offset += size;
}
structSize = offset;
/*
* Header
*/
maxSize = X86ISA::htog(maxSize);
proxy.writeBlob(addr + 0x8, (uint8_t *)(&maxSize), 2);
for (int i = 0; i < 2; i++) {
mainChecksum += maxSize;
maxSize >>= 8;
}
// Set the checksum
mainChecksum = -mainChecksum;
proxy.writeBlob(addr + 0x4, (uint8_t *)(&mainChecksum), 1);
/*
* Intermediate header
*/
uint16_t tableSize = offset;
tableSize = X86ISA::htog(tableSize);
proxy.writeBlob(addr + 0x16, (uint8_t *)(&tableSize), 2);
for (int i = 0; i < 2; i++) {
intChecksum += tableSize;
tableSize >>= 8;
}
intChecksum = -intChecksum;
proxy.writeBlob(addr + 0x15, (uint8_t *)(&intChecksum), 1);
}
X86ISA::SMBios::BiosInformation *
X86SMBiosBiosInformationParams::create()
{
return new X86ISA::SMBios::BiosInformation(this);
}
X86ISA::SMBios::SMBiosTable *
X86SMBiosSMBiosTableParams::create()
{
return new X86ISA::SMBios::SMBiosTable(this);
}

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/*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_BIOS_SMBIOS_HH__
#define __ARCH_X86_BIOS_SMBIOS_HH__
#include <string>
#include <vector>
#include "base/types.hh"
#include "enums/Characteristic.hh"
#include "enums/ExtCharacteristic.hh"
#include "sim/sim_object.hh"
class PortProxy;
struct X86SMBiosBiosInformationParams;
struct X86SMBiosSMBiosStructureParams;
struct X86SMBiosSMBiosTableParams;
namespace X86ISA
{
namespace SMBios
{
class SMBiosStructure : public SimObject
{
protected:
typedef X86SMBiosSMBiosStructureParams Params;
public:
virtual
~SMBiosStructure()
{}
// Offset 00h, 1 byte
uint8_t type;
// Offset 01h, 1 byte
//Length: computed when written to memory.
// Offset 02h, 2 bytes
uint16_t handle;
virtual uint8_t
getLength()
{
// This is the size of a structure with nothing but the header
return 4;
}
virtual uint16_t writeOut(PortProxy& proxy, Addr addr);
protected:
bool stringFields;
SMBiosStructure(Params * p, uint8_t _type);
std::vector<std::string> strings;
void writeOutStrings(PortProxy& proxy, Addr addr);
int getStringLength();
public:
int addString(std::string & newString);
std::string readString(int n);
void setString(int n, std::string & newString);
};
class BiosInformation : public SMBiosStructure
{
protected:
const static uint8_t Type = 0;
typedef X86SMBiosBiosInformationParams Params;
public:
// Offset 04h, 1 byte
uint8_t vendor;
// Offset 05h, 1 byte
uint8_t version;
// Offset 06h, 2 bytes
uint16_t startingAddrSegment;
// Offset 08h, 1 byte
uint8_t releaseDate;
// Offset 09h, 1 byte
uint8_t romSize;
// Offset 0Ah, 8 bytes
//See tables in 3.3.1 in the SMBios 2.5 spec from the DMTF for
//bit definitions.
uint64_t characteristics;
// Offset 12h, 2 bytes
uint16_t characteristicExtBytes;
// Offset 14h, 1 byte
uint8_t majorVer;
// Offset 15h, 1 byte
uint8_t minorVer;
// Offset 16h, 1 byte
uint8_t embContFirmwareMajor;
// Offset 17h, 1 byte
uint8_t embContFirmwareMinor;
BiosInformation(Params * p);
uint8_t getLength() { return 0x18; }
uint16_t writeOut(PortProxy& proxy, Addr addr);
};
class SMBiosTable : public SimObject
{
protected:
typedef X86SMBiosSMBiosTableParams Params;
struct SMBiosHeader
{
SMBiosHeader()
{}
// Offset 00h, 4 bytes
static const char anchorString[];
// Offset 04h, 1 byte
//Checksum: computed when written to memory.
// Offset 05h, 1 byte
static const uint8_t entryPointLength;
// Offset 06h, 1 byte
uint8_t majorVersion;
// Offset 07h, 1 byte
uint8_t minorVersion;
// Offset 08h, 2 bytes
//Maximum structure size: computed when written to memory.
// Offset 0Ah, 1 byte
static const uint8_t entryPointRevision;
// Offset 0Bh, 5 bytes
static const uint8_t formattedArea[5];
// Offset 10h, 15 bytes
struct IntermediateHeader
{
IntermediateHeader() : tableAddr(0)
{}
// Offset 10h, 5 bytes
static const char anchorString[];
// Offset 15h, 1 byte
//Checksum: computed when written to memory.
// Offset 16h, 2 bytes
//Length of the structure table in bytes: computed when
//written to memory.
// Offset 18h, 4 bytes
uint32_t tableAddr;
// Offset 1Ch, 2 bytes
//Number of structures: computed when written to memory
// Offset 1Eh, 1 byte
uint8_t smbiosBCDRevision;
} intermediateHeader;
} smbiosHeader;
std::vector<SMBiosStructure *> structures;
public:
SMBiosTable(Params * p);
Addr getTableAddr()
{
return smbiosHeader.intermediateHeader.tableAddr;
}
void setTableAddr(Addr addr)
{
smbiosHeader.intermediateHeader.tableAddr = addr;
}
void writeOut(PortProxy& proxy, Addr addr,
Addr &headerSize, Addr &structSize);
};
} //SMBios
} //X86ISA
#endif

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/*
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/cpuid.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
namespace X86ISA {
enum StandardCpuidFunction {
VendorAndLargestStdFunc,
FamilyModelStepping,
NumStandardCpuidFuncs
};
enum ExtendedCpuidFunctions {
VendorAndLargestExtFunc,
FamilyModelSteppingBrandFeatures,
NameString1,
NameString2,
NameString3,
L1CacheAndTLB,
L2L3CacheAndL2TLB,
APMInfo,
/*
* The following are defined by the spec but not yet implemented
*/
/* LongModeAddressSize,
// Function 9 is reserved
SVMInfo = 10,
// Functions 11-24 are reserved
TLB1GBPageInfo = 25,
PerformanceInfo,*/
NumExtendedCpuidFuncs
};
static const int vendorStringSize = 13;
static const char vendorString[vendorStringSize] = "M5 Simulator";
static const int nameStringSize = 48;
static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
uint64_t
stringToRegister(const char *str)
{
uint64_t reg = 0;
for (int pos = 3; pos >=0; pos--) {
reg <<= 8;
reg |= str[pos];
}
return reg;
}
bool
doCpuid(ThreadContext * tc, uint32_t function,
uint32_t index, CpuidResult &result)
{
uint16_t family = bits(function, 31, 16);
uint16_t funcNum = bits(function, 15, 0);
if (family == 0x8000) {
// The extended functions
switch (funcNum) {
case VendorAndLargestExtFunc:
assert(vendorStringSize >= 12);
result = CpuidResult(
0x80000000 + NumExtendedCpuidFuncs - 1,
stringToRegister(vendorString),
stringToRegister(vendorString + 4),
stringToRegister(vendorString + 8));
break;
case FamilyModelSteppingBrandFeatures:
result = CpuidResult(0x00020f51, 0x00000405,
0xe3d3fbff, 0x00000001);
break;
case NameString1:
case NameString2:
case NameString3:
{
// Zero fill anything beyond the end of the string. This
// should go away once the string is a vetted parameter.
char cleanName[nameStringSize];
memset(cleanName, '\0', nameStringSize);
strncpy(cleanName, nameString, nameStringSize);
int offset = (funcNum - NameString1) * 16;
assert(nameStringSize >= offset + 16);
result = CpuidResult(
stringToRegister(cleanName + offset + 0),
stringToRegister(cleanName + offset + 4),
stringToRegister(cleanName + offset + 12),
stringToRegister(cleanName + offset + 8));
}
break;
case L1CacheAndTLB:
result = CpuidResult(0xff08ff08, 0xff20ff20,
0x40020140, 0x40020140);
break;
case L2L3CacheAndL2TLB:
result = CpuidResult(0x00000000, 0x42004200,
0x00000000, 0x04008140);
break;
case APMInfo:
result = CpuidResult(0x80000018, 0x68747541,
0x69746e65, 0x444d4163);
break;
/* case LongModeAddressSize:
case SVMInfo:
case TLB1GBPageInfo:
case PerformanceInfo:*/
default:
return false;
}
} else if(family == 0x0000) {
// The standard functions
switch (funcNum) {
case VendorAndLargestStdFunc:
assert(vendorStringSize >= 12);
result = CpuidResult(
NumStandardCpuidFuncs - 1,
stringToRegister(vendorString),
stringToRegister(vendorString + 4),
stringToRegister(vendorString + 8));
break;
case FamilyModelStepping:
result = CpuidResult(0x00020f51, 0000000405,
0xe7d3fbff, 0x00000001);
break;
default:
return false;
}
}
return true;
}
} // namespace X86ISA

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/*
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_CPUID_HH__
#define __ARCH_X86_CPUID_HH__
#include "base/types.hh"
class ThreadContext;
namespace X86ISA
{
struct CpuidResult
{
uint64_t rax;
uint64_t rbx;
uint64_t rcx;
uint64_t rdx;
// These are not in alphebetical order on purpose. The order reflects
// how the CPUID orders the registers when it returns results.
CpuidResult(uint64_t _rax, uint64_t _rbx,
uint64_t _rdx, uint64_t _rcx) :
rax(_rax), rbx(_rbx), rcx(_rcx), rdx(_rdx)
{}
CpuidResult()
{}
};
bool doCpuid(ThreadContext * tc, uint32_t function,
uint32_t index, CpuidResult &result);
} // namespace X86ISA
#endif

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/*
* Copyright (c) 2011 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/decoder.hh"
#include "arch/x86/regs/misc.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
#include "debug/Decoder.hh"
namespace X86ISA
{
void Decoder::doReset()
{
origPC = basePC + offset;
DPRINTF(Decoder, "Setting origPC to %#x\n", origPC);
emi.rex = 0;
emi.legacy = 0;
emi.opcode.num = 0;
emi.opcode.op = 0;
emi.opcode.prefixA = emi.opcode.prefixB = 0;
immediateCollected = 0;
emi.immediate = 0;
emi.displacement = 0;
emi.dispSize = 0;
emi.modRM = 0;
emi.sib = 0;
m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
emi.mode.mode = m5Reg.mode;
emi.mode.submode = m5Reg.submode;
}
void Decoder::process()
{
//This function drives the decoder state machine.
//Some sanity checks. You shouldn't try to process more bytes if
//there aren't any, and you shouldn't overwrite an already
//decoder ExtMachInst.
assert(!outOfBytes);
assert(!instDone);
//While there's still something to do...
while(!instDone && !outOfBytes)
{
uint8_t nextByte = getNextByte();
switch(state)
{
case ResetState:
doReset();
state = PrefixState;
case PrefixState:
state = doPrefixState(nextByte);
break;
case OpcodeState:
state = doOpcodeState(nextByte);
break;
case ModRMState:
state = doModRMState(nextByte);
break;
case SIBState:
state = doSIBState(nextByte);
break;
case DisplacementState:
state = doDisplacementState();
break;
case ImmediateState:
state = doImmediateState();
break;
case ErrorState:
panic("Went to the error state in the decoder.\n");
default:
panic("Unrecognized state! %d\n", state);
}
}
}
//Either get a prefix and record it in the ExtMachInst, or send the
//state machine on to get the opcode(s).
Decoder::State Decoder::doPrefixState(uint8_t nextByte)
{
uint8_t prefix = Prefixes[nextByte];
State nextState = PrefixState;
// REX prefixes are only recognized in 64 bit mode.
if (prefix == RexPrefix && emi.mode.submode != SixtyFourBitMode)
prefix = 0;
if (prefix)
consumeByte();
switch(prefix)
{
//Operand size override prefixes
case OperandSizeOverride:
DPRINTF(Decoder, "Found operand size override prefix.\n");
emi.legacy.op = true;
break;
case AddressSizeOverride:
DPRINTF(Decoder, "Found address size override prefix.\n");
emi.legacy.addr = true;
break;
//Segment override prefixes
case CSOverride:
case DSOverride:
case ESOverride:
case FSOverride:
case GSOverride:
case SSOverride:
DPRINTF(Decoder, "Found segment override.\n");
emi.legacy.seg = prefix;
break;
case Lock:
DPRINTF(Decoder, "Found lock prefix.\n");
emi.legacy.lock = true;
break;
case Rep:
DPRINTF(Decoder, "Found rep prefix.\n");
emi.legacy.rep = true;
break;
case Repne:
DPRINTF(Decoder, "Found repne prefix.\n");
emi.legacy.repne = true;
break;
case RexPrefix:
DPRINTF(Decoder, "Found Rex prefix %#x.\n", nextByte);
emi.rex = nextByte;
break;
case 0:
nextState = OpcodeState;
break;
default:
panic("Unrecognized prefix %#x\n", nextByte);
}
return nextState;
}
//Load all the opcodes (currently up to 2) and then figure out
//what immediate and/or ModRM is needed.
Decoder::State Decoder::doOpcodeState(uint8_t nextByte)
{
State nextState = ErrorState;
emi.opcode.num++;
//We can't handle 3+ byte opcodes right now
assert(emi.opcode.num < 4);
consumeByte();
if(emi.opcode.num == 1 && nextByte == 0x0f)
{
nextState = OpcodeState;
DPRINTF(Decoder, "Found two byte opcode.\n");
emi.opcode.prefixA = nextByte;
}
else if(emi.opcode.num == 2 && (nextByte == 0x38 || nextByte == 0x3A))
{
nextState = OpcodeState;
DPRINTF(Decoder, "Found three byte opcode.\n");
emi.opcode.prefixB = nextByte;
}
else
{
DPRINTF(Decoder, "Found opcode %#x.\n", nextByte);
emi.opcode.op = nextByte;
//Figure out the effective operand size. This can be overriden to
//a fixed value at the decoder level.
int logOpSize;
if (emi.rex.w)
logOpSize = 3; // 64 bit operand size
else if (emi.legacy.op)
logOpSize = m5Reg.altOp;
else
logOpSize = m5Reg.defOp;
//Set the actual op size
emi.opSize = 1 << logOpSize;
//Figure out the effective address size. This can be overriden to
//a fixed value at the decoder level.
int logAddrSize;
if(emi.legacy.addr)
logAddrSize = m5Reg.altAddr;
else
logAddrSize = m5Reg.defAddr;
//Set the actual address size
emi.addrSize = 1 << logAddrSize;
//Figure out the effective stack width. This can be overriden to
//a fixed value at the decoder level.
emi.stackSize = 1 << m5Reg.stack;
//Figure out how big of an immediate we'll retreive based
//on the opcode.
int immType = ImmediateType[emi.opcode.num - 1][nextByte];
if (emi.opcode.num == 1 && nextByte >= 0xA0 && nextByte <= 0xA3)
immediateSize = SizeTypeToSize[logAddrSize - 1][immType];
else
immediateSize = SizeTypeToSize[logOpSize - 1][immType];
//Determine what to expect next
if (UsesModRM[emi.opcode.num - 1][nextByte]) {
nextState = ModRMState;
} else {
if(immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
nextState = ResetState;
}
}
}
return nextState;
}
//Get the ModRM byte and determine what displacement, if any, there is.
//Also determine whether or not to get the SIB byte, displacement, or
//immediate next.
Decoder::State Decoder::doModRMState(uint8_t nextByte)
{
State nextState = ErrorState;
ModRM modRM;
modRM = nextByte;
DPRINTF(Decoder, "Found modrm byte %#x.\n", nextByte);
if (m5Reg.defOp == 1) {
//figure out 16 bit displacement size
if ((modRM.mod == 0 && modRM.rm == 6) || modRM.mod == 2)
displacementSize = 2;
else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
} else {
//figure out 32/64 bit displacement size
if ((modRM.mod == 0 && modRM.rm == 5) || modRM.mod == 2)
displacementSize = 4;
else if (modRM.mod == 1)
displacementSize = 1;
else
displacementSize = 0;
}
// The "test" instruction in group 3 needs an immediate, even though
// the other instructions with the same actual opcode don't.
if (emi.opcode.num == 1 && (modRM.reg & 0x6) == 0) {
if (emi.opcode.op == 0xF6)
immediateSize = 1;
else if (emi.opcode.op == 0xF7)
immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
}
//If there's an SIB, get that next.
//There is no SIB in 16 bit mode.
if (modRM.rm == 4 && modRM.mod != 3) {
// && in 32/64 bit mode)
nextState = SIBState;
} else if(displacementSize) {
nextState = DisplacementState;
} else if(immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
nextState = ResetState;
}
//The ModRM byte is consumed no matter what
consumeByte();
emi.modRM = modRM;
return nextState;
}
//Get the SIB byte. We don't do anything with it at this point, other
//than storing it in the ExtMachInst. Determine if we need to get a
//displacement or immediate next.
Decoder::State Decoder::doSIBState(uint8_t nextByte)
{
State nextState = ErrorState;
emi.sib = nextByte;
DPRINTF(Decoder, "Found SIB byte %#x.\n", nextByte);
consumeByte();
if (emi.modRM.mod == 0 && emi.sib.base == 5)
displacementSize = 4;
if (displacementSize) {
nextState = DisplacementState;
} else if(immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
nextState = ResetState;
}
return nextState;
}
//Gather up the displacement, or at least as much of it
//as we can get.
Decoder::State Decoder::doDisplacementState()
{
State nextState = ErrorState;
getImmediate(immediateCollected,
emi.displacement,
displacementSize);
DPRINTF(Decoder, "Collecting %d byte displacement, got %d bytes.\n",
displacementSize, immediateCollected);
if(displacementSize == immediateCollected) {
//Reset this for other immediates.
immediateCollected = 0;
//Sign extend the displacement
switch(displacementSize)
{
case 1:
emi.displacement = sext<8>(emi.displacement);
break;
case 2:
emi.displacement = sext<16>(emi.displacement);
break;
case 4:
emi.displacement = sext<32>(emi.displacement);
break;
default:
panic("Undefined displacement size!\n");
}
DPRINTF(Decoder, "Collected displacement %#x.\n",
emi.displacement);
if(immediateSize) {
nextState = ImmediateState;
} else {
instDone = true;
nextState = ResetState;
}
emi.dispSize = displacementSize;
}
else
nextState = DisplacementState;
return nextState;
}
//Gather up the immediate, or at least as much of it
//as we can get
Decoder::State Decoder::doImmediateState()
{
State nextState = ErrorState;
getImmediate(immediateCollected,
emi.immediate,
immediateSize);
DPRINTF(Decoder, "Collecting %d byte immediate, got %d bytes.\n",
immediateSize, immediateCollected);
if(immediateSize == immediateCollected)
{
//Reset this for other immediates.
immediateCollected = 0;
//XXX Warning! The following is an observed pattern and might
//not always be true!
//Instructions which use 64 bit operands but 32 bit immediates
//need to have the immediate sign extended to 64 bits.
//Instructions which use true 64 bit immediates won't be
//affected, and instructions that use true 32 bit immediates
//won't notice.
switch(immediateSize)
{
case 4:
emi.immediate = sext<32>(emi.immediate);
break;
case 1:
emi.immediate = sext<8>(emi.immediate);
}
DPRINTF(Decoder, "Collected immediate %#x.\n",
emi.immediate);
instDone = true;
nextState = ResetState;
}
else
nextState = ImmediateState;
return nextState;
}
DecodeCache::InstMap Decoder::instMap;
DecodeCache::AddrMap<StaticInstPtr> Decoder::decodePages;
StaticInstPtr
Decoder::decode(ExtMachInst mach_inst, Addr addr)
{
StaticInstPtr &si = decodePages.lookup(addr);
if (si && (si->machInst == mach_inst))
return si;
DecodeCache::InstMap::iterator iter = instMap.find(mach_inst);
if (iter != instMap.end()) {
si = iter->second;
return si;
}
si = decodeInst(mach_inst);
instMap[mach_inst] = si;
return si;
}
}

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/*
* Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_DECODER_HH__
#define __ARCH_X86_DECODER_HH__
#include <cassert>
#include "arch/x86/regs/misc.hh"
#include "arch/x86/types.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/decode_cache.hh"
#include "cpu/static_inst.hh"
#include "debug/Decoder.hh"
class ThreadContext;
namespace X86ISA
{
class Decoder
{
private:
//These are defined and documented in decoder_tables.cc
static const uint8_t Prefixes[256];
static const uint8_t UsesModRM[2][256];
static const uint8_t ImmediateType[2][256];
static const uint8_t SizeTypeToSize[3][10];
protected:
ThreadContext * tc;
//The bytes to be predecoded
MachInst fetchChunk;
//The pc of the start of fetchChunk
Addr basePC;
//The pc the current instruction started at
Addr origPC;
//The offset into fetchChunk of current processing
int offset;
//The extended machine instruction being generated
ExtMachInst emi;
HandyM5Reg m5Reg;
inline uint8_t getNextByte()
{
return ((uint8_t *)&fetchChunk)[offset];
}
void getImmediate(int &collected, uint64_t &current, int size)
{
//Figure out how many bytes we still need to get for the
//immediate.
int toGet = size - collected;
//Figure out how many bytes are left in our "buffer"
int remaining = sizeof(MachInst) - offset;
//Get as much as we need, up to the amount available.
toGet = toGet > remaining ? remaining : toGet;
//Shift the bytes we want to be all the way to the right
uint64_t partialImm = fetchChunk >> (offset * 8);
//Mask off what we don't want
partialImm &= mask(toGet * 8);
//Shift it over to overlay with our displacement.
partialImm <<= (immediateCollected * 8);
//Put it into our displacement
current |= partialImm;
//Update how many bytes we've collected.
collected += toGet;
consumeBytes(toGet);
}
inline void consumeByte()
{
offset++;
assert(offset <= sizeof(MachInst));
if(offset == sizeof(MachInst))
outOfBytes = true;
}
inline void consumeBytes(int numBytes)
{
offset += numBytes;
assert(offset <= sizeof(MachInst));
if(offset == sizeof(MachInst))
outOfBytes = true;
}
void doReset();
//State machine state
protected:
//Whether or not we're out of bytes
bool outOfBytes;
//Whether we've completed generating an ExtMachInst
bool instDone;
//The size of the displacement value
int displacementSize;
//The size of the immediate value
int immediateSize;
//This is how much of any immediate value we've gotten. This is used
//for both the actual immediate and the displacement.
int immediateCollected;
enum State {
ResetState,
PrefixState,
OpcodeState,
ModRMState,
SIBState,
DisplacementState,
ImmediateState,
//We should never get to this state. Getting here is an error.
ErrorState
};
State state;
//Functions to handle each of the states
State doPrefixState(uint8_t);
State doOpcodeState(uint8_t);
State doModRMState(uint8_t);
State doSIBState(uint8_t);
State doDisplacementState();
State doImmediateState();
public:
Decoder(ThreadContext * _tc) :
tc(_tc), basePC(0), origPC(0), offset(0),
outOfBytes(true), instDone(false),
state(ResetState)
{
memset(&emi, 0, sizeof(emi));
emi.mode.mode = LongMode;
emi.mode.submode = SixtyFourBitMode;
m5Reg = 0;
}
void reset()
{
state = ResetState;
}
ThreadContext * getTC()
{
return tc;
}
void setTC(ThreadContext * _tc)
{
tc = _tc;
}
void process();
//Use this to give data to the decoder. This should be used
//when there is control flow.
void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
{
DPRINTF(Decoder, "Getting more bytes.\n");
basePC = fetchPC;
offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
fetchChunk = data;
outOfBytes = false;
process();
}
bool needMoreBytes()
{
return outOfBytes;
}
bool instReady()
{
return instDone;
}
void
updateNPC(X86ISA::PCState &nextPC)
{
if (!nextPC.size()) {
int size = basePC + offset - origPC;
DPRINTF(Decoder,
"Calculating the instruction size: "
"basePC: %#x offset: %#x origPC: %#x size: %d\n",
basePC, offset, origPC, size);
nextPC.size(size);
nextPC.npc(nextPC.pc() + size);
}
}
protected:
/// Caching for decoded instruction objects.
static DecodeCache::InstMap instMap;
static DecodeCache::AddrMap<StaticInstPtr> decodePages;
public:
StaticInstPtr decodeInst(ExtMachInst mach_inst);
/// Decode a machine instruction.
/// @param mach_inst The binary instruction to decode.
/// @retval A pointer to the corresponding StaticInst object.
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
StaticInstPtr
decode(X86ISA::PCState &nextPC)
{
if (!instDone)
return NULL;
instDone = false;
updateNPC(nextPC);
return decode(emi, origPC);
}
};
} // namespace X86ISA
#endif // __ARCH_X86_DECODER_HH__

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/*
* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/decoder.hh"
#include "arch/x86/types.hh"
namespace X86ISA
{
const uint8_t CS = CSOverride;
const uint8_t DS = DSOverride;
const uint8_t ES = ESOverride;
const uint8_t FS = FSOverride;
const uint8_t GS = GSOverride;
const uint8_t SS = SSOverride;
const uint8_t OO = OperandSizeOverride;
const uint8_t AO = AddressSizeOverride;
const uint8_t LO = Lock;
const uint8_t RE = Rep;
const uint8_t RN = Repne;
const uint8_t RX = RexPrefix;
//This table identifies whether a byte is a prefix, and if it is,
//which prefix it is.
const uint8_t Decoder::Prefixes[256] =
{ //LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 1*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 2*/ 0 , 0 , 0 , 0 , 0 , 0 , ES, 0 , 0 , 0 , 0 , 0 , 0 , 0 , CS, 0,
/* 3*/ 0 , 0 , 0 , 0 , 0 , 0 , SS, 0 , 0 , 0 , 0 , 0 , 0 , 0 , DS, 0,
/* 4*/ RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX, RX,
/* 5*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 6*/ 0 , 0 , 0 , 0 , FS, GS, OO, AO, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 7*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 8*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 9*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* A*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* B*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* C*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* D*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* E*/ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* F*/ LO, 0 , RN, RE, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
};
//This table identifies whether a particular opcode uses the ModRM byte
const uint8_t Decoder::UsesModRM[2][256] =
{//For one byte instructions
{ //LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0,
/* 1 */ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0,
/* 2 */ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0,
/* 3 */ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0,
/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 6 */ 0 , 0 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 1 , 0 , 1 , 0 , 0 , 0 , 0,
/* 7 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 8 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* A */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* C */ 1 , 1 , 0 , 0 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* D */ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 1
},
//For two byte instructions
{ //LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 1 , 0 , 1,
/* 1 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* 2 */ 1 , 1 , 1 , 1 , 1 , 0 , 1 , 0 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 4 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* 5 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* 6 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* 7 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 1 , 1 , 1 , 1,
/* 8 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* 9 */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* A */ 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 1 , 1 , 1 , 1 , 1,
/* B */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 1 , 1 , 1 , 1 , 1 , 1,
/* C */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0,
/* D */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* E */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1,
/* F */ 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 1 , 0
}
};
enum SizeType {
NoImm,
NI = NoImm,
ByteImm,
BY = ByteImm,
WordImm,
WO = WordImm,
DWordImm,
DW = DWordImm,
QWordImm,
QW = QWordImm,
OWordImm,
OW = OWordImm,
VWordImm,
VW = VWordImm,
ZWordImm,
ZW = ZWordImm,
//The enter instruction takes -2- immediates for a total of 3 bytes
Enter,
EN = Enter,
Pointer,
PO = Pointer
};
const uint8_t Decoder::SizeTypeToSize[3][10] =
{
// noimm byte word dword qword oword vword zword enter pointer
{0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit
{0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit
{0, 1, 2, 4, 8, 16, 8, 4, 3, 0 } //64 bit
};
//This table determines the immediate type. The first index is the
//number of bytes in the instruction, and the second is the meaningful
//byte of the opcode. I didn't use the NI constant here for the sake
//of clarity.
const uint8_t Decoder::ImmediateType[2][256] =
{//For one byte instructions
{ //LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 , 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 ,
/* 1 */ 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 , 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 ,
/* 2 */ 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 , 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 ,
/* 3 */ 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 , 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 ,
/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , ZW, ZW, BY, BY, 0 , 0 , 0 , 0 ,
/* 7 */ BY, BY, BY, BY, BY, BY, BY, BY, BY, BY, BY, BY, BY, BY, BY, BY,
/* 8 */ BY, ZW, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ VW, VW, VW, VW, 0 , 0 , 0 , 0 , BY, ZW, 0 , 0 , 0 , 0 , 0 , 0 ,
/* B */ BY, BY, BY, BY, BY, BY, BY, BY, VW, VW, VW, VW, VW, VW, VW, VW,
/* C */ BY, BY, WO, 0 , 0 , 0 , BY, ZW, EN, 0 , WO, 0 , 0 , BY, 0 , 0 ,
/* D */ 0 , 0 , 0 , 0 , BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* E */ BY, BY, BY, BY, BY, BY, BY, BY, ZW, ZW, PO, BY, 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
},
//For two byte instructions
{ //LSB
// MSB 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F
/* 0 */ 0 , 0 , 0 , 0 , WO, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY ,
/* 0 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 2 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 3 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 7 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 8 */ ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 ,
/* B */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , ZW, 0 , BY, 0 , 0 , 0 , 0 , 0 ,
/* C */ 0 , 0 , BY, 0 , BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* D */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* E */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* F */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0
}
};
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <cassert>
#include "arch/x86/emulenv.hh"
#include "base/misc.hh"
using namespace X86ISA;
void EmulEnv::doModRM(const ExtMachInst & machInst)
{
assert(machInst.modRM.mod != 3);
//Use the SIB byte for addressing if the modrm byte calls for it.
if (machInst.modRM.rm == 4 && machInst.addrSize != 2) {
scale = 1 << machInst.sib.scale;
index = machInst.sib.index | (machInst.rex.x << 3);
base = machInst.sib.base | (machInst.rex.b << 3);
//In this special case, we don't use a base. The displacement also
//changes, but that's managed by the decoder.
if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0)
base = NUM_INTREGS;
//In -this- special case, we don't use an index.
if (index == INTREG_RSP)
index = NUM_INTREGS;
} else {
if (machInst.addrSize == 2) {
unsigned rm = machInst.modRM.rm;
if (rm <= 3) {
scale = 1;
if (rm < 2) {
base = INTREG_RBX;
} else {
base = INTREG_RBP;
}
index = (rm % 2) ? INTREG_RDI : INTREG_RSI;
} else {
scale = 0;
switch (rm) {
case 4:
base = INTREG_RSI;
break;
case 5:
base = INTREG_RDI;
break;
case 6:
base = INTREG_RBP;
break;
case 7:
base = INTREG_RBX;
break;
}
}
} else {
scale = 0;
base = machInst.modRM.rm | (machInst.rex.b << 3);
if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
//Since we need to use a different encoding of this
//instruction anyway, just ignore the base in those cases
base = NUM_INTREGS;
}
}
}
//Figure out what segment to use. This won't be entirely accurate since
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
if ((base != INTREG_RBP && base != INTREG_RSP) || machInst.dispSize) {
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction
int segFromInst = machInst.legacy.seg;
if (segFromInst)
seg = (SegmentRegIndex)(segFromInst - 1);
} else {
seg = SEGMENT_REG_SS;
}
}
void EmulEnv::setSeg(const ExtMachInst & machInst)
{
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction
int segFromInst = machInst.legacy.seg;
if (segFromInst)
seg = (SegmentRegIndex)(segFromInst - 1);
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_EMULENV_HH__
#define __ARCH_X86_EMULENV_HH__
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/segment.hh"
#include "arch/x86/registers.hh"
#include "arch/x86/types.hh"
namespace X86ISA
{
struct EmulEnv
{
RegIndex reg;
RegIndex regm;
SegmentRegIndex seg;
uint8_t scale;
RegIndex index;
RegIndex base;
int dataSize;
int addressSize;
int stackSize;
EmulEnv(RegIndex _reg, RegIndex _regm,
int _dataSize, int _addressSize, int _stackSize) :
reg(_reg), regm(_regm), seg(SEGMENT_REG_DS),
scale(0), index(NUM_INTREGS),
base(NUM_INTREGS),
dataSize(_dataSize), addressSize(_addressSize),
stackSize(_stackSize)
{;}
void doModRM(const ExtMachInst & machInst);
void setSeg(const ExtMachInst & machInst);
};
}
#endif // __ARCH_X86_TYPES_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2003-2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
#include "sim/full_system.hh"
namespace X86ISA
{
void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
{
if (!FullSystem) {
FaultBase::invoke(tc, inst);
return;
}
PCState pcState = tc->pcState();
Addr pc = pcState.pc();
DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
pc, vector, describe());
using namespace X86ISAInst::RomLabels;
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
MicroPC entry;
if (m5reg.mode == LongMode) {
if (isSoft()) {
entry = extern_label_longModeSoftInterrupt;
} else {
entry = extern_label_longModeInterrupt;
}
} else {
entry = extern_label_legacyModeInterrupt;
}
tc->setIntReg(INTREG_MICRO(1), vector);
tc->setIntReg(INTREG_MICRO(7), pc);
if (errorCode != (uint64_t)(-1)) {
if (m5reg.mode == LongMode) {
entry = extern_label_longModeInterruptWithError;
} else {
panic("Legacy mode interrupts with error codes "
"aren't implementde.\n");
}
// Software interrupts shouldn't have error codes. If one
// does, there would need to be microcode to set it up.
assert(!isSoft());
tc->setIntReg(INTREG_MICRO(15), errorCode);
}
pcState.upc(romMicroPC(entry));
pcState.nupc(romMicroPC(entry) + 1);
tc->pcState(pcState);
}
std::string
X86FaultBase::describe() const
{
std::stringstream ss;
ccprintf(ss, "%s", mnemonic());
if (errorCode != (uint64_t)(-1)) {
ccprintf(ss, "(%#x)", errorCode);
}
return ss.str();
}
void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
{
X86FaultBase::invoke(tc);
if (!FullSystem)
return;
// This is the same as a fault, but it happens -after- the
// instruction.
PCState pc = tc->pcState();
pc.uEnd();
}
void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
{
panic("Abort exception!");
}
void
InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
{
if (FullSystem) {
X86Fault::invoke(tc, inst);
} else {
panic("Unrecognized/invalid instruction executed:\n %s",
inst->machInst);
}
}
void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
{
if (FullSystem) {
HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
X86FaultBase::invoke(tc);
/*
* If something bad happens while trying to enter the page fault
* handler, I'm pretty sure that's a double fault and then all
* bets are off. That means it should be safe to update this
* state now.
*/
if (m5reg.mode == LongMode) {
tc->setMiscReg(MISCREG_CR2, addr);
} else {
tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
}
} else {
PageFaultErrorCode code = errorCode;
const char *modeStr = "";
if (code.fetch)
modeStr = "execute";
else if (code.write)
modeStr = "write";
else
modeStr = "read";
panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
}
}
std::string
PageFault::describe() const
{
std::stringstream ss;
ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
return ss.str();
}
void
InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(Faults, "Init interrupt.\n");
// The otherwise unmodified integer registers should be set to 0.
for (int index = 0; index < NUM_INTREGS; index++) {
tc->setIntReg(index, 0);
}
CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
CR0 newCR0 = 1 << 4;
newCR0.cd = cr0.cd;
newCR0.nw = cr0.nw;
tc->setMiscReg(MISCREG_CR0, newCR0);
tc->setMiscReg(MISCREG_CR2, 0);
tc->setMiscReg(MISCREG_CR3, 0);
tc->setMiscReg(MISCREG_CR4, 0);
tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
tc->setMiscReg(MISCREG_EFER, 0);
SegAttr dataAttr = 0;
dataAttr.dpl = 0;
dataAttr.unusable = 0;
dataAttr.defaultSize = 0;
dataAttr.longMode = 0;
dataAttr.avl = 0;
dataAttr.granularity = 0;
dataAttr.present = 1;
dataAttr.type = 3;
dataAttr.writable = 1;
dataAttr.readable = 1;
dataAttr.expandDown = 0;
dataAttr.system = 1;
for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
}
SegAttr codeAttr = 0;
codeAttr.dpl = 0;
codeAttr.unusable = 0;
codeAttr.defaultSize = 0;
codeAttr.longMode = 0;
codeAttr.avl = 0;
codeAttr.granularity = 0;
codeAttr.present = 1;
codeAttr.type = 10;
codeAttr.writable = 0;
codeAttr.readable = 1;
codeAttr.expandDown = 0;
codeAttr.system = 1;
tc->setMiscReg(MISCREG_CS, 0xf000);
tc->setMiscReg(MISCREG_CS_BASE,
0x00000000ffff0000ULL);
tc->setMiscReg(MISCREG_CS_EFF_BASE,
0x00000000ffff0000ULL);
// This has the base value pre-added.
tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
tc->pcState(pc);
tc->setMiscReg(MISCREG_TSG_BASE, 0);
tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_IDTR_BASE, 0);
tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_TSL, 0);
tc->setMiscReg(MISCREG_TSL_BASE, 0);
tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_TSL_ATTR, 0);
tc->setMiscReg(MISCREG_TR, 0);
tc->setMiscReg(MISCREG_TR_BASE, 0);
tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
tc->setMiscReg(MISCREG_TR_ATTR, 0);
// This value should be the family/model/stepping of the processor.
// (page 418). It should be consistent with the value from CPUID, but
// the actual value probably doesn't matter much.
tc->setIntReg(INTREG_RDX, 0);
tc->setMiscReg(MISCREG_DR0, 0);
tc->setMiscReg(MISCREG_DR1, 0);
tc->setMiscReg(MISCREG_DR2, 0);
tc->setMiscReg(MISCREG_DR3, 0);
tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
// Update the handy M5 Reg.
tc->setMiscReg(MISCREG_M5_REG, 0);
MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
pc.upc(romMicroPC(entry));
pc.nupc(romMicroPC(entry) + 1);
tc->pcState(pc);
}
void
StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
panic("Startup IPI recived outside of real mode. "
"Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
}
tc->setMiscReg(MISCREG_CS, vector << 8);
tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
// This has the base value pre-added.
tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
}
} // namespace X86ISA

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_FAULTS_HH__
#define __ARCH_X86_FAULTS_HH__
#include <string>
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "sim/faults.hh"
#include "sim/tlb.hh"
namespace X86ISA
{
// Base class for all x86 "faults" where faults is in the m5 sense
class X86FaultBase : public FaultBase
{
protected:
const char * faultName;
const char * mnem;
uint8_t vector;
uint64_t errorCode;
X86FaultBase(const char * _faultName, const char * _mnem,
const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
: faultName(_faultName), mnem(_mnem),
vector(_vector), errorCode(_errorCode)
{
}
const char * name() const
{
return faultName;
}
virtual bool isBenign()
{
return true;
}
virtual const char * mnemonic() const
{
return mnem;
}
virtual bool isSoft()
{
return false;
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
virtual std::string describe() const;
};
// Base class for x86 faults which behave as if the underlying instruction
// didn't happen.
class X86Fault : public X86FaultBase
{
protected:
X86Fault(const char * name, const char * mnem,
const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
: X86FaultBase(name, mnem, vector, _errorCode)
{}
};
// Base class for x86 traps which behave as if the underlying instruction
// completed.
class X86Trap : public X86FaultBase
{
protected:
X86Trap(const char * name, const char * mnem,
const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
: X86FaultBase(name, mnem, vector, _errorCode)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
// Base class for x86 aborts which seem to be catastrophic failures.
class X86Abort : public X86FaultBase
{
protected:
X86Abort(const char * name, const char * mnem,
const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
: X86FaultBase(name, mnem, vector, _errorCode)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
// Base class for x86 interrupts.
class X86Interrupt : public X86FaultBase
{
protected:
X86Interrupt(const char * name, const char * mnem,
const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
: X86FaultBase(name, mnem, _vector, _errorCode)
{}
};
class UnimpInstFault : public FaultBase
{
public:
const char * name() const
{
return "unimplemented_micro";
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
panic("Unimplemented instruction!");
}
};
// Below is a summary of the interrupt/exception information in the
// architecture manuals.
// Class | Type | vector | Cause | mnem
//------------------------------------------------------------------------
//Contrib Fault 0 Divide-by-Zero-Error #DE
//Benign Either 1 Debug #DB
//Benign Interrupt 2 Non-Maskable-Interrupt #NMI
//Benign Trap 3 Breakpoint #BP
//Benign Trap 4 Overflow #OF
//Benign Fault 5 Bound-Range #BR
//Benign Fault 6 Invalid-Opcode #UD
//Benign Fault 7 Device-Not-Available #NM
//Benign Abort 8 Double-Fault #DF
// 9 Coprocessor-Segment-Overrun
//Contrib Fault 10 Invalid-TSS #TS
//Contrib Fault 11 Segment-Not-Present #NP
//Contrib Fault 12 Stack #SS
//Contrib Fault 13 General-Protection #GP
//Either Fault 14 Page-Fault #PF
// 15 Reserved
//Benign Fault 16 x87 Floating-Point Exception Pending #MF
//Benign Fault 17 Alignment-Check #AC
//Benign Abort 18 Machine-Check #MC
//Benign Fault 19 SIMD Floating-Point #XF
// 20-29 Reserved
//Contrib ? 30 Security Exception #SX
// 31 Reserved
//Benign Interrupt 0-255 External Interrupts #INTR
//Benign Interrupt 0-255 Software Interrupts INTn
class DivideByZero : public X86Fault
{
public:
DivideByZero() :
X86Fault("Divide-by-Zero-Error", "#DE", 0)
{}
};
class DebugException : public X86FaultBase
{
public:
DebugException() :
X86FaultBase("Debug", "#DB", 1)
{}
};
class NonMaskableInterrupt : public X86Interrupt
{
public:
NonMaskableInterrupt(uint8_t _vector) :
X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
{}
};
class Breakpoint : public X86Trap
{
public:
Breakpoint() :
X86Trap("Breakpoint", "#BP", 3)
{}
};
class OverflowTrap : public X86Trap
{
public:
OverflowTrap() :
X86Trap("Overflow", "#OF", 4)
{}
};
class BoundRange : public X86Fault
{
public:
BoundRange() :
X86Fault("Bound-Range", "#BR", 5)
{}
};
class InvalidOpcode : public X86Fault
{
public:
InvalidOpcode() :
X86Fault("Invalid-Opcode", "#UD", 6)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
class DeviceNotAvailable : public X86Fault
{
public:
DeviceNotAvailable() :
X86Fault("Device-Not-Available", "#NM", 7)
{}
};
class DoubleFault : public X86Abort
{
public:
DoubleFault() :
X86Abort("Double-Fault", "#DF", 8, 0)
{}
};
class InvalidTSS : public X86Fault
{
public:
InvalidTSS(uint32_t _errorCode) :
X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
{}
};
class SegmentNotPresent : public X86Fault
{
public:
SegmentNotPresent(uint32_t _errorCode) :
X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
{}
};
class StackFault : public X86Fault
{
public:
StackFault(uint32_t _errorCode) :
X86Fault("Stack", "#SS", 12, _errorCode)
{}
};
class GeneralProtection : public X86Fault
{
public:
GeneralProtection(uint32_t _errorCode) :
X86Fault("General-Protection", "#GP", 13, _errorCode)
{}
};
class PageFault : public X86Fault
{
protected:
BitUnion32(PageFaultErrorCode)
Bitfield<0> present;
Bitfield<1> write;
Bitfield<2> user;
Bitfield<3> reserved;
Bitfield<4> fetch;
EndBitUnion(PageFaultErrorCode)
Addr addr;
public:
PageFault(Addr _addr, uint32_t _errorCode) :
X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
{}
PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
bool user, bool reserved) :
X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
{
PageFaultErrorCode code = 0;
code.present = present;
code.write = (mode == BaseTLB::Write);
code.user = user;
code.reserved = reserved;
code.fetch = (mode == BaseTLB::Execute);
errorCode = code;
}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
virtual std::string describe() const;
};
class X87FpExceptionPending : public X86Fault
{
public:
X87FpExceptionPending() :
X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
{}
};
class AlignmentCheck : public X86Fault
{
public:
AlignmentCheck() :
X86Fault("Alignment-Check", "#AC", 17, 0)
{}
};
class MachineCheck : public X86Abort
{
public:
MachineCheck() :
X86Abort("Machine-Check", "#MC", 18)
{}
};
class SIMDFloatingPointFault : public X86Fault
{
public:
SIMDFloatingPointFault() :
X86Fault("SIMD Floating-Point", "#XF", 19)
{}
};
class SecurityException : public X86FaultBase
{
public:
SecurityException() :
X86FaultBase("Security Exception", "#SX", 30)
{}
};
class ExternalInterrupt : public X86Interrupt
{
public:
ExternalInterrupt(uint8_t _vector) :
X86Interrupt("External Interrupt", "#INTR", _vector)
{}
};
class SystemManagementInterrupt : public X86Interrupt
{
public:
SystemManagementInterrupt() :
X86Interrupt("System Management Interrupt", "#SMI", 0)
{}
};
class InitInterrupt : public X86Interrupt
{
public:
InitInterrupt(uint8_t _vector) :
X86Interrupt("INIT Interrupt", "#INIT", _vector)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
class StartupInterrupt : public X86Interrupt
{
public:
StartupInterrupt(uint8_t _vector) :
X86Interrupt("Startup Interrupt", "#SIPI", _vector)
{}
void invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
class SoftwareInterrupt : public X86Interrupt
{
public:
SoftwareInterrupt(uint8_t _vector) :
X86Interrupt("Software Interrupt", "#INTR", _vector)
{}
bool isSoft()
{
return true;
}
};
}
#endif // __ARCH_X86_FAULTS_HH__

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/*
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/insts/badmicroop.hh"
#include "arch/x86/isa_traits.hh"
namespace X86ISA
{
// This microop needs to be allocated on the heap even though it could
// theoretically be statically allocated. The reference counted pointer would
// try to delete the static memory when it was destructed.
const StaticInstPtr badMicroop =
new X86ISAInst::MicroPanic(NoopMachInst, "BAD",
StaticInst::IsMicroop | StaticInst::IsLastMicroop,
"Invalid microop!", 0);
} // namespace X86ISA

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/*
* Copyright (c) 2011 Advanced Micro Devices, Inc.
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_BADMICROOP_HH__
#define __ARCH_X86_INSTS_BADMICROOP_HH__
#include "cpu/static_inst_fwd.hh"
namespace X86ISA
{
extern const StaticInstPtr badMicroop;
} // namespace X86ISA
#endif //__ARCH_X86_INSTS_BADMICROOP_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_MACROOP_HH__
#define __ARCH_X86_INSTS_MACROOP_HH__
#include "arch/x86/insts/badmicroop.hh"
#include "arch/x86/insts/static_inst.hh"
#include "arch/x86/emulenv.hh"
#include "arch/x86/types.hh"
namespace X86ISA
{
// Base class for combinationally generated macroops
class MacroopBase : public X86StaticInst
{
protected:
const char *macrocodeBlock;
const uint32_t numMicroops;
X86ISA::EmulEnv env;
//Constructor.
MacroopBase(const char *mnem, ExtMachInst _machInst,
uint32_t _numMicroops, X86ISA::EmulEnv _env) :
X86StaticInst(mnem, _machInst, No_OpClass),
numMicroops(_numMicroops), env(_env)
{
assert(numMicroops);
microops = new StaticInstPtr[numMicroops];
flags[IsMacroop] = true;
}
~MacroopBase()
{
delete [] microops;
}
StaticInstPtr * microops;
StaticInstPtr
fetchMicroop(MicroPC microPC) const
{
if (microPC >= numMicroops)
return badMicroop;
else
return microops[microPC];
}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
return mnemonic;
}
public:
ExtMachInst
getExtMachInst()
{
return machInst;
}
X86ISA::EmulEnv
getEmulEnv()
{
return env;
}
};
}
#endif //__ARCH_X86_INSTS_MACROOP_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <string>
#include "arch/x86/insts/microfpop.hh"
#include "arch/x86/regs/misc.hh"
namespace X86ISA
{
/*
uint64_t FpOp::genFlags(uint64_t oldFlags, uint64_t flagMask,
uint64_t _dest, uint64_t _src1, uint64_t _src2,
bool subtract) const
{
}
*/
std::string FpOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, dataSize);
response << ", ";
printSrcReg(response, 0, dataSize);
response << ", ";
printSrcReg(response, 1, dataSize);
return response.str();
}
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_MICROFPOP_HH__
#define __ARCH_X86_INSTS_MICROFPOP_HH__
#include "arch/x86/insts/microop.hh"
namespace X86ISA
{
/**
* Base classes for FpOps which provides a generateDisassembly method.
*/
class FpOp : public X86MicroopBase
{
protected:
const RegIndex src1;
const RegIndex src2;
const RegIndex dest;
const uint8_t dataSize;
const int8_t spm;
// Constructor
FpOp(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, int8_t _spm,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), src2(_src2.idx), dest(_dest.idx),
dataSize(_dataSize), spm(_spm)
{}
/*
//Figure out what the condition code flags should be.
uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
uint64_t _dest, uint64_t _src1, uint64_t _src2,
bool subtract = false) const;
bool checkCondition(uint64_t flags) const;*/
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}
#endif //__ARCH_X86_INSTS_MICROFPOP_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <string>
#include "arch/x86/insts/microldstop.hh"
namespace X86ISA
{
std::string LdStOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
if(flags[IsLoad])
printDestReg(response, 0, dataSize);
else
printSrcReg(response, 2, dataSize);
response << ", ";
printMem(response, segment, scale, index, base, disp,
addressSize, false);
return response.str();
}
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_MICROLDSTOP_HH__
#define __ARCH_X86_INSTS_MICROLDSTOP_HH__
#include "arch/x86/insts/microop.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
namespace X86ISA
{
const Request::FlagsType SegmentFlagMask = mask(4);
const int FlagShift = 4;
enum FlagBit {
CPL0FlagBit = 1,
AddrSizeFlagBit = 2,
StoreCheck = 4
};
/**
* Base class for load and store ops
*/
class LdStOp : public X86MicroopBase
{
protected:
const uint8_t scale;
const RegIndex index;
const RegIndex base;
const uint64_t disp;
const uint8_t segment;
const RegIndex data;
const uint8_t dataSize;
const uint8_t addressSize;
const Request::FlagsType memFlags;
RegIndex foldOBit, foldABit;
//Constructor
LdStOp(ExtMachInst _machInst,
const char * mnem, const char * _instMnem,
uint64_t setFlags,
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
uint64_t _disp, InstRegIndex _segment,
InstRegIndex _data,
uint8_t _dataSize, uint8_t _addressSize,
Request::FlagsType _memFlags,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags, __opClass),
scale(_scale), index(_index.idx), base(_base.idx),
disp(_disp), segment(_segment.idx),
data(_data.idx),
dataSize(_dataSize), addressSize(_addressSize),
memFlags(_memFlags | _segment.idx)
{
assert(_segment.idx < NUM_SEGMENTREGS);
foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
foldABit =
(addressSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}
#endif //__ARCH_X86_INSTS_MICROLDSTOP_HH__

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/*
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <string>
#include "arch/x86/insts/micromediaop.hh"
#include "arch/x86/regs/misc.hh"
namespace X86ISA
{
std::string MediaOpReg::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, destSize);
response << ", ";
printSrcReg(response, 0, srcSize);
response << ", ";
printSrcReg(response, 1, srcSize);
return response.str();
}
std::string MediaOpImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, destSize);
response << ", ";
printSrcReg(response, 0, srcSize);
ccprintf(response, ", %#x", imm8);
return response.str();
}
}

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/*
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_MICROMEDIAOP_HH__
#define __ARCH_X86_INSTS_MICROMEDIAOP_HH__
#include "arch/x86/insts/microop.hh"
namespace X86ISA
{
enum MediaFlag {
MediaMultHiOp = 1,
MediaSignedOp = 64,
MediaScalarOp = 128
};
class MediaOpBase : public X86MicroopBase
{
protected:
const RegIndex src1;
const RegIndex dest;
const uint8_t srcSize;
const uint8_t destSize;
const uint8_t ext;
static const RegIndex foldOBit = 0;
// Constructor
MediaOpBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), dest(_dest.idx),
srcSize(_srcSize), destSize(_destSize), ext(_ext)
{}
bool
scalarOp() const
{
return ext & MediaScalarOp;
}
int
numItems(int size) const
{
return scalarOp() ? 1 : (sizeof(FloatRegBits) / size);
}
bool
multHi() const
{
return ext & MediaMultHiOp;
}
bool
signedOp() const
{
return ext & MediaSignedOp;
}
};
class MediaOpReg : public MediaOpBase
{
protected:
const RegIndex src2;
// Constructor
MediaOpReg(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
src2(_src2.idx)
{}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
class MediaOpImm : public MediaOpBase
{
protected:
uint8_t imm8;
// Constructor
MediaOpImm(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
imm8(_imm8)
{}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}
#endif //__ARCH_X86_INSTS_MICROMEDIAOP_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/insts/microop.hh"
#include "arch/x86/regs/misc.hh"
namespace X86ISA
{
bool X86MicroopBase::checkCondition(uint64_t flags, int condition) const
{
CCFlagBits ccflags = flags;
switch(condition)
{
case ConditionTests::True:
return true;
case ConditionTests::ECF:
return ccflags.ecf;
case ConditionTests::EZF:
return ccflags.ezf;
case ConditionTests::SZnZF:
return !(!ccflags.ezf & ccflags.zf);
case ConditionTests::MSTRZ:
panic("This condition is not implemented!");
case ConditionTests::STRZ:
panic("This condition is not implemented!");
case ConditionTests::MSTRC:
panic("This condition is not implemented!");
case ConditionTests::STRZnEZF:
return !ccflags.ezf & ccflags.zf;
//And no interrupts or debug traps are waiting
case ConditionTests::OF:
return ccflags.of;
case ConditionTests::CF:
return ccflags.cf;
case ConditionTests::ZF:
return ccflags.zf;
case ConditionTests::CvZF:
return ccflags.cf | ccflags.zf;
case ConditionTests::SF:
return ccflags.sf;
case ConditionTests::PF:
return ccflags.pf;
case ConditionTests::SxOF:
return ccflags.sf ^ ccflags.of;
case ConditionTests::SxOvZF:
return (ccflags.sf ^ ccflags.of) | ccflags.zf;
case ConditionTests::False:
return false;
case ConditionTests::NotECF:
return !ccflags.ecf;
case ConditionTests::NotEZF:
return !ccflags.ezf;
case ConditionTests::NotSZnZF:
return !ccflags.ezf & ccflags.zf;
case ConditionTests::NotMSTRZ:
panic("This condition is not implemented!");
case ConditionTests::NotSTRZ:
panic("This condition is not implemented!");
case ConditionTests::NotMSTRC:
panic("This condition is not implemented!");
case ConditionTests::STRnZnEZF:
return !ccflags.ezf & !ccflags.zf;
//And no interrupts or debug traps are waiting
case ConditionTests::NotOF:
return !ccflags.of;
case ConditionTests::NotCF:
return !ccflags.cf;
case ConditionTests::NotZF:
return !ccflags.zf;
case ConditionTests::NotCvZF:
return !(ccflags.cf | ccflags.zf);
case ConditionTests::NotSF:
return !ccflags.sf;
case ConditionTests::NotPF:
return !ccflags.pf;
case ConditionTests::NotSxOF:
return !(ccflags.sf ^ ccflags.of);
case ConditionTests::NotSxOvZF:
return !((ccflags.sf ^ ccflags.of) | ccflags.zf);
}
panic("Unknown condition: %d\n", condition);
return true;
}
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_MICROOP_HH__
#define __ARCH_X86_INSTS_MICROOP_HH__
#include "arch/x86/insts/static_inst.hh"
namespace X86ISA
{
namespace ConditionTests
{
enum CondTest {
True,
NotFalse = True,
ECF,
EZF,
SZnZF,
MSTRZ,
STRZ,
MSTRC,
STRZnEZF,
OF,
CF,
ZF,
CvZF,
SF,
PF,
SxOF,
SxOvZF,
False,
NotTrue = False,
NotECF,
NotEZF,
NotSZnZF,
NotMSTRZ,
NotSTRZ,
NotMSTRC,
STRnZnEZF,
NotOF,
NotCF,
NotZF,
NotCvZF,
NotSF,
NotPF,
NotSxOF,
NotSxOvZF
};
}
//A class which is the base of all x86 micro ops. It provides a function to
//set necessary flags appropriately.
class X86MicroopBase : public X86StaticInst
{
protected:
const char * instMnem;
uint8_t opSize;
uint8_t addrSize;
X86MicroopBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
uint64_t setFlags, OpClass __opClass) :
X86ISA::X86StaticInst(mnem, _machInst, __opClass),
instMnem(_instMnem)
{
const int ChunkSize = sizeof(unsigned long);
const int Chunks = sizeof(setFlags) / ChunkSize;
// Since the bitset constructor can only handle unsigned long
// sized chunks, feed it those one at a time while oring them in.
for (int i = 0; i < Chunks; i++) {
unsigned shift = i * ChunkSize * 8;
flags |= (std::bitset<NumFlags>(setFlags >> shift) << shift);
}
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "\t%s.%s", instMnem, mnemonic);
return ss.str();
}
bool checkCondition(uint64_t flags, int condition) const;
void
advancePC(PCState &pcState) const
{
if (flags[IsLastMicroop])
pcState.uEnd();
else
pcState.uAdvance();
}
};
}
#endif //__ARCH_X86_INSTS_MICROOP_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include <string>
#include "arch/x86/insts/microregop.hh"
#include "arch/x86/regs/misc.hh"
#include "base/condcodes.hh"
#include "debug/X86.hh"
namespace X86ISA
{
uint64_t RegOpBase::genFlags(uint64_t oldFlags, uint64_t flagMask,
uint64_t _dest, uint64_t _src1, uint64_t _src2,
bool subtract) const
{
DPRINTF(X86, "flagMask = %#x\n", flagMask);
uint64_t flags = oldFlags & ~flagMask;
if(flagMask & (ECFBit | CFBit))
{
if(findCarry(dataSize*8, _dest, _src1, _src2))
flags |= (flagMask & (ECFBit | CFBit));
if(subtract)
flags ^= (flagMask & (ECFBit | CFBit));
}
if(flagMask & PFBit && !findParity(8, _dest))
flags |= PFBit;
if(flagMask & AFBit)
{
if(findCarry(4, _dest, _src1, _src2))
flags |= AFBit;
if(subtract)
flags ^= AFBit;
}
if(flagMask & (EZFBit | ZFBit) && findZero(dataSize*8, _dest))
flags |= (flagMask & (EZFBit | ZFBit));
if(flagMask & SFBit && findNegative(dataSize*8, _dest))
flags |= SFBit;
if(flagMask & OFBit && findOverflow(dataSize*8, _dest, _src1, _src2))
flags |= OFBit;
return flags;
}
std::string RegOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, dataSize);
response << ", ";
printSrcReg(response, 0, dataSize);
response << ", ";
printSrcReg(response, 1, dataSize);
return response.str();
}
std::string RegOpImm::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, dataSize);
response << ", ";
printSrcReg(response, 0, dataSize);
ccprintf(response, ", %#x", imm8);
return response.str();
}
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_MICROREGOP_HH__
#define __ARCH_X86_INSTS_MICROREGOP_HH__
#include "arch/x86/insts/microop.hh"
namespace X86ISA
{
/**
* Base classes for RegOps which provides a generateDisassembly method.
*/
class RegOpBase : public X86MicroopBase
{
protected:
const RegIndex src1;
const RegIndex dest;
const uint8_t dataSize;
const uint16_t ext;
RegIndex foldOBit;
// Constructor
RegOpBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), dest(_dest.idx),
dataSize(_dataSize), ext(_ext)
{
foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0;
}
//Figure out what the condition code flags should be.
uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
uint64_t _dest, uint64_t _src1, uint64_t _src2,
bool subtract = false) const;
};
class RegOp : public RegOpBase
{
protected:
const RegIndex src2;
// Constructor
RegOp(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
RegOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _dataSize, _ext,
__opClass),
src2(_src2.idx)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
class RegOpImm : public RegOpBase
{
protected:
const uint8_t imm8;
// Constructor
RegOpImm(ExtMachInst _machInst,
const char * mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
RegOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _dataSize, _ext,
__opClass),
imm8(_imm8)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}
#endif //__ARCH_X86_INSTS_MICROREGOP_HH__

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/insts/static_inst.hh"
#include "arch/x86/regs/segment.hh"
namespace X86ISA
{
void X86StaticInst::printMnemonic(std::ostream &os,
const char * mnemonic) const
{
ccprintf(os, " %s ", mnemonic);
}
void X86StaticInst::printMnemonic(std::ostream &os,
const char * instMnemonic, const char * mnemonic) const
{
ccprintf(os, " %s : %s ", instMnemonic, mnemonic);
}
void X86StaticInst::printSegment(std::ostream &os, int segment) const
{
switch (segment)
{
case SEGMENT_REG_ES:
ccprintf(os, "ES");
break;
case SEGMENT_REG_CS:
ccprintf(os, "CS");
break;
case SEGMENT_REG_SS:
ccprintf(os, "SS");
break;
case SEGMENT_REG_DS:
ccprintf(os, "DS");
break;
case SEGMENT_REG_FS:
ccprintf(os, "FS");
break;
case SEGMENT_REG_GS:
ccprintf(os, "GS");
break;
case SEGMENT_REG_HS:
ccprintf(os, "HS");
break;
case SEGMENT_REG_TSL:
ccprintf(os, "TSL");
break;
case SEGMENT_REG_TSG:
ccprintf(os, "TSG");
break;
case SEGMENT_REG_LS:
ccprintf(os, "LS");
break;
case SEGMENT_REG_MS:
ccprintf(os, "MS");
break;
case SYS_SEGMENT_REG_TR:
ccprintf(os, "TR");
break;
case SYS_SEGMENT_REG_IDTR:
ccprintf(os, "IDTR");
break;
default:
panic("Unrecognized segment %d\n", segment);
}
}
void
X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
{
if(_numSrcRegs > reg)
printReg(os, _srcRegIdx[reg], size);
}
void
X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
{
if(_numDestRegs > reg)
printReg(os, _destRegIdx[reg], size);
}
void
X86StaticInst::printReg(std::ostream &os, int reg, int size) const
{
assert(size == 1 || size == 2 || size == 4 || size == 8);
static const char * abcdFormats[9] =
{"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
static const char * piFormats[9] =
{"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
static const char * longFormats[9] =
{"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
static const char * microFormats[9] =
{"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
if (reg < FP_Base_DepTag) {
const char * suffix = "";
bool fold = reg & IntFoldBit;
reg &= ~IntFoldBit;
if(fold)
suffix = "h";
else if(reg < 8 && size == 1)
suffix = "l";
switch (reg) {
case INTREG_RAX:
ccprintf(os, abcdFormats[size], "a");
break;
case INTREG_RBX:
ccprintf(os, abcdFormats[size], "b");
break;
case INTREG_RCX:
ccprintf(os, abcdFormats[size], "c");
break;
case INTREG_RDX:
ccprintf(os, abcdFormats[size], "d");
break;
case INTREG_RSP:
ccprintf(os, piFormats[size], "sp");
break;
case INTREG_RBP:
ccprintf(os, piFormats[size], "bp");
break;
case INTREG_RSI:
ccprintf(os, piFormats[size], "si");
break;
case INTREG_RDI:
ccprintf(os, piFormats[size], "di");
break;
case INTREG_R8W:
ccprintf(os, longFormats[size], "8");
break;
case INTREG_R9W:
ccprintf(os, longFormats[size], "9");
break;
case INTREG_R10W:
ccprintf(os, longFormats[size], "10");
break;
case INTREG_R11W:
ccprintf(os, longFormats[size], "11");
break;
case INTREG_R12W:
ccprintf(os, longFormats[size], "12");
break;
case INTREG_R13W:
ccprintf(os, longFormats[size], "13");
break;
case INTREG_R14W:
ccprintf(os, longFormats[size], "14");
break;
case INTREG_R15W:
ccprintf(os, longFormats[size], "15");
break;
default:
ccprintf(os, microFormats[size], reg - NUM_INTREGS);
}
ccprintf(os, suffix);
} else if (reg < Ctrl_Base_DepTag) {
int fpindex = reg - FP_Base_DepTag;
if(fpindex < NumMMXRegs) {
ccprintf(os, "%%mmx%d", reg - FP_Base_DepTag);
return;
}
fpindex -= NumMMXRegs;
if(fpindex < NumXMMRegs * 2) {
ccprintf(os, "%%xmm%d_%s", fpindex / 2,
(fpindex % 2) ? "high": "low");
return;
}
fpindex -= NumXMMRegs * 2;
if(fpindex < NumMicroFpRegs) {
ccprintf(os, "%%ufp%d", fpindex);
return;
}
fpindex -= NumMicroFpRegs;
ccprintf(os, "%%st(%d)", fpindex);
} else {
switch (reg - Ctrl_Base_DepTag) {
default:
ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
}
}
}
void X86StaticInst::printMem(std::ostream &os, uint8_t segment,
uint8_t scale, RegIndex index, RegIndex base,
uint64_t disp, uint8_t addressSize, bool rip) const
{
bool someAddr = false;
printSegment(os, segment);
os << ":[";
if (rip) {
os << "rip";
someAddr = true;
} else {
if (scale != 0 && index != ZeroReg)
{
if(scale != 1)
ccprintf(os, "%d*", scale);
printReg(os, index, addressSize);
someAddr = true;
}
if (base != ZeroReg)
{
if(someAddr)
os << " + ";
printReg(os, base, addressSize);
someAddr = true;
}
}
if (disp != 0)
{
if(someAddr)
os << " + ";
ccprintf(os, "%#x", disp);
someAddr = true;
}
if (!someAddr)
os << "0";
os << "]";
}
std::string X86StaticInst::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, mnemonic);
return ss.str();
}
}

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/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INSTS_STATICINST_HH__
#define __ARCH_X86_INSTS_STATICINST_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/X86.hh"
namespace X86ISA
{
/**
* Class for register indices passed to instruction constructors. Using a
* wrapper struct for these lets take advantage of the compiler's type
* checking.
*/
struct InstRegIndex
{
RegIndex idx;
explicit InstRegIndex(RegIndex _idx) : idx(_idx)
{}
};
/**
* Base class for all X86 static instructions.
*/
class X86StaticInst : public StaticInst
{
protected:
// Constructor.
X86StaticInst(const char *mnem,
ExtMachInst _machInst, OpClass __opClass)
: StaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
void printMnemonic(std::ostream &os, const char * mnemonic) const;
void printMnemonic(std::ostream &os, const char * instMnemonic,
const char * mnemonic) const;
void printSegment(std::ostream &os, int segment) const;
void printReg(std::ostream &os, int reg, int size) const;
void printSrcReg(std::ostream &os, int reg, int size) const;
void printDestReg(std::ostream &os, int reg, int size) const;
void printMem(std::ostream &os, uint8_t segment,
uint8_t scale, RegIndex index, RegIndex base,
uint64_t disp, uint8_t addressSize, bool rip) const;
inline uint64_t merge(uint64_t into, uint64_t val, int size) const
{
X86IntReg reg = into;
if(_destRegIdx[0] & IntFoldBit)
{
reg.H = val;
return reg;
}
switch(size)
{
case 1:
reg.L = val;
break;
case 2:
reg.X = val;
break;
case 4:
//XXX Check if this should be zeroed or sign extended
reg = 0;
reg.E = val;
break;
case 8:
reg.R = val;
break;
default:
panic("Tried to merge with unrecognized size %d.\n", size);
}
return reg;
}
inline uint64_t pick(uint64_t from, int idx, int size) const
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
if(_srcRegIdx[idx] & IntFoldBit)
return reg.H;
switch(size)
{
case 1:
return reg.L;
case 2:
return reg.X;
case 4:
return reg.E;
case 8:
return reg.R;
default:
panic("Tried to pick with unrecognized size %d.\n", size);
}
}
inline int64_t signedPick(uint64_t from, int idx, int size) const
{
X86IntReg reg = from;
DPRINTF(X86, "Picking with size %d\n", size);
if(_srcRegIdx[idx] & IntFoldBit)
return reg.SH;
switch(size)
{
case 1:
return reg.SL;
case 2:
return reg.SX;
case 4:
return reg.SE;
case 8:
return reg.SR;
default:
panic("Tried to pick with unrecognized size %d.\n", size);
}
}
void
advancePC(PCState &pcState) const
{
pcState.advance();
}
};
}
#endif //__ARCH_X86_INSTS_STATICINST_HH__

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/*
* Copyright (c) 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/regs/apic.hh"
#include "arch/x86/interrupts.hh"
#include "arch/x86/intmessage.hh"
#include "cpu/base.hh"
#include "debug/LocalApic.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/pc.hh"
#include "dev/x86/south_bridge.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"
#include "sim/full_system.hh"
int
divideFromConf(uint32_t conf)
{
// This figures out what division we want from the division configuration
// register in the local APIC. The encoding is a little odd but it can
// be deciphered fairly easily.
int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
shift = (shift + 1) % 8;
return 1 << shift;
}
namespace X86ISA
{
ApicRegIndex
decodeAddr(Addr paddr)
{
ApicRegIndex regNum;
paddr &= ~mask(3);
switch (paddr)
{
case 0x20:
regNum = APIC_ID;
break;
case 0x30:
regNum = APIC_VERSION;
break;
case 0x80:
regNum = APIC_TASK_PRIORITY;
break;
case 0x90:
regNum = APIC_ARBITRATION_PRIORITY;
break;
case 0xA0:
regNum = APIC_PROCESSOR_PRIORITY;
break;
case 0xB0:
regNum = APIC_EOI;
break;
case 0xD0:
regNum = APIC_LOGICAL_DESTINATION;
break;
case 0xE0:
regNum = APIC_DESTINATION_FORMAT;
break;
case 0xF0:
regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
break;
case 0x100:
case 0x108:
case 0x110:
case 0x118:
case 0x120:
case 0x128:
case 0x130:
case 0x138:
case 0x140:
case 0x148:
case 0x150:
case 0x158:
case 0x160:
case 0x168:
case 0x170:
case 0x178:
regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
break;
case 0x180:
case 0x188:
case 0x190:
case 0x198:
case 0x1A0:
case 0x1A8:
case 0x1B0:
case 0x1B8:
case 0x1C0:
case 0x1C8:
case 0x1D0:
case 0x1D8:
case 0x1E0:
case 0x1E8:
case 0x1F0:
case 0x1F8:
regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
break;
case 0x200:
case 0x208:
case 0x210:
case 0x218:
case 0x220:
case 0x228:
case 0x230:
case 0x238:
case 0x240:
case 0x248:
case 0x250:
case 0x258:
case 0x260:
case 0x268:
case 0x270:
case 0x278:
regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
break;
case 0x280:
regNum = APIC_ERROR_STATUS;
break;
case 0x300:
regNum = APIC_INTERRUPT_COMMAND_LOW;
break;
case 0x310:
regNum = APIC_INTERRUPT_COMMAND_HIGH;
break;
case 0x320:
regNum = APIC_LVT_TIMER;
break;
case 0x330:
regNum = APIC_LVT_THERMAL_SENSOR;
break;
case 0x340:
regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
break;
case 0x350:
regNum = APIC_LVT_LINT0;
break;
case 0x360:
regNum = APIC_LVT_LINT1;
break;
case 0x370:
regNum = APIC_LVT_ERROR;
break;
case 0x380:
regNum = APIC_INITIAL_COUNT;
break;
case 0x390:
regNum = APIC_CURRENT_COUNT;
break;
case 0x3E0:
regNum = APIC_DIVIDE_CONFIGURATION;
break;
default:
// A reserved register field.
panic("Accessed reserved register field %#x.\n", paddr);
break;
}
return regNum;
}
}
Tick
X86ISA::Interrupts::read(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - pioAddr;
//Make sure we're at least only accessing one register.
if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
uint32_t val = htog(readReg(reg));
DPRINTF(LocalApic,
"Reading Local APIC register %d at offset %#x as %#x.\n",
reg, offset, val);
pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
pkt->makeAtomicResponse();
return latency;
}
Tick
X86ISA::Interrupts::write(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - pioAddr;
//Make sure we're at least only accessing one register.
if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
panic("Accessed more than one register at a time in the APIC!\n");
ApicRegIndex reg = decodeAddr(offset);
uint32_t val = regs[reg];
pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
DPRINTF(LocalApic,
"Writing Local APIC register %d at offset %#x as %#x.\n",
reg, offset, gtoh(val));
setReg(reg, gtoh(val));
pkt->makeAtomicResponse();
return latency;
}
void
X86ISA::Interrupts::requestInterrupt(uint8_t vector,
uint8_t deliveryMode, bool level)
{
/*
* Fixed and lowest-priority delivery mode interrupts are handled
* using the IRR/ISR registers, checking against the TPR, etc.
* The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
*/
if (deliveryMode == DeliveryMode::Fixed ||
deliveryMode == DeliveryMode::LowestPriority) {
DPRINTF(LocalApic, "Interrupt is an %s.\n",
DeliveryMode::names[deliveryMode]);
// Queue up the interrupt in the IRR.
if (vector > IRRV)
IRRV = vector;
if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
if (level) {
setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
} else {
clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
}
}
} else if (!DeliveryMode::isReserved(deliveryMode)) {
DPRINTF(LocalApic, "Interrupt is an %s.\n",
DeliveryMode::names[deliveryMode]);
if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
pendingUnmaskableInt = pendingSmi = true;
smiVector = vector;
} else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
pendingUnmaskableInt = pendingNmi = true;
nmiVector = vector;
} else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
pendingExtInt = true;
extIntVector = vector;
} else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
pendingUnmaskableInt = pendingInit = true;
initVector = vector;
} else if (deliveryMode == DeliveryMode::SIPI &&
!pendingStartup && !startedUp) {
pendingUnmaskableInt = pendingStartup = true;
startupVector = vector;
}
}
if (FullSystem)
cpu->wakeup();
}
void
X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
{
assert(newCPU);
if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
panic("Local APICs can't be moved between CPUs"
" with different IDs.\n");
}
cpu = newCPU;
initialApicId = cpu->cpuId();
regs[APIC_ID] = (initialApicId << 24);
}
void
X86ISA::Interrupts::init()
{
//
// The local apic must register its address ranges on both its pio port
// via the basicpiodevice(piodevice) init() function and its int port
// that it inherited from IntDev. Note IntDev is not a SimObject itself.
//
BasicPioDevice::init();
IntDev::init();
// the slave port has a range so inform the connected master
intSlavePort.sendRangeChange();
}
Tick
X86ISA::Interrupts::recvMessage(PacketPtr pkt)
{
Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
assert(pkt->cmd == MemCmd::MessageReq);
switch(offset)
{
case 0:
{
TriggerIntMessage message = pkt->get<TriggerIntMessage>();
DPRINTF(LocalApic,
"Got Trigger Interrupt message with vector %#x.\n",
message.vector);
requestInterrupt(message.vector,
message.deliveryMode, message.trigger);
}
break;
default:
panic("Local apic got unknown interrupt message at offset %#x.\n",
offset);
break;
}
pkt->makeAtomicResponse();
return latency;
}
Tick
X86ISA::Interrupts::recvResponse(PacketPtr pkt)
{
assert(!pkt->isError());
assert(pkt->cmd == MemCmd::MessageResp);
if (--pendingIPIs == 0) {
InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
// Record that the ICR is now idle.
low.deliveryStatus = 0;
regs[APIC_INTERRUPT_COMMAND_LOW] = low;
}
DPRINTF(LocalApic, "ICR is now idle.\n");
return 0;
}
AddrRangeList
X86ISA::Interrupts::getAddrRanges()
{
AddrRangeList ranges;
Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
x86LocalAPICAddress(initialApicId, 0) +
PageBytes);
ranges.push_back(range);
pioAddr = range.start;
return ranges;
}
AddrRangeList
X86ISA::Interrupts::getIntAddrRange()
{
AddrRangeList ranges;
ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
x86InterruptAddress(initialApicId, 0) +
PhysAddrAPICRangeSize));
return ranges;
}
uint32_t
X86ISA::Interrupts::readReg(ApicRegIndex reg)
{
if (reg >= APIC_TRIGGER_MODE(0) &&
reg <= APIC_TRIGGER_MODE(15)) {
panic("Local APIC Trigger Mode registers are unimplemented.\n");
}
switch (reg) {
case APIC_ARBITRATION_PRIORITY:
panic("Local APIC Arbitration Priority register unimplemented.\n");
break;
case APIC_PROCESSOR_PRIORITY:
panic("Local APIC Processor Priority register unimplemented.\n");
break;
case APIC_ERROR_STATUS:
regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
break;
case APIC_CURRENT_COUNT:
{
if (apicTimerEvent.scheduled()) {
assert(clock);
// Compute how many m5 ticks happen per count.
uint64_t ticksPerCount = clock *
divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
// Compute how many m5 ticks are left.
uint64_t val = apicTimerEvent.when() - curTick();
// Turn that into a count.
val = (val + ticksPerCount - 1) / ticksPerCount;
return val;
} else {
return 0;
}
}
default:
break;
}
return regs[reg];
}
void
X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
{
uint32_t newVal = val;
if (reg >= APIC_IN_SERVICE(0) &&
reg <= APIC_IN_SERVICE(15)) {
panic("Local APIC In-Service registers are unimplemented.\n");
}
if (reg >= APIC_TRIGGER_MODE(0) &&
reg <= APIC_TRIGGER_MODE(15)) {
panic("Local APIC Trigger Mode registers are unimplemented.\n");
}
if (reg >= APIC_INTERRUPT_REQUEST(0) &&
reg <= APIC_INTERRUPT_REQUEST(15)) {
panic("Local APIC Interrupt Request registers "
"are unimplemented.\n");
}
switch (reg) {
case APIC_ID:
newVal = val & 0xFF;
break;
case APIC_VERSION:
// The Local APIC Version register is read only.
return;
case APIC_TASK_PRIORITY:
newVal = val & 0xFF;
break;
case APIC_ARBITRATION_PRIORITY:
panic("Local APIC Arbitration Priority register unimplemented.\n");
break;
case APIC_PROCESSOR_PRIORITY:
panic("Local APIC Processor Priority register unimplemented.\n");
break;
case APIC_EOI:
// Remove the interrupt that just completed from the local apic state.
clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
updateISRV();
return;
case APIC_LOGICAL_DESTINATION:
newVal = val & 0xFF000000;
break;
case APIC_DESTINATION_FORMAT:
newVal = val | 0x0FFFFFFF;
break;
case APIC_SPURIOUS_INTERRUPT_VECTOR:
regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
if (val & (1 << 9))
warn("Focus processor checking not implemented.\n");
break;
case APIC_ERROR_STATUS:
{
if (regs[APIC_INTERNAL_STATE] & 0x1) {
regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
newVal = 0;
} else {
regs[APIC_INTERNAL_STATE] |= ULL(0x1);
return;
}
}
break;
case APIC_INTERRUPT_COMMAND_LOW:
{
InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
// Check if we're already sending an IPI.
if (low.deliveryStatus) {
newVal = low;
break;
}
low = val;
InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
// Record that an IPI is being sent.
low.deliveryStatus = 1;
TriggerIntMessage message = 0;
message.destination = high.destination;
message.vector = low.vector;
message.deliveryMode = low.deliveryMode;
message.destMode = low.destMode;
message.level = low.level;
message.trigger = low.trigger;
bool timing = sys->getMemoryMode() == Enums::timing;
// Be careful no updates of the delivery status bit get lost.
regs[APIC_INTERRUPT_COMMAND_LOW] = low;
ApicList apics;
int numContexts = sys->numContexts();
switch (low.destShorthand) {
case 0:
if (message.deliveryMode == DeliveryMode::LowestPriority) {
panic("Lowest priority delivery mode "
"IPIs aren't implemented.\n");
}
if (message.destMode == 1) {
int dest = message.destination;
hack_once("Assuming logical destinations are 1 << id.\n");
for (int i = 0; i < numContexts; i++) {
if (dest & 0x1)
apics.push_back(i);
dest = dest >> 1;
}
} else {
if (message.destination == 0xFF) {
for (int i = 0; i < numContexts; i++) {
if (i == initialApicId) {
requestInterrupt(message.vector,
message.deliveryMode, message.trigger);
} else {
apics.push_back(i);
}
}
} else {
if (message.destination == initialApicId) {
requestInterrupt(message.vector,
message.deliveryMode, message.trigger);
} else {
apics.push_back(message.destination);
}
}
}
break;
case 1:
newVal = val;
requestInterrupt(message.vector,
message.deliveryMode, message.trigger);
break;
case 2:
requestInterrupt(message.vector,
message.deliveryMode, message.trigger);
// Fall through
case 3:
{
for (int i = 0; i < numContexts; i++) {
if (i != initialApicId) {
apics.push_back(i);
}
}
}
break;
}
pendingIPIs += apics.size();
intMasterPort.sendMessage(apics, message, timing);
newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
}
break;
case APIC_LVT_TIMER:
case APIC_LVT_THERMAL_SENSOR:
case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
case APIC_LVT_LINT0:
case APIC_LVT_LINT1:
case APIC_LVT_ERROR:
{
uint64_t readOnlyMask = (1 << 12) | (1 << 14);
newVal = (val & ~readOnlyMask) |
(regs[reg] & readOnlyMask);
}
break;
case APIC_INITIAL_COUNT:
{
assert(clock);
newVal = bits(val, 31, 0);
// Compute how many timer ticks we're being programmed for.
uint64_t newCount = newVal *
(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
// Schedule on the edge of the next tick plus the new count.
Tick offset = curTick() % clock;
if (offset) {
reschedule(apicTimerEvent,
curTick() + (newCount + 1) * clock - offset, true);
} else {
reschedule(apicTimerEvent,
curTick() + newCount * clock, true);
}
}
break;
case APIC_CURRENT_COUNT:
//Local APIC Current Count register is read only.
return;
case APIC_DIVIDE_CONFIGURATION:
newVal = val & 0xB;
break;
default:
break;
}
regs[reg] = newVal;
return;
}
X86ISA::Interrupts::Interrupts(Params * p) :
BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
clock(0),
apicTimerEvent(this),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
pendingExtInt(false), extIntVector(0),
pendingInit(false), initVector(0),
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL),
intSlavePort(name() + ".int_slave", this, this, latency)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
//Set the local apic DFR to the flat model.
regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
ISRV = 0;
IRRV = 0;
}
bool
X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
{
RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
if (pendingUnmaskableInt) {
DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
return true;
}
if (rflags.intf) {
if (pendingExtInt) {
DPRINTF(LocalApic, "Reported pending external interrupt.\n");
return true;
}
if (IRRV > ISRV && bits(IRRV, 7, 4) >
bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
return true;
}
}
return false;
}
Fault
X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
{
assert(checkInterrupts(tc));
// These are all probably fairly uncommon, so we'll make them easier to
// check for.
if (pendingUnmaskableInt) {
if (pendingSmi) {
DPRINTF(LocalApic, "Generated SMI fault object.\n");
return new SystemManagementInterrupt();
} else if (pendingNmi) {
DPRINTF(LocalApic, "Generated NMI fault object.\n");
return new NonMaskableInterrupt(nmiVector);
} else if (pendingInit) {
DPRINTF(LocalApic, "Generated INIT fault object.\n");
return new InitInterrupt(initVector);
} else if (pendingStartup) {
DPRINTF(LocalApic, "Generating SIPI fault object.\n");
return new StartupInterrupt(startupVector);
} else {
panic("pendingUnmaskableInt set, but no unmaskable "
"ints were pending.\n");
return NoFault;
}
} else if (pendingExtInt) {
DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
return new ExternalInterrupt(extIntVector);
} else {
DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
// The only thing left are fixed and lowest priority interrupts.
return new ExternalInterrupt(IRRV);
}
}
void
X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
{
assert(checkInterrupts(tc));
if (pendingUnmaskableInt) {
if (pendingSmi) {
DPRINTF(LocalApic, "SMI sent to core.\n");
pendingSmi = false;
} else if (pendingNmi) {
DPRINTF(LocalApic, "NMI sent to core.\n");
pendingNmi = false;
} else if (pendingInit) {
DPRINTF(LocalApic, "Init sent to core.\n");
pendingInit = false;
startedUp = false;
} else if (pendingStartup) {
DPRINTF(LocalApic, "SIPI sent to core.\n");
pendingStartup = false;
startedUp = true;
}
if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
pendingUnmaskableInt = false;
} else if (pendingExtInt) {
pendingExtInt = false;
} else {
DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
// Mark the interrupt as "in service".
ISRV = IRRV;
setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
// Clear it out of the IRR.
clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
updateIRRV();
}
}
void
X86ISA::Interrupts::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
SERIALIZE_SCALAR(clock);
SERIALIZE_SCALAR(pendingSmi);
SERIALIZE_SCALAR(smiVector);
SERIALIZE_SCALAR(pendingNmi);
SERIALIZE_SCALAR(nmiVector);
SERIALIZE_SCALAR(pendingExtInt);
SERIALIZE_SCALAR(extIntVector);
SERIALIZE_SCALAR(pendingInit);
SERIALIZE_SCALAR(initVector);
SERIALIZE_SCALAR(pendingStartup);
SERIALIZE_SCALAR(startupVector);
SERIALIZE_SCALAR(startedUp);
SERIALIZE_SCALAR(pendingUnmaskableInt);
SERIALIZE_SCALAR(pendingIPIs);
SERIALIZE_SCALAR(IRRV);
SERIALIZE_SCALAR(ISRV);
bool apicTimerEventScheduled = apicTimerEvent.scheduled();
SERIALIZE_SCALAR(apicTimerEventScheduled);
Tick apicTimerEventTick = apicTimerEvent.when();
SERIALIZE_SCALAR(apicTimerEventTick);
}
void
X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
UNSERIALIZE_SCALAR(clock);
UNSERIALIZE_SCALAR(pendingSmi);
UNSERIALIZE_SCALAR(smiVector);
UNSERIALIZE_SCALAR(pendingNmi);
UNSERIALIZE_SCALAR(nmiVector);
UNSERIALIZE_SCALAR(pendingExtInt);
UNSERIALIZE_SCALAR(extIntVector);
UNSERIALIZE_SCALAR(pendingInit);
UNSERIALIZE_SCALAR(initVector);
UNSERIALIZE_SCALAR(pendingStartup);
UNSERIALIZE_SCALAR(startupVector);
UNSERIALIZE_SCALAR(startedUp);
UNSERIALIZE_SCALAR(pendingUnmaskableInt);
UNSERIALIZE_SCALAR(pendingIPIs);
UNSERIALIZE_SCALAR(IRRV);
UNSERIALIZE_SCALAR(ISRV);
bool apicTimerEventScheduled;
UNSERIALIZE_SCALAR(apicTimerEventScheduled);
if (apicTimerEventScheduled) {
Tick apicTimerEventTick;
UNSERIALIZE_SCALAR(apicTimerEventTick);
if (apicTimerEvent.scheduled()) {
reschedule(apicTimerEvent, apicTimerEventTick, true);
} else {
schedule(apicTimerEvent, apicTimerEventTick);
}
}
}
X86ISA::Interrupts *
X86LocalApicParams::create()
{
return new X86ISA::Interrupts(this);
}

316
simulators/gem5/src/arch/x86/interrupts.hh Normal file
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@ -0,0 +1,316 @@
/*
* Copyright (c) 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
* Andreas Hansson
*/
#ifndef __ARCH_X86_INTERRUPTS_HH__
#define __ARCH_X86_INTERRUPTS_HH__
#include "arch/x86/regs/apic.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/intmessage.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
#include "dev/x86/intdev.hh"
#include "dev/io_device.hh"
#include "params/X86LocalApic.hh"
#include "sim/eventq.hh"
class ThreadContext;
class BaseCPU;
namespace X86ISA {
class Interrupts : public BasicPioDevice, IntDev
{
protected:
// Storage for the APIC registers
uint32_t regs[NUM_APIC_REGS];
BitUnion32(LVTEntry)
Bitfield<7, 0> vector;
Bitfield<10, 8> deliveryMode;
Bitfield<12> status;
Bitfield<13> polarity;
Bitfield<14> remoteIRR;
Bitfield<15> trigger;
Bitfield<16> masked;
Bitfield<17> periodic;
EndBitUnion(LVTEntry)
/*
* Timing related stuff.
*/
Tick latency;
Tick clock;
class ApicTimerEvent : public Event
{
private:
Interrupts *localApic;
public:
ApicTimerEvent(Interrupts *_localApic) :
Event(), localApic(_localApic)
{}
void process()
{
assert(localApic);
if (localApic->triggerTimerInterrupt()) {
localApic->setReg(APIC_INITIAL_COUNT,
localApic->readReg(APIC_INITIAL_COUNT));
}
}
};
ApicTimerEvent apicTimerEvent;
/*
* A set of variables to keep track of interrupts that don't go through
* the IRR.
*/
bool pendingSmi;
uint8_t smiVector;
bool pendingNmi;
uint8_t nmiVector;
bool pendingExtInt;
uint8_t extIntVector;
bool pendingInit;
uint8_t initVector;
bool pendingStartup;
uint8_t startupVector;
bool startedUp;
// This is a quick check whether any of the above (except ExtInt) are set.
bool pendingUnmaskableInt;
// A count of how many IPIs are in flight.
int pendingIPIs;
/*
* IRR and ISR maintenance.
*/
uint8_t IRRV;
uint8_t ISRV;
int
findRegArrayMSB(ApicRegIndex base)
{
int offset = 7;
do {
if (regs[base + offset] != 0) {
return offset * 32 + findMsbSet(regs[base + offset]);
}
} while (offset--);
return 0;
}
void
updateIRRV()
{
IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
}
void
updateISRV()
{
ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
}
void
setRegArrayBit(ApicRegIndex base, uint8_t vector)
{
regs[base + (vector / 32)] |= (1 << (vector % 32));
}
void
clearRegArrayBit(ApicRegIndex base, uint8_t vector)
{
regs[base + (vector / 32)] &= ~(1 << (vector % 32));
}
bool
getRegArrayBit(ApicRegIndex base, uint8_t vector)
{
return bits(regs[base + (vector / 32)], vector % 5);
}
void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
BaseCPU *cpu;
int initialApicId;
// Port for receiving interrupts
IntSlavePort intSlavePort;
public:
int getInitialApicId() { return initialApicId; }
/*
* Params stuff.
*/
typedef X86LocalApicParams Params;
void setCPU(BaseCPU * newCPU);
void
setClock(Tick newClock)
{
clock = newClock;
}
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/*
* Initialize this object by registering it with the IO APIC.
*/
void init();
/*
* Functions to interact with the interrupt port from IntDev.
*/
Tick read(PacketPtr pkt);
Tick write(PacketPtr pkt);
Tick recvMessage(PacketPtr pkt);
Tick recvResponse(PacketPtr pkt);
bool
triggerTimerInterrupt()
{
LVTEntry entry = regs[APIC_LVT_TIMER];
if (!entry.masked)
requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
return entry.periodic;
}
AddrRangeList getAddrRanges();
AddrRangeList getIntAddrRange();
MasterPort &getMasterPort(const std::string &if_name, int idx = -1)
{
if (if_name == "int_master") {
return intMasterPort;
}
return BasicPioDevice::getMasterPort(if_name, idx);
}
SlavePort &getSlavePort(const std::string &if_name, int idx = -1)
{
if (if_name == "int_slave") {
return intSlavePort;
}
return BasicPioDevice::getSlavePort(if_name, idx);
}
/*
* Functions to access and manipulate the APIC's registers.
*/
uint32_t readReg(ApicRegIndex miscReg);
void setReg(ApicRegIndex reg, uint32_t val);
void
setRegNoEffect(ApicRegIndex reg, uint32_t val)
{
regs[reg] = val;
}
/*
* Constructor.
*/
Interrupts(Params * p);
/*
* Functions for retrieving interrupts for the CPU to handle.
*/
bool checkInterrupts(ThreadContext *tc) const;
Fault getInterrupt(ThreadContext *tc);
void updateIntrInfo(ThreadContext *tc);
/*
* Serialization.
*/
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
/*
* Old functions needed for compatability but which will be phased out
* eventually.
*/
void
post(int int_num, int index)
{
panic("Interrupts::post unimplemented!\n");
}
void
clear(int int_num, int index)
{
panic("Interrupts::clear unimplemented!\n");
}
void
clearAll()
{
panic("Interrupts::clearAll unimplemented!\n");
}
};
} // namespace X86ISA
#endif // __ARCH_X86_INTERRUPTS_HH__

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/*
* Copyright (c) 2008 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_INTMESSAGE_HH__
#define __ARCH_X86_INTMESSAGE_HH__
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
namespace X86ISA
{
BitUnion32(TriggerIntMessage)
Bitfield<7, 0> destination;
Bitfield<15, 8> vector;
Bitfield<18, 16> deliveryMode;
Bitfield<19> destMode;
Bitfield<20> level;
Bitfield<21> trigger;
EndBitUnion(TriggerIntMessage)
namespace DeliveryMode
{
enum IntDeliveryMode {
Fixed = 0,
LowestPriority = 1,
SMI = 2,
NMI = 4,
INIT = 5,
SIPI = 6,
ExtInt = 7,
NumModes
};
static const char * const names[NumModes] = {
"Fixed", "LowestPriority", "SMI", "Reserved",
"NMI", "INIT", "Startup", "ExtInt"
};
static inline bool
isReserved(int mode)
{
return mode == 3;
}
}
static const Addr TriggerIntOffset = 0;
static inline PacketPtr
prepIntRequest(const uint8_t id, Addr offset, Addr size)
{
RequestPtr req = new Request(x86InterruptAddress(id, offset),
size, Request::UNCACHEABLE,
Request::intMasterId);
PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
pkt->allocate();
return pkt;
}
template<class T>
PacketPtr
buildIntRequest(const uint8_t id, T payload, Addr offset, Addr size)
{
PacketPtr pkt = prepIntRequest(id, offset, size);
pkt->set<T>(payload);
return pkt;
}
static inline PacketPtr
buildIntRequest(const uint8_t id, TriggerIntMessage payload)
{
return buildIntRequest(id, payload, TriggerIntOffset,
sizeof(TriggerIntMessage));
}
static inline PacketPtr
buildIntResponse()
{
panic("buildIntResponse not implemented.\n");
}
}
#endif

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/*
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/isa.hh"
#include "arch/x86/tlb.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
namespace X86ISA
{
void
ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
{
HandyM5Reg m5reg = 0;
if (efer.lma) {
m5reg.mode = LongMode;
if (csAttr.longMode)
m5reg.submode = SixtyFourBitMode;
else
m5reg.submode = CompatabilityMode;
} else {
m5reg.mode = LegacyMode;
if (cr0.pe) {
if (rflags.vm)
m5reg.submode = Virtual8086Mode;
else
m5reg.submode = ProtectedMode;
} else {
m5reg.submode = RealMode;
}
}
m5reg.cpl = csAttr.dpl;
m5reg.paging = cr0.pg;
m5reg.prot = cr0.pe;
// Compute the default and alternate operand size.
if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
m5reg.defOp = 2;
m5reg.altOp = 1;
} else {
m5reg.defOp = 1;
m5reg.altOp = 2;
}
// Compute the default and alternate address size.
if (m5reg.submode == SixtyFourBitMode) {
m5reg.defAddr = 3;
m5reg.altAddr = 2;
} else if (csAttr.defaultSize) {
m5reg.defAddr = 2;
m5reg.altAddr = 1;
} else {
m5reg.defAddr = 1;
m5reg.altAddr = 2;
}
// Compute the stack size
if (m5reg.submode == SixtyFourBitMode) {
m5reg.stack = 3;
} else if (ssAttr.defaultSize) {
m5reg.stack = 2;
} else {
m5reg.stack = 1;
}
regVal[MISCREG_M5_REG] = m5reg;
}
void
ISA::clear()
{
// Blank everything. 0 might not be an appropriate value for some things,
// but it is for most.
memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
regVal[MISCREG_DR7] = 1 << 10;
}
MiscReg
ISA::readMiscRegNoEffect(int miscReg)
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to read them directly.
assert( miscReg != MISCREG_CR1 &&
!(miscReg > MISCREG_CR4 &&
miscReg < MISCREG_CR8) &&
!(miscReg > MISCREG_CR8 &&
miscReg <= MISCREG_CR15));
return regVal[miscReg];
}
MiscReg
ISA::readMiscReg(int miscReg, ThreadContext * tc)
{
if (miscReg == MISCREG_TSC) {
return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
}
return readMiscRegNoEffect(miscReg);
}
void
ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to write to them directly.
assert( miscReg != MISCREG_CR1 &&
!(miscReg > MISCREG_CR4 &&
miscReg < MISCREG_CR8) &&
!(miscReg > MISCREG_CR8 &&
miscReg <= MISCREG_CR15));
regVal[miscReg] = val;
}
void
ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
{
MiscReg newVal = val;
switch(miscReg)
{
case MISCREG_CR0:
{
CR0 toggled = regVal[miscReg] ^ val;
CR0 newCR0 = val;
Efer efer = regVal[MISCREG_EFER];
if (toggled.pg && efer.lme) {
if (newCR0.pg) {
//Turning on long mode
efer.lma = 1;
regVal[MISCREG_EFER] = efer;
} else {
//Turning off long mode
efer.lma = 0;
regVal[MISCREG_EFER] = efer;
}
}
if (toggled.pg) {
tc->getITBPtr()->invalidateAll();
tc->getDTBPtr()->invalidateAll();
}
//This must always be 1.
newCR0.et = 1;
newVal = newCR0;
updateHandyM5Reg(regVal[MISCREG_EFER],
newCR0,
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
regVal[MISCREG_RFLAGS]);
}
break;
case MISCREG_CR2:
break;
case MISCREG_CR3:
tc->getITBPtr()->invalidateNonGlobal();
tc->getDTBPtr()->invalidateNonGlobal();
break;
case MISCREG_CR4:
{
CR4 toggled = regVal[miscReg] ^ val;
if (toggled.pae || toggled.pse || toggled.pge) {
tc->getITBPtr()->invalidateAll();
tc->getDTBPtr()->invalidateAll();
}
}
break;
case MISCREG_CR8:
break;
case MISCREG_CS_ATTR:
{
SegAttr toggled = regVal[miscReg] ^ val;
SegAttr newCSAttr = val;
if (toggled.longMode) {
if (newCSAttr.longMode) {
regVal[MISCREG_ES_EFF_BASE] = 0;
regVal[MISCREG_CS_EFF_BASE] = 0;
regVal[MISCREG_SS_EFF_BASE] = 0;
regVal[MISCREG_DS_EFF_BASE] = 0;
} else {
regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
}
}
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
newCSAttr,
regVal[MISCREG_SS_ATTR],
regVal[MISCREG_RFLAGS]);
}
break;
case MISCREG_SS_ATTR:
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
val,
regVal[MISCREG_RFLAGS]);
break;
// These segments always actually use their bases, or in other words
// their effective bases must stay equal to their actual bases.
case MISCREG_FS_BASE:
case MISCREG_GS_BASE:
case MISCREG_HS_BASE:
case MISCREG_TSL_BASE:
case MISCREG_TSG_BASE:
case MISCREG_TR_BASE:
case MISCREG_IDTR_BASE:
regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
break;
// These segments ignore their bases in 64 bit mode.
// their effective bases must stay equal to their actual bases.
case MISCREG_ES_BASE:
case MISCREG_CS_BASE:
case MISCREG_SS_BASE:
case MISCREG_DS_BASE:
{
Efer efer = regVal[MISCREG_EFER];
SegAttr csAttr = regVal[MISCREG_CS_ATTR];
if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
regVal[MISCREG_SEG_EFF_BASE(miscReg -
MISCREG_SEG_BASE_BASE)] = val;
}
break;
case MISCREG_TSC:
regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
return;
case MISCREG_DR0:
case MISCREG_DR1:
case MISCREG_DR2:
case MISCREG_DR3:
/* These should eventually set up breakpoints. */
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
/* Fall through to have the same effects as DR6. */
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
DR6 newDR6 = val;
dr6.b0 = newDR6.b0;
dr6.b1 = newDR6.b1;
dr6.b2 = newDR6.b2;
dr6.b3 = newDR6.b3;
dr6.bd = newDR6.bd;
dr6.bs = newDR6.bs;
dr6.bt = newDR6.bt;
newVal = dr6;
}
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
/* Fall through to have the same effects as DR7. */
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];
DR7 newDR7 = val;
dr7.l0 = newDR7.l0;
dr7.g0 = newDR7.g0;
if (dr7.l0 || dr7.g0) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 0. */
}
dr7.l1 = newDR7.l1;
dr7.g1 = newDR7.g1;
if (dr7.l1 || dr7.g1) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 1. */
}
dr7.l2 = newDR7.l2;
dr7.g2 = newDR7.g2;
if (dr7.l2 || dr7.g2) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 2. */
}
dr7.l3 = newDR7.l3;
dr7.g3 = newDR7.g3;
if (dr7.l3 || dr7.g3) {
panic("Debug register breakpoints not implemented.\n");
} else {
/* Disable breakpoint 3. */
}
dr7.gd = newDR7.gd;
dr7.rw0 = newDR7.rw0;
dr7.len0 = newDR7.len0;
dr7.rw1 = newDR7.rw1;
dr7.len1 = newDR7.len1;
dr7.rw2 = newDR7.rw2;
dr7.len2 = newDR7.len2;
dr7.rw3 = newDR7.rw3;
dr7.len3 = newDR7.len3;
}
break;
case MISCREG_M5_REG:
// Writing anything to the m5reg with side effects makes it update
// based on the current values of the relevant registers. The actual
// value written is discarded.
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
regVal[MISCREG_RFLAGS]);
return;
default:
break;
}
setMiscRegNoEffect(miscReg, newVal);
}
void
ISA::serialize(EventManager *em, std::ostream & os)
{
SERIALIZE_ARRAY(regVal, NumMiscRegs);
}
void
ISA::unserialize(EventManager *em, Checkpoint * cp,
const std::string & section)
{
UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
updateHandyM5Reg(regVal[MISCREG_EFER],
regVal[MISCREG_CR0],
regVal[MISCREG_CS_ATTR],
regVal[MISCREG_SS_ATTR],
regVal[MISCREG_RFLAGS]);
}
}

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/*
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_ISA_HH__
#define __ARCH_X86_ISA_HH__
#include <iostream>
#include <string>
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/registers.hh"
#include "base/types.hh"
class Checkpoint;
class EventManager;
class ThreadContext;
namespace X86ISA
{
class ISA
{
protected:
MiscReg regVal[NUM_MISCREGS];
void updateHandyM5Reg(Efer efer, CR0 cr0,
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
public:
void clear();
ISA()
{
clear();
}
MiscReg readMiscRegNoEffect(int miscReg);
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, MiscReg val);
void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
int
flattenIntIndex(int reg)
{
return reg & ~IntFoldBit;
}
int
flattenFloatIndex(int reg)
{
if (reg >= NUM_FLOATREGS) {
reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
regVal[MISCREG_X87_TOP]);
}
return reg;
}
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
};
}
#endif

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// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
//REX prefix
def bitfield REX rex;
def bitfield REX_PRESENT rex.present;
def bitfield REX_W rex.w;
def bitfield REX_R rex.r;
def bitfield REX_X rex.x;
def bitfield REX_B rex.b;
//Legacy prefixes
def bitfield LEGACY legacy;
def bitfield LEGACY_DECODEVAL legacy.decodeVal;
def bitfield LEGACY_REPNE legacy.repne;
def bitfield LEGACY_REP legacy.rep;
def bitfield LEGACY_LOCK legacy.lock;
def bitfield LEGACY_OP legacy.op;
def bitfield LEGACY_ADDR legacy.addr;
def bitfield LEGACY_SEG legacy.seg;
// Pieces of the opcode
def bitfield OPCODE_NUM opcode.num;
def bitfield OPCODE_PREFIXA opcode.prefixA;
def bitfield OPCODE_PREFIXB opcode.prefixB;
def bitfield OPCODE_OP opcode.op;
//The top 5 bits of the opcode tend to split the instructions into groups
def bitfield OPCODE_OP_TOP5 opcode.op.top5;
def bitfield OPCODE_OP_BOTTOM3 opcode.op.bottom3;
// Immediate fields
def bitfield IMMEDIATE immediate;
def bitfield DISPLACEMENT displacement;
//Modifier bytes
def bitfield MODRM modRM;
def bitfield MODRM_MOD modRM.mod;
def bitfield MODRM_REG modRM.reg;
def bitfield MODRM_RM modRM.rm;
def bitfield SIB sib;
def bitfield SIB_SCALE sib.scale;
def bitfield SIB_INDEX sib.index;
def bitfield SIB_BASE sib.base;
def bitfield OPSIZE opSize;
def bitfield ADDRSIZE addrSize;
def bitfield STACKSIZE stackSize;
def bitfield MODE mode;
def bitfield MODE_MODE mode.mode;
def bitfield MODE_SUBMODE mode.submode;

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// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// The actual decoder specification
//
decode LEGACY_LOCK default Unknown::unknown()
{
//No lock prefix
0x0: decode OPCODE_NUM default Unknown::unknown()
{
0x0: M5InternalError::error(
{{"Saw an ExtMachInst with zero opcode bytes!"}});
//1 byte opcodes
##include "one_byte_opcodes.isa"
//2 byte opcodes
##include "two_byte_opcodes.isa"
//3 byte opcodes
##include "three_byte_opcodes.isa"
}
//Lock prefix
##include "locked_opcodes.isa"
}

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// Copyright (c) 2009 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Decode opcodes with the lock prefix. Opcodes which shouldn't have that
// prefix should effectively decode to UD2.
//
// All the memory references in these instructions happen through modrm bytes.
// We therefore only need to make sure the modrm byte encodes a memory
// reference to make sure these are the memory forms of these instructions.
0x1: decode MODRM_MOD {
format Inst {
0x3: UD2();
default: decode OPCODE_NUM {
0x1: decode OPCODE_OP_TOP5 {
0x00: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::ADD_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x01: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::OR_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x02: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::ADC_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x03: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::SBB_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x04: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::AND_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x05: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::SUB_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x06: decode OPCODE_OP_BOTTOM3 {
default: MultiInst::XOR_LOCKED(OPCODE_OP_BOTTOM3,
[Mb,Gb], [Mv,Gv]);
}
0x10: decode OPCODE_OP_BOTTOM3 {
0x0: decode MODRM_REG {
0x0: ADD_LOCKED(Mb,Ib);
0x1: OR_LOCKED(Mb,Ib);
0x2: ADC_LOCKED(Mb,Ib);
0x3: SBB_LOCKED(Mb,Ib);
0x4: AND_LOCKED(Mb,Ib);
0x5: SUB_LOCKED(Mb,Ib);
0x6: XOR_LOCKED(Mb,Ib);
}
0x1: decode MODRM_REG {
0x0: ADD_LOCKED(Mv,Iz);
0x1: OR_LOCKED(Mv,Iz);
0x2: ADC_LOCKED(Mv,Iz);
0x3: SBB_LOCKED(Mv,Iz);
0x4: AND_LOCKED(Mv,Iz);
0x5: SUB_LOCKED(Mv,Iz);
0x6: XOR_LOCKED(Mv,Iz);
}
0x2: decode MODE_SUBMODE {
0x0: UD2();
default: decode MODRM_REG {
0x0: ADD_LOCKED(Mb,Ib);
0x1: OR_LOCKED(Mb,Ib);
0x2: ADC_LOCKED(Mb,Ib);
0x3: SBB_LOCKED(Mb,Ib);
0x4: AND_LOCKED(Mb,Ib);
0x5: SUB_LOCKED(Mb,Ib);
0x6: XOR_LOCKED(Mb,Ib);
}
}
//0x3: group1_Ev_Ib();
0x3: decode MODRM_REG {
0x0: ADD_LOCKED(Mv,Ib);
0x1: OR_LOCKED(Mv,Ib);
0x2: ADC_LOCKED(Mv,Ib);
0x3: SBB_LOCKED(Mv,Ib);
0x4: AND_LOCKED(Mv,Ib);
0x5: SUB_LOCKED(Mv,Ib);
0x6: XOR_LOCKED(Mv,Ib);
}
0x6: XCHG_LOCKED(Mb,Gb);
0x7: XCHG_LOCKED(Mv,Gv);
}
0x1E: decode OPCODE_OP_BOTTOM3 {
//0x6: group3_Eb();
0x6: decode MODRM_REG {
0x2: NOT_LOCKED(Mb);
0x3: NEG_LOCKED(Mb);
}
//0x7: group3_Ev();
0x7: decode MODRM_REG {
0x2: NOT_LOCKED(Mv);
0x3: NEG_LOCKED(Mv);
}
}
0x1F: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODRM_REG {
0x0: INC_LOCKED(Mb);
0x1: DEC_LOCKED(Mb);
default: UD2();
}
//0x7: group5();
0x7: decode MODRM_REG {
0x0: INC_LOCKED(Mv);
0x1: DEC_LOCKED(Mv);
}
}
}
0x2: decode OPCODE_PREFIXA {
0x0F: decode OPCODE_OP_TOP5 {
0x04: decode OPCODE_OP_BOTTOM3 {
0x0: WarnUnimpl::mov_Rd_CR8D();
0x2: WarnUnimpl::mov_CR8D_Rd();
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x3: BTS_LOCKED(Mv,Gv);
}
0x16: decode OPCODE_OP_BOTTOM3 {
0x0: CMPXCHG_LOCKED(Mb,Gb);
0x1: CMPXCHG_LOCKED(Mv,Gv);
0x3: BTR_LOCKED(Mv,Gv);
}
0x17: decode OPCODE_OP_BOTTOM3 {
0x2: decode MODRM_REG {
0x5: BTS_LOCKED(Mv,Ib);
0x6: BTR_LOCKED(Mv,Ib);
0x7: BTC_LOCKED(Mv,Ib);
}
0x3: BTC_LOCKED(Mv,Gv);
}
0x18: decode OPCODE_OP_BOTTOM3 {
0x0: XADD_LOCKED(Mb,Gb);
0x1: XADD_LOCKED(Mv,Gv);
//0x7: group9();
0x7: decode MODRM_REG {
//Also CMPXCHG16B
0x1: CMPXCHG8B_LOCKED(Mdp);
}
}
}
default: M5InternalError::error(
{{"Unexpected first opcode byte in two byte opcode!"}});
}
}
}
}

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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Decode the one byte opcodes
//
0x1: decode OPCODE_OP_TOP5 {
format Inst {
0x00: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::push_ES();
}
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::pop_ES();
}
default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x01: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::push_CS();
}
//Any time this is seen, it should generate a two byte opcode
0x7: M5InternalError::error(
{{"Saw a one byte opcode whose value was 0x0F!"}});
default: MultiInst::OR(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x02: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::push_SS();
}
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::pop_SS();
}
default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x03: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::push_DS();
}
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::pop_DS();
}
default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x04: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
{{"Tried to execute the ES segment override prefix!"}});
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::daa();
}
default: MultiInst::AND(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x05: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
{{"Tried to execute the CS segment override prefix!"}});
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::das();
}
default: MultiInst::SUB(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x06: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
{{"Tried to execute the SS segment override prefix!"}});
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::aaa();
}
default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x07: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
{{"Tried to execute the DS segment override prefix!"}});
0x7: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::aas();
}
default: MultiInst::CMP(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAb,Ib], [rAv,Iz]);
}
0x08: decode MODE_SUBMODE {
0x0: M5InternalError::error (
{{"Tried to execute an REX prefix!"}});
default: INC(Bv);
}
0x09: decode MODE_SUBMODE {
0x0: M5InternalError::error (
{{"Tried to execute an REX prefix!"}});
default: DEC(Bv);
}
0x0A: PUSH(Bv);
0x0B: POP(Bv);
0x0C: decode OPCODE_OP_BOTTOM3 {
0x0: decode MODE_SUBMODE {
0x0: UD2();
default: PUSHA();
}
0x1: decode MODE_SUBMODE {
0x0: UD2();
default: POPA();
}
0x2: decode MODE_SUBMODE {
0x0: UD2();
default: BOUND(Gv,Mv);
}
0x3: decode MODE_SUBMODE {
//The second operand should really be of size "d", but it's
//set to "v" in order to have a consistent register size.
//This shouldn't affect behavior.
0x0: MOVSXD(Gv,Ev);
default: WarnUnimpl::arpl_Ew_Gw();
}
0x4: M5InternalError::error(
{{"Tried to execute the FS segment override prefix!"}});
0x5: M5InternalError::error(
{{"Tried to execute the GS segment override prefix!"}});
0x6: M5InternalError::error(
{{"Tried to execute the operand size override prefix!"}});
0x7: M5InternalError::error(
{{"Tried to execute the DS address size override prefix!"}});
}
0x0D: decode OPCODE_OP_BOTTOM3 {
0x0: PUSH(Iz);
0x1: IMUL(Gv,Ev,Iz);
0x2: PUSH(Ib);
0x3: IMUL(Gv,Ev,Ib);
0x4: StringInst::INS(Yb,rD);
0x5: StringInst::INS(Yz,rD);
0x6: StringInst::OUTS(rD,Xb);
0x7: StringInst::OUTS(rD,Xz);
}
0x0E: decode OPCODE_OP_BOTTOM3 {
0x0: JO(Jb);
0x1: JNO(Jb);
0x2: JB(Jb);
0x3: JNB(Jb);
0x4: JZ(Jb);
0x5: JNZ(Jb);
0x6: JBE(Jb);
0x7: JNBE(Jb);
}
0x0F: decode OPCODE_OP_BOTTOM3 {
0x0: JS(Jb);
0x1: JNS(Jb);
0x2: JP(Jb);
0x3: JNP(Jb);
0x4: JL(Jb);
0x5: JNL(Jb);
0x6: JLE(Jb);
0x7: JNLE(Jb);
}
0x10: decode OPCODE_OP_BOTTOM3 {
//0x0: group1_Eb_Ib();
0x0: decode MODRM_REG {
0x0: ADD(Eb,Ib);
0x1: OR(Eb,Ib);
0x2: ADC(Eb,Ib);
0x3: SBB(Eb,Ib);
0x4: AND(Eb,Ib);
0x5: SUB(Eb,Ib);
0x6: XOR(Eb,Ib);
0x7: CMP(Eb,Ib);
}
//0x1: group1_Ev_Iz();
0x1: decode MODRM_REG {
0x0: ADD(Ev,Iz);
0x1: OR(Ev,Iz);
0x2: ADC(Ev,Iz);
0x3: SBB(Ev,Iz);
0x4: AND(Ev,Iz);
0x5: SUB(Ev,Iz);
0x6: XOR(Ev,Iz);
0x7: CMP(Ev,Iz);
}
0x2: decode MODE_SUBMODE {
0x0: UD2();
//default: group1_Eb_Ib();
default: decode MODRM_REG {
0x0: ADD(Eb,Ib);
0x1: OR(Eb,Ib);
0x2: ADC(Eb,Ib);
0x3: SBB(Eb,Ib);
0x4: AND(Eb,Ib);
0x5: SUB(Eb,Ib);
0x6: XOR(Eb,Ib);
0x7: CMP(Eb,Ib);
}
}
//0x3: group1_Ev_Ib();
0x3: decode MODRM_REG {
0x0: ADD(Ev,Ib);
0x1: OR(Ev,Ib);
0x2: ADC(Ev,Ib);
0x3: SBB(Ev,Ib);
0x4: AND(Ev,Ib);
0x5: SUB(Ev,Ib);
0x6: XOR(Ev,Ib);
0x7: CMP(Ev,Ib);
}
0x4: TEST(Eb,Gb);
0x5: TEST(Ev,Gv);
0x6: XCHG(Eb,Gb);
0x7: XCHG(Ev,Gv);
}
0x11: decode OPCODE_OP_BOTTOM3 {
0x0: MOV(Eb,Gb);
0x1: MOV(Ev,Gv);
0x2: MOV(Gb,Eb);
0x3: MOV(Gv,Ev);
0x4: decode MODRM_REG {
0x0, 0x1, 0x2,
0x3, 0x4, 0x5: MOV(Ev,Sv);
}
0x5: LEA(Gv,M);
0x6: decode MODE_SUBMODE {
0x3, 0x4: MOV_REAL(Sv,Ev);
default: decode MODRM_REG {
0x1: UD2(); // Moving to the CS selector is illegal.
0x2: MOVSS(Sv,Ev);
0x0, 0x3,
0x4, 0x5: MOV(Sv,Ev);
default: UD2();
}
}
//0x7: group10_Ev();
0x7: decode MODRM_REG {
0x0: POP(Ev);
default: UD2();
}
}
0x12: decode OPCODE_OP_BOTTOM3 {
0x0: NopInst::NOP(); //XXX repe makes this a "pause"
default: XCHG(Bv,rAv);
}
0x13: decode OPCODE_OP_BOTTOM3 {
0x0: CDQE(rAv);
0x1: CQO(rAv,rDv);
0x2: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::call_far_Ap();
}
0x3: WarnUnimpl::fwait(); //aka wait
0x4: PUSHF();
0x5: POPF();
//The 64 bit versions of both of these should be illegal only
//if CPUID says it isn't supported. For now, we'll just assume
//that it's supported.
0x6: SAHF();
0x7: LAHF();
}
0x14: decode OPCODE_OP_BOTTOM3 {
0x0: MOV(rAb, Ob);
0x1: MOV(rAv, Ov);
0x2: MOV(Ob, rAb);
0x3: MOV(Ov, rAv);
0x4: StringInst::MOVS(Yb,Xb);
0x5: StringInst::MOVS(Yv,Xv);
0x6: StringTestInst::CMPS(Yb,Xb);
0x7: StringTestInst::CMPS(Yv,Xv);
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x0: TEST(rAb,Ib);
0x1: TEST(rAv,Iz);
0x2: StringInst::STOS(Yb);
0x3: StringInst::STOS(Yv);
0x4: StringInst::LODS(Xb);
0x5: StringInst::LODS(Xv);
0x6: StringTestInst::SCAS(Yb);
0x7: StringTestInst::SCAS(Yv);
}
0x16: MOV(Bb,Ib);
0x17: MOV(Bv,Iv);
0x18: decode OPCODE_OP_BOTTOM3 {
//0x0: group2_Eb_Ib();
0x0: decode MODRM_REG {
0x0: ROL(Eb,Ib);
0x1: ROR(Eb,Ib);
0x2: RCL(Eb,Ib);
0x3: RCR(Eb,Ib);
0x4: SAL(Eb,Ib);
0x5: SHR(Eb,Ib);
0x6: SAL(Eb,Ib);
0x7: SAR(Eb,Ib);
}
//0x1: group2_Ev_Ib();
0x1: decode MODRM_REG {
0x0: ROL(Ev,Ib);
0x1: ROR(Ev,Ib);
0x2: RCL(Ev,Ib);
0x3: RCR(Ev,Ib);
0x4: SAL(Ev,Ib);
0x5: SHR(Ev,Ib);
0x6: SAL(Ev,Ib);
0x7: SAR(Ev,Ib);
}
0x2: RET_NEAR(Iw);
0x3: RET_NEAR();
0x4: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::les_Gz_Mp();
}
0x5: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::lds_Gz_Mp();
}
//0x6: group12_Eb_Ib();
0x6: decode MODRM_REG {
0x0: MOV(Eb,Ib);
default: UD2();
}
//0x7: group12_Ev_Iz();
0x7: decode MODRM_REG {
0x0: MOV(Ev,Iz);
default: UD2();
}
}
format WarnUnimpl {
0x19: decode OPCODE_OP_BOTTOM3 {
// The second parameter here should be of size b, but
// immediate sizes are determined elsewhere and this would
// confuse the instruction type specialization code.
0x0: Inst::ENTER(Iw,Iw);
0x1: Inst::LEAVE();
0x2: ret_far_Iw();
0x3: decode MODE_SUBMODE {
0x3, 0x4: ret_far_real();
default: Inst::RET_FAR();
}
0x4: int3();
0x5: decode FullSystemInt default int_Ib() {
0: decode IMMEDIATE {
// Really only the LSB matters, but the decoder
// will sign extend it, and there's no easy way to
// specify only checking the first byte.
-0x80: SyscallInst::int80('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
}
}
0x6: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: into();
}
0x7: decode MODE_SUBMODE {
0x4: Inst::IRET_REAL();
0x3: Inst::IRET_VIRT();
default: Inst::IRET_PROT();
}
}
}
0x1A: decode OPCODE_OP_BOTTOM3 {
//0x0: group2_Eb_1();
0x0: decode MODRM_REG {
0x0: ROL_1(Eb);
0x1: ROR_1(Eb);
0x2: RCL_1(Eb);
0x3: RCR_1(Eb);
0x4: SAL_1(Eb);
0x5: SHR_1(Eb);
0x6: SAL_1(Eb);
0x7: SAR_1(Eb);
}
//0x1: group2_Ev_1();
0x1: decode MODRM_REG {
0x0: ROL_1(Ev);
0x1: ROR_1(Ev);
0x2: RCL_1(Ev);
0x3: RCR_1(Ev);
0x4: SAL_1(Ev);
0x5: SHR_1(Ev);
0x6: SAL_1(Ev);
0x7: SAR_1(Ev);
}
//0x2: group2_Eb_Cl();
0x2: decode MODRM_REG {
0x0: ROL(Eb,rCb);
0x1: ROR(Eb,rCb);
0x2: RCL(Eb,rCb);
0x3: RCR(Eb,rCb);
0x4: SAL(Eb,rCb);
0x5: SHR(Eb,rCb);
0x6: SAL(Eb,rCb);
0x7: SAR(Eb,rCb);
}
//The second operand should have size "b", but to have
//consistent register sizes it's "v". This shouldn't have
//any affect on functionality.
//0x3: group2_Ev_Cl();
0x3: decode MODRM_REG {
0x0: ROL(Ev,rCv);
0x1: ROR(Ev,rCv);
0x2: RCL(Ev,rCv);
0x3: RCR(Ev,rCv);
0x4: SAL(Ev,rCv);
0x5: SHR(Ev,rCv);
0x6: SAL(Ev,rCv);
0x7: SAR(Ev,rCv);
}
0x4: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::aam_Ib();
}
0x5: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::aad_Ib();
}
0x6: decode MODE_SUBMODE {
0x0: UD2();
default: SALC(rAb);
}
0x7: XLAT();
}
##include "x87.isa"
0x1C: decode OPCODE_OP_BOTTOM3 {
0x0: LOOPNE(Jb);
0x1: LOOPE(Jb);
0x2: LOOP(Jb);
0x3: JRCX(Jb);
0x4: IN(rAb,Ib);
0x5: IN(rAv,Iv);
0x6: OUT(Ib,rAb);
0x7: OUT(Iv,rAv);
}
0x1D: decode OPCODE_OP_BOTTOM3 {
0x0: CALL_NEAR(Jz);
0x1: JMP(Jz);
0x2: decode MODE_SUBMODE {
0x0: UD2();
0x1: JMP_FAR(Iz);
0x2: JMP_FAR(Iz);
0x3: JMP_FAR_REAL(Iz);
0x4: JMP_FAR_REAL(Iz);
}
0x3: JMP(Jb);
0x4: IN(rAb,rD);
0x5: IN(rAv,rD);
0x6: OUT(rD,rAb);
0x7: OUT(rD,rAv);
}
0x1E: decode OPCODE_OP_BOTTOM3 {
0x0: M5InternalError::error(
{{"Tried to execute the lock prefix!"}});
0x1: WarnUnimpl::int1();
0x2: M5InternalError::error(
{{"Tried to execute the repne prefix!"}});
0x3: M5InternalError::error(
{{"Tried to execute the rep/repe prefix!"}});
0x4: HLT();
0x5: CMC();
//0x6: group3_Eb();
0x6: decode MODRM_REG {
0x0: TEST(Eb,Iz);
0x1: TEST(Eb,Iz);
0x2: NOT(Eb);
0x3: NEG(Eb);
0x4: MUL_B(Eb);
0x5: IMUL_B(Eb);
//This should be Eb, but it access the entire word value ax.
0x6: DIV_B(Ew);
0x7: IDIV_B(Eb);
}
//0x7: group3_Ev();
0x7: decode MODRM_REG {
0x0: TEST(Ev,Iz);
0x1: TEST(Ev,Iz);
0x2: NOT(Ev);
0x3: NEG(Ev);
0x4: MUL(Ev);
0x5: IMUL(Ev);
0x6: DIV(Ev);
0x7: IDIV(Ev);
}
}
0x1F: decode OPCODE_OP_BOTTOM3 {
0x0: CLC();
0x1: STC();
0x2: CLI();
0x3: STI();
0x4: CLD();
0x5: STD();
//0x6: group4();
0x6: decode MODRM_REG {
0x0: INC(Eb);
0x1: DEC(Eb);
default: UD2();
}
//0x7: group5();
0x7: decode MODRM_REG {
0x0: INC(Ev);
0x1: DEC(Ev);
0x2: CALL_NEAR(Ev);
0x3: WarnUnimpl::call_far_Mp();
0x4: JMP(Ev);
0x5: decode MODE_SUBMODE {
0x0: JMP_FAR(Mz);
0x1: JMP_FAR(Mz);
0x2: JMP_FAR(Mz);
0x3: JMP_FAR_REAL(Mz);
0x4: JMP_FAR_REAL(Mz);
}
0x6: PUSH(Ev);
0x7: UD2();
}
}
}
default: FailUnimpl::oneByteOps();
}

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// Copyright (c) 2008 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Decode the three byte opcodes
//
0x3: decode OPCODE_PREFIXA {
0x0F: decode OPCODE_PREFIXB {
0x38: decode LEGACY_OP {
format WarnUnimpl {
1: decode OPCODE_OP {
0x00: pshufb_Vdq_Wdq();
0x01: phaddw_Vdq_Wdq();
0x02: phaddd_Vdq_Wdq();
0x03: phaddsw_Vdq_Wdq();
0x04: pmaddubsw_Vdq_Wdq();
0x05: phsubw_Vdq_Wdq();
0x06: phsubd_Vdq_Wdq();
0x07: phsubsw_Vdq_Wdq();
0x08: psignb_Vdq_Wdq();
0x09: psignw_Vdq_Wdq();
0x0A: psignd_Vdq_Wdq();
0x0B: pmulhrsw_Vdq_Wdq();
0x10: pblendvb_Vdq_Wdq();
0x14: blendvps_Vdq_Wdq();
0x15: blendvpd_Vdq_Wdq();
0x17: ptest_Vdq_Wdq();
0x1C: pabsb_Vdq_Wdq();
0x1D: pabsw_Vdq_Wdq();
0x1E: pabsd_Vdq_Wdq();
0x20: pmovsxbw_Vdq_Udq_or_Mq();
0x21: pmovsxbd_Vdq_Udq_or_Md();
0x22: pmovsxbq_Vdq_Udq_or_Mw();
0x23: pmovsxwd_Vdq_Udq_or_Mq();
0x24: pmovsxwq_Vdq_Udq_or_Md();
0x25: pmovsxdq_Vdq_Udq_or_Mq();
0x28: pmuldq_Vdq_Wdq();
0x29: pcmpeqq_Vdq_Wdq();
0x2A: movntdqa_Vdq_Mdq();
0x2B: packusdw_Vdq_Wdq();
0x30: pmovzxbw_Vdq_Udq_or_Mq();
0x31: pmovzxbd_Vdq_Udq_or_Md();
0x32: pmovzxbq_Vdq_Udq_or_Mw();
0x33: pmovzxwd_Vdq_Udq_or_Mq();
0x34: pmovzxwq_Vdq_Udq_or_Md();
0x35: pmovzxdq_Vdq_Udq_or_Mq();
0x37: pcmpgtq_Vdq_Wdq();
0x38: pminsb_Vdq_Wdq();
0x39: pminsd_Vdq_Wdq();
0x3A: pminuw_Vdq_Wdq();
0x3B: pminud_Vdq_Wdq();
0x3C: pmaxsb_Vdq_Wdq();
0x3D: pmaxsd_Vdq_Wdq();
0x3E: pmaxuw_Vdq_Wdq();
0x3F: pmaxud_Vdq_Wdq();
0x40: pmulld_Vdq_Wdq();
0x41: phminposuw_Vdq_Wdq();
default: Inst::UD2();
}
default: decode LEGACY_REPNE {
1: decode OPCODE_OP {
0xF0: crc32_Gd_Eb();
0xF1: crc32_Gd_Ev();
default: Inst::UD2();
}
default: decode OPCODE_OP {
0x00: pshufb_Pq_Qq();
0x01: phaddw_Pq_Qq();
0x02: phaddd_Pq_Qq();
0x03: phaddsw_Pq_Qq();
0x04: pmaddubsw_Pq_Qq();
0x05: phsubw_Pq_Qq();
0x06: phsubd_Pq_Qq();
0x07: phsubsw_Pq_Qq();
0x08: psignb_Pq_Qq();
0x09: psignw_Pq_Qq();
0x0A: psignd_Pq_Qq();
0x0B: pmulhrsw_Pq_Qq();
0x1C: pabsb_Pq_Qq();
0x1D: pabsw_Pq_Qq();
0x1E: pabsd_Pq_Qq();
default: Inst::UD2();
}
}
}
}
0x3A: decode LEGACY_OP {
format WarnUnimpl {
1: decode OPCODE_OP {
0x08: roundps_Vdq_Wdq_Ib();
0x09: roundpd_Vdq_Wdq_Ib();
0x0A: roundss_Vss_Wss_Ib();
0x0B: roundsd_Vsd_Wsd_Ib();
0x0C: blendps_Vdq_Wdq_Ib();
0x0D: blendpd_Vdq_Wdq_Ib();
0x0E: pblendw_Vdq_Wdq_Ib();
0x0F: palignr_Vdq_Wdq_Ib();
0x14: pextrb_Rd_or_Mb_Vdq_Ib();
0x15: decode MODRM_MOD {
0x3: Inst::PEXTRW(Rd,Vdq,Ib);
default: pextrw_Mw_Vdq_Ib();
}
0x16: pextrd_pextrq_Ed_or_Eq_Vdq_Ib();
0x17: extractps_Ed_Vdq_Ib();
0x20: pinsrb_Vdq_Rd_or_Rq_or_Mb_Ib();
0x21: insertps_Vdq_Udq_or_Md_Ib();
0x22: pinsrd_pinsrq_Vdq_Ed_or_Eq_Ib();
0x40: dpps_Vdq_Wdq_Ib();
0x41: dppd_Vdq_Wdq_Ib();
0x42: pcmpistrm_Vdq_Wdq_Ib();
0x43: pcmpistri_Vdq_Wdq_Ib();
default: Inst::UD2();
}
default: decode OPCODE_OP {
0x0F: palignr_Pq_Qq_Ib();
default: Inst::UD2();
}
}
}
default: M5InternalError::error(
{{"Unexpected second opcode byte in three byte opcode!"}});
}
default: M5InternalError::error(
{{"Unexpected first opcode byte in three byte opcode!"}});
}

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// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
format WarnUnimpl {
0x1B: decode OPCODE_OP_BOTTOM3 {
//0x0: esc0();
0x0: decode MODRM_REG {
0x0: fadd();
0x1: fmul();
0x2: fcom();
0x3: fcomp();
0x4: fsub();
0x5: fsubr();
0x6: fdiv();
0x7: fdivr();
}
//0x1: esc1();
0x1: decode MODRM_REG {
0x0: fld();
0x1: decode MODRM_MOD {
0x3: fxch();
default: Inst::UD2();
}
0x2: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: fnop();
default: Inst::UD2();
}
default: fst();
}
0x3: decode MODRM_MOD {
0x3: Inst::UD2();
default: fstp();
}
0x4: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: fchs();
0x1: fabs();
0x4: ftst();
0x5: fxam();
default: Inst::UD2();
}
default: fldenv();
}
0x5: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: fld1();
0x1: fldl2t();
0x2: fldl2e();
0x3: fldpi();
0x4: fldlg2();
0x5: fldln2();
0x6: fldz();
}
default: fldcw_Mw();
}
0x6: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: f2xm1();
0x1: fyl2x();
0x2: fptan();
0x3: fpatan();
0x4: fxtract();
0x5: fprem1();
0x6: fdecstp();
0x7: fincstp();
}
default: fnstenv();
}
0x7: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: fprem();
0x1: fyl2xp1();
0x2: fsqrt();
0x3: fsincos();
0x4: frndint();
0x5: fscale();
0x6: fsin();
0x7: fcos();
}
default: fnstcw_Mw();
}
}
//0x2: esc2();
0x2: decode MODRM_REG {
0x0: decode MODRM_MOD {
0x3: fcmovb();
default: fiadd();
}
0x1: decode MODRM_MOD {
0x3: fcmove();
default: fimul();
}
0x2: decode MODRM_MOD {
0x3: fcmovbe();
default: ficom();
}
0x3: decode MODRM_MOD {
0x3: fcmovu();
default: ficomp();
}
0x4: decode MODRM_MOD {
0x3: Inst::UD2();
default: fisub();
}
0x5: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x1: fucompp();
default: Inst::UD2();
}
default: fisubr();
}
0x6: decode MODRM_MOD {
0x3: Inst::UD2();
default: fidiv();
}
0x7: decode MODRM_MOD {
0x3: Inst::UD2();
default: fidivr();
}
}
//0x3: esc3();
0x3: decode MODRM_REG {
0x0: decode MODRM_MOD {
0x3: fcmovnb();
default: fild();
}
0x1: decode MODRM_MOD {
0x3: fcmovne();
default: fisttp();
}
0x2: decode MODRM_MOD {
0x3: fcmovnbe();
default: fist();
}
0x3: decode MODRM_MOD {
0x3: fcmovnu();
default: fistp();
}
0x4: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x2: fnclex();
0x3: fninit();
default: Inst::UD2();
}
default: Inst::UD2();
}
0x5: decode MODRM_MOD {
0x3: fucomi();
default: fld();
}
0x6: decode MODRM_MOD {
0x3: fcomi();
default: Inst::UD2();
}
0x7: decode MODRM_MOD {
0x3: Inst::UD2();
default: fstp();
}
}
//0x4: esc4();
0x4: decode MODRM_REG {
0x0: fadd();
0x1: fmul();
0x2: decode MODRM_MOD {
0x3: Inst::UD2();
default: fcom();
}
0x3: decode MODRM_MOD {
0x3: Inst::UD2();
default: fcomp();
}
0x4: decode MODRM_MOD {
0x3: fsubr();
default: fsub();
}
0x5: decode MODRM_MOD {
0x3: fsub();
default: fsubr();
}
0x6: decode MODRM_MOD {
0x3: fdivr();
default: fdiv();
}
0x7: decode MODRM_MOD {
0x3: fdiv();
default: fdivr();
}
}
//0x5: esc5();
0x5: decode MODRM_REG {
0x0: decode MODRM_MOD {
0x3: ffree();
default: Inst::FLD(Mq);
}
0x1: decode MODRM_MOD {
0x3: Inst::UD2();
default: fisttp();
}
0x2: Inst::FST(Eq);
0x3: Inst::FSTP(Eq);
0x4: decode MODRM_MOD {
0x3: fucom();
default: frstor();
}
0x5: decode MODRM_MOD {
0x3: fucomp();
default: Inst::UD2();
}
0x6: decode MODRM_MOD {
0x3: Inst::UD2();
default: fnsave();
}
0x7: decode MODRM_MOD {
0x3: Inst::UD2();
default: fnstsw();
}
}
//0x6: esc6();
0x6: decode MODRM_REG {
0x0: decode MODRM_MOD {
0x3: faddp();
default: fiadd();
}
0x1: decode MODRM_MOD {
0x3: fmulp();
default: fimul();
}
0x2: decode MODRM_MOD {
0x3: Inst::UD2();
default: ficom();
}
0x3: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x1: fcompp();
default: Inst::UD2();
}
default: ficomp();
}
0x4: decode MODRM_MOD {
0x3: fsubrp();
default: fisub();
}
0x5: decode MODRM_MOD {
0x3: fsubp();
default: fisubr();
}
0x6: decode MODRM_MOD {
0x3: fdivrp();
default: fidiv();
}
0x7: decode MODRM_MOD {
0x3: fdivp();
default: fidivr();
}
}
//0x7: esc7();
0x7: decode MODRM_REG {
0x0: decode MODRM_MOD {
// The ffreep instruction isn't entirely real. It should work
// the same as ffree but then also pop the register stack.
0x3: ffreep();
default: fild();
}
0x1: decode MODRM_MOD {
0x3: Inst::UD2();
default: fisttp();
}
0x2: decode MODRM_MOD {
0x3: Inst::UD2();
default: fist();
}
0x3: decode MODRM_MOD {
0x3: Inst::UD2();
default: fistp();
}
0x4: decode MODRM_MOD {
0x3: decode MODRM_RM {
0x0: fnstsw();
default: Inst::UD2();
}
default: fbld();
}
0x5: decode MODRM_MOD {
0x3: fucomip();
default: fild();
}
0x6: decode MODRM_MOD {
0x3: fcomip();
default: fbstp();
}
0x7: decode MODRM_MOD {
0x3: Inst::UD2();
default: fistp();
}
}
}
}

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// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
// Definitions of execute methods that panic.
def template BasicExecPanic {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
{
panic("Execute method called when it shouldn't!");
M5_DUMMY_RETURN
}
}};
// Basic instruction class declaration template.
def template BasicDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
};
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
}
}};
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
}
}};
// Basic decode template.
def template BasicDecode {{
return new %(class_name)s(machInst);
}};
// Basic decode template, passing mnemonic in as string arg to constructor.
def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'X86ISA::X86StaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

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// Copyright (c) 2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
output header {{
class CPUIDInst : public X86ISA::X86StaticInst
{
public:
static const RegIndex foldOBit = 0;
/// Constructor
CPUIDInst(const char *_mnemonic, ExtMachInst _machInst,
OpClass __opClass) :
X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
{
flags[IsSerializing] = 1;
flags[IsSerializeAfter] = 1;
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string CPUIDInst::generateDisassembly(Addr PC,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
ccprintf(response, " ");
printReg(response, _srcRegIdx[0], machInst.opSize);
return response.str();
}
}};
def template CPUIDExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
// If the CPUID instruction used a valid function number, this will
// be set to true. Otherwise, the instruction does nothing.
%(op_decl)s;
%(op_rd)s;
%(code)s;
%(op_wb)s;
return NoFault;
}
}};
def format CPUIDInst(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'CPUIDInst', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = CPUIDExecute.subst(iop)
}};

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// -*- mode:c++ -*-
// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// "Format" which really indicates an internal error. This is a more
// significant problem for x86 than for other ISAs because of it's complex
// ExtMachInst type.
//
def template ErrorDecode {{
{
panic("X86 decoder internal error: '%s' %s",
%(message)s, machInst);
}
}};
def format M5InternalError(error_message) {{
iop = InstObjParams(name, 'M5InternalError')
iop.message = error_message
decode_block = ErrorDecode.subst(iop)
}};

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// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
//Include the basic format
//Templates from this format are used later
##include "basic.isa"
//Include a format to generate a CPUID instruction.
##include "cpuid.isa"
//Include the "unknown" format
##include "unknown.isa"
//Include the "unimp" format
##include "unimp.isa"
//Include a format to signal m5 internal errors. This is used to indicate a
//malfunction of the decode mechanism.
##include "error.isa"
//Include a format which implements a batch of instructions which do the same
//thing on a variety of inputs
##include "multi.isa"
//Include a format for a non-microcoded nop.
##include "nop.isa"
//Include a format which implements an extra layer of decoding to handle the
//repe and repne prefixes
##include "string.isa"
//Include a format which makes instructions who's sole purpose is to generate
//a syscall.
##include "syscall.isa"

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// -*- mode:c++ -*-
// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
//////////////////////////////////////////////////////////////////////////
//
// Instructions operate on one or multiple types of sets of arguments.
//
//////////////////////////////////////////////////////////////////////////
def format Inst(*opTypeSet) {{
blocks = specializeInst(Name, list(opTypeSet), EmulEnv())
(header_output, decoder_output,
decode_block, exec_output) = blocks.makeList()
}};
def format MultiInst(switchVal, *opTypeSets) {{
switcher = {}
for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets):
switcher[count] = (specializeInst, Name, opTypeSet, EmulEnv())
blocks = doSplitDecode(switchVal, switcher)
(header_output, decoder_output,
decode_block, exec_output) = blocks.makeList()
}};

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// -*- mode:c++ -*-
// Copyright (c) 2010 Advanced Micro Devices, Inc.
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// "Format" which describes an instruction whose only purpose is to
// call a syscall in SE mode.
//
output header {{
class NopInst : public X86ISA::X86StaticInst
{
public:
static const RegIndex foldOBit = 0;
/// Constructor
NopInst(const char *_mnemonic, ExtMachInst _machInst,
OpClass __opClass) :
X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string NopInst::generateDisassembly(Addr PC,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
return response.str();
}
}};
def template NopExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
return NoFault;
}
}};
def format NopInst(*opt_flags) {{
iop = InstObjParams(name, Name, 'NopInst', "", opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = NopExecute.subst(iop)
}};

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// -*- mode:c++ -*-
// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
//////////////////////////////////////////////////////////////////////////
//
// String Instructions
//
//////////////////////////////////////////////////////////////////////////
def format StringTestInst(*opTypeSet) {{
allBlocks = OutputBlocks()
regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv())
eBlocks = specializeInst(Name + "_E", list(opTypeSet), EmulEnv())
nBlocks = specializeInst(Name + "_N", list(opTypeSet), EmulEnv())
for blocks in (regBlocks, eBlocks, nBlocks):
allBlocks.header_output += blocks.header_output
allBlocks.decoder_output += blocks.decoder_output
allBlocks.exec_output += blocks.exec_output
allBlocks.decode_block = '''
if (LEGACY_REP) {
%s
} else if (LEGACY_REPNE) {
%s
} else {
%s
}
''' % (eBlocks.decode_block, nBlocks.decode_block, regBlocks.decode_block)
(header_output, decoder_output,
decode_block, exec_output) = allBlocks.makeList()
}};
def format StringInst(*opTypeSet) {{
allBlocks = OutputBlocks()
regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv())
eBlocks = specializeInst(Name + "_E", list(opTypeSet), EmulEnv())
for blocks in (regBlocks, eBlocks):
allBlocks.header_output += blocks.header_output
allBlocks.decoder_output += blocks.decoder_output
allBlocks.exec_output += blocks.exec_output
allBlocks.decode_block = '''
if (LEGACY_REP) {
%s
} else if (LEGACY_REPNE) {
// The repne prefix is illegal
return new MicroFault(machInst, "illprefix", 0,
new InvalidOpcode, 0);
} else {
%s
}
''' % (eBlocks.decode_block, regBlocks.decode_block)
(header_output, decoder_output,
decode_block, exec_output) = allBlocks.makeList()
}};

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// -*- mode:c++ -*-
// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// "Format" which describes an instruction whose only purpose is to
// call a syscall in SE mode.
//
output header {{
class SyscallInst : public X86ISA::X86StaticInst
{
public:
static const RegIndex foldOBit = 0;
/// Constructor
SyscallInst(const char *_mnemonic, ExtMachInst _machInst,
OpClass __opClass) :
X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string SyscallInst::generateDisassembly(Addr PC,
const SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, mnemonic);
ccprintf(response, " ");
printReg(response, _srcRegIdx[0], machInst.opSize);
return response.str();
}
}};
def template SyscallExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(code)s;
return fault;
}
}};
def format SyscallInst(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'SyscallInst', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = SyscallExecute.subst(iop)
}};

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// -*- mode:c++ -*-
// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Unimplemented instructions
//
output header {{
/**
* Static instruction class for unimplemented instructions that
* cause simulator termination. Note that these are recognized
* (legal) instructions that the simulator does not support; the
* 'Unknown' class is used for unrecognized/illegal instructions.
* This is a leaf class.
*/
class FailUnimplemented : public X86ISA::X86StaticInst
{
public:
/// Constructor
FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: X86ISA::X86StaticInst(_mnemonic, _machInst, No_OpClass)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
/**
* Base class for unimplemented instructions that cause a warning
* to be printed (but do not terminate simulation). This
* implementation is a little screwy in that it will print a
* warning for each instance of a particular unimplemented machine
* instruction, not just for each unimplemented opcode. Should
* probably make the 'warned' flag a static member of the derived
* class.
*/
class WarnUnimplemented : public X86ISA::X86StaticInst
{
private:
/// Have we warned on this instruction yet?
mutable bool warned;
public:
/// Constructor
WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: X86ISA::X86StaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
{
// don't call execute() (which panics) if we're on a
// speculative path
flags[IsNonSpeculative] = true;
}
%(BasicExecDeclare)s
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string
FailUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
#ifdef SS_COMPATIBLE_DISASSEMBLY
return csprintf("%-10s", mnemonic);
#else
return csprintf("%-10s (unimplemented)", mnemonic);
#endif
}
}};
output exec {{
Fault
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' %s",
mnemonic, machInst);
return NoFault;
}
Fault
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);
warned = true;
}
return NoFault;
}
}};
def format FailUnimpl() {{
iop = InstObjParams(name, 'FailUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};
def format WarnUnimpl() {{
iop = InstObjParams(name, 'WarnUnimplemented')
decode_block = BasicDecodeWithMnemonic.subst(iop)
}};

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// Copyright (c) 2007 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Unknown instructions
//
output header {{
/**
* Class for Unknown/Illegal instructions
*/
class Unknown : public X86ISA::X86StaticInst
{
public:
// Constructor
Unknown(ExtMachInst _machInst) :
X86ISA::X86StaticInst("unknown", _machInst, No_OpClass)
{
}
%(BasicExecDeclare)s
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string Unknown::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
return "Unknown instruction";
}
}};
output exec {{
Fault Unknown::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
return new InvalidOpcode();
}
}};
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};

131
simulators/gem5/src/arch/x86/isa/includes.isa Normal file
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// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
////////////////////////////////////////////////////////////////////
//
// Output include file directives. Also import the python modules we
// need for all the x86 custom decoder stuff
//
let {{
import copy
}};
output header {{
#include <cstring>
#include <iostream>
#include <sstream>
#include "arch/generic/debugfaults.hh"
#include "arch/x86/insts/macroop.hh"
#include "arch/x86/insts/microfpop.hh"
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/insts/micromediaop.hh"
#include "arch/x86/insts/microregop.hh"
#include "arch/x86/insts/static_inst.hh"
#include "arch/x86/emulenv.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/registers.hh"
#include "arch/x86/types.hh"
#include "base/misc.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "sim/faults.hh"
using X86ISA::InstRegIndex;
}};
output decoder {{
#include "arch/x86/decoder.hh"
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/segment.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/microcode_rom.hh"
#include "arch/x86/tlb.hh"
#include "base/loader/symtab.hh"
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
#include "sim/full_system.hh"
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
#endif
#include <algorithm>
using namespace X86ISA;
}};
output exec {{
#if defined(linux) || defined(__APPLE__)
#include <fenv.h>
#endif
#if defined(__sun) || defined (__OpenBSD__)
#include <ieeefp.h>
#endif
#include <cmath>
#include <limits>
#include "arch/generic/debugfaults.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/cpuid.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/memhelpers.hh"
#include "arch/x86/tlb.hh"
#include "base/bigint.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/X86.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
using namespace X86ISA;
using namespace std;
}};

50
simulators/gem5/src/arch/x86/isa/insts/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["romutil",
"general_purpose",
"simd128",
"simd64",
"system",
"x87"]
microcode = '''
# X86 microcode
'''
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

60
simulators/gem5/src/arch/x86/isa/insts/general_purpose/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["arithmetic",
"cache_and_memory_management",
"compare_and_test",
"control_transfer",
"data_conversion",
"data_transfer",
"flags",
"input_output",
"load_effective_address",
"load_segment_registers",
"logical",
"no_operation",
"rotate_and_shift",
"semaphores",
"string",
"system_calls"]
microcode = '''
# Microcode for general purpose instructions
'''
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

46
simulators/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["add_and_subtract",
"increment_and_decrement",
"multiply_and_divide"]
microcode = ""
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

461
simulators/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop ADD_R_R
{
add reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADD_R_I
{
limm t1, imm
add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADD_M_I
{
limm t2, imm
ldst t1, seg, sib, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop ADD_P_I
{
rdip t7
limm t2, imm
ldst t1, seg, riprel, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop ADD_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADD_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADD_M_R
{
ldst t1, seg, sib, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop ADD_P_R
{
rdip t7
ldst t1, seg, riprel, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop ADD_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADD_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADD_R_M
{
ld t1, seg, sib, disp
add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADD_R_P
{
rdip t7
ld t1, seg, riprel, disp
add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_R_R
{
sub reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_R_I
{
limm t1, imm
sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_R_M
{
ld t1, seg, sib, disp
sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_R_P
{
rdip t7
ld t1, seg, riprel, disp
sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_M_I
{
limm t2, imm
ldst t1, seg, sib, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop SUB_P_I
{
rdip t7
limm t2, imm
ldst t1, seg, riprel, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop SUB_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SUB_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop SUB_M_R
{
ldst t1, seg, sib, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop SUB_P_R
{
rdip t7
ldst t1, seg, riprel, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop SUB_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SUB_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADC_R_R
{
adc reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADC_R_I
{
limm t1, imm
adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADC_M_I
{
limm t2, imm
ldst t1, seg, sib, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop ADC_P_I
{
rdip t7
limm t2, imm
ldst t1, seg, riprel, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop ADC_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADC_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADC_M_R
{
ldst t1, seg, sib, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop ADC_P_R
{
rdip t7
ldst t1, seg, riprel, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop ADC_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop ADC_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop ADC_R_M
{
ld t1, seg, sib, disp
adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADC_R_P
{
rdip t7
ld t1, seg, riprel, disp
adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_R_R
{
sbb reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_R_I
{
limm t1, imm
sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_R_M
{
ld t1, seg, sib, disp
sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_R_P
{
rdip t7
ld t1, seg, riprel, disp
sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_M_I
{
limm t2, imm
ldst t1, seg, sib, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop SBB_P_I
{
rdip t7
limm t2, imm
ldst t1, seg, riprel, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop SBB_LOCKED_M_I
{
limm t2, imm
mfence
ldstl t1, seg, sib, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SBB_LOCKED_P_I
{
rdip t7
limm t2, imm
mfence
ldstl t1, seg, riprel, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop SBB_M_R
{
ldst t1, seg, sib, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, sib, disp
};
def macroop SBB_P_R
{
rdip t7
ldst t1, seg, riprel, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, seg, riprel, disp
};
def macroop SBB_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
mfence
};
def macroop SBB_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
mfence
};
def macroop NEG_R
{
sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
};
def macroop NEG_M
{
ldst t1, seg, sib, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, seg, sib, disp
};
def macroop NEG_P
{
rdip t7
ldst t1, seg, riprel, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, seg, riprel, disp
};
def macroop NEG_LOCKED_M
{
mfence
ldstl t1, seg, sib, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
stul t1, seg, sib, disp
mfence
};
def macroop NEG_LOCKED_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
stul t1, seg, riprel, disp
mfence
};
'''

116
simulators/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop INC_R
{
addi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
};
def macroop INC_M
{
ldst t1, seg, sib, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, seg, sib, disp
};
def macroop INC_P
{
rdip t7
ldst t1, seg, riprel, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, seg, riprel, disp
};
def macroop INC_LOCKED_M
{
mfence
ldstl t1, seg, sib, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, sib, disp
mfence
};
def macroop INC_LOCKED_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, riprel, disp
mfence
};
def macroop DEC_R
{
subi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
};
def macroop DEC_M
{
ldst t1, seg, sib, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, seg, sib, disp
};
def macroop DEC_P
{
rdip t7
ldst t1, seg, riprel, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, seg, riprel, disp
};
def macroop DEC_LOCKED_M
{
mfence
ldstl t1, seg, sib, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, sib, disp
mfence
};
def macroop DEC_LOCKED_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
stul t1, seg, riprel, disp
mfence
};
'''

436
simulators/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
#
# Byte version of one operand unsigned multiply.
#
def macroop MUL_B_R
{
mul1u rax, reg, flags=(OF,CF)
mulel rax
muleh ah
};
def macroop MUL_B_M
{
ld t1, seg, sib, disp
mul1u rax, t1, flags=(OF,CF)
mulel rax
muleh ah
};
def macroop MUL_B_P
{
rdip t7
ld t1, seg, riprel, disp
mul1u rax, t1, flags=(OF,CF)
mulel rax
muleh ah
};
#
# One operand unsigned multiply.
#
def macroop MUL_R
{
mul1u rax, reg, flags=(OF,CF)
mulel rax
muleh rdx
};
def macroop MUL_M
{
ld t1, seg, sib, disp
mul1u rax, t1, flags=(OF,CF)
mulel rax
muleh rdx
};
def macroop MUL_P
{
rdip t7
ld t1, seg, riprel, disp
mul1u rax, t1, flags=(OF,CF)
mulel rax
muleh rdx
};
#
# Byte version of one operand signed multiply.
#
def macroop IMUL_B_R
{
mul1s rax, reg, flags=(OF,CF)
mulel rax
muleh ah
};
def macroop IMUL_B_M
{
ld t1, seg, sib, disp
mul1s rax, t1, flags=(OF,CF)
mulel rax
muleh ah
};
def macroop IMUL_B_P
{
rdip t7
ld t1, seg, riprel, disp
mul1s rax, t1, flags=(OF,CF)
mulel rax
muleh ah
};
#
# One operand signed multiply.
#
def macroop IMUL_R
{
mul1s rax, reg, flags=(OF,CF)
mulel rax
muleh rdx
};
def macroop IMUL_M
{
ld t1, seg, sib, disp
mul1s rax, t1, flags=(OF,CF)
mulel rax
muleh rdx
};
def macroop IMUL_P
{
rdip t7
ld t1, seg, riprel, disp
mul1s rax, t1, flags=(OF,CF)
mulel rax
muleh rdx
};
def macroop IMUL_R_R
{
mul1s reg, regm, flags=(OF,CF)
mulel reg
muleh t0
};
def macroop IMUL_R_M
{
ld t1, seg, sib, disp
mul1s reg, t1, flags=(CF,OF)
mulel reg
muleh t0
};
def macroop IMUL_R_P
{
rdip t7
ld t1, seg, riprel, disp
mul1s reg, t1, flags=(CF,OF)
mulel reg
muleh t0
};
#
# Three operand signed multiply.
#
def macroop IMUL_R_R_I
{
limm t1, imm
mul1s regm, t1, flags=(OF,CF)
mulel reg
muleh t0
};
def macroop IMUL_R_M_I
{
limm t1, imm
ld t2, seg, sib, disp
mul1s t2, t1, flags=(OF,CF)
mulel reg
muleh t0
};
def macroop IMUL_R_P_I
{
rdip t7
limm t1, imm
ld t2, seg, riprel, disp
mul1s t2, t1, flags=(OF,CF)
mulel reg
muleh t0
};
'''
pcRel = '''
rdip t7
ld %s, seg, riprel, disp
'''
sibRel = '''
ld %s, seg, sib, disp
'''
#
# One byte version of unsigned division
#
divcode = '''
def macroop DIV_B_%(suffix)s
{
%(readOp1)s
# Do the initial part of the division
div1 ah, %(op1)s, dataSize=1
#These are split out so we can initialize the number of bits in the
#second register
div2i t1, rax, 8, dataSize=1
div2 t1, rax, t1, dataSize=1
#Loop until we're out of bits to shift in
divLoopTop:
div2 t1, rax, t1, dataSize=1
div2 t1, rax, t1, flags=(EZF,), dataSize=1
br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax, dataSize=1
divr ah, dataSize=1
};
'''
#
# Unsigned division
#
divcode += '''
def macroop DIV_%(suffix)s
{
%(readOp1)s
# Do the initial part of the division
div1 rdx, %(op1)s
#These are split out so we can initialize the number of bits in the
#second register
div2i t1, rax, "env.dataSize * 8"
div2 t1, rax, t1
#Loop until we're out of bits to shift in
#The amount of unrolling here could stand some tuning
divLoopTop:
div2 t1, rax, t1
div2 t1, rax, t1
div2 t1, rax, t1
div2 t1, rax, t1, flags=(EZF,)
br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq rax
divr rdx
};
'''
#
# One byte version of signed division
#
divcode += '''
def macroop IDIV_B_%(suffix)s
{
# Negate dividend
sub t1, t0, rax, flags=(ECF,), dataSize=1
ruflag t4, 3
sub t2, t0, ah, dataSize=1
sub t2, t2, t4
%(readOp1)s
#Find the sign of the divisor
slli t0, %(op1)s, 1, flags=(ECF,), dataSize=1
# Negate divisor
sub t3, t0, %(op1)s, dataSize=1
# Put the divisor's absolute value into t3
mov t3, t3, %(op1)s, flags=(nCECF,), dataSize=1
#Find the sign of the dividend
slli t0, ah, 1, flags=(ECF,), dataSize=1
# Put the dividend's absolute value into t1 and t2
mov t1, t1, rax, flags=(nCECF,), dataSize=1
mov t2, t2, ah, flags=(nCECF,), dataSize=1
# Do the initial part of the division
div1 t2, t3, dataSize=1
#These are split out so we can initialize the number of bits in the
#second register
div2i t4, t1, 8, dataSize=1
div2 t4, t1, t4, dataSize=1
#Loop until we're out of bits to shift in
divLoopTop:
div2 t4, t1, t4, dataSize=1
div2 t4, t1, t4, flags=(EZF,), dataSize=1
br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5, dataSize=1
divr t6, dataSize=1
# Fix up signs. The sign of the dividend is still lying around in ECF.
# The sign of the remainder, ah, is the same as the dividend. The sign
# of the quotient is negated if the signs of the divisor and dividend
# were different.
# Negate the remainder
sub t4, t0, t6, dataSize=1
# If the dividend was negitive, put the negated remainder in ah.
mov ah, ah, t4, (CECF,), dataSize=1
# Otherwise put the regular remainder in ah.
mov ah, ah, t6, (nCECF,), dataSize=1
# Negate the quotient.
sub t4, t0, t5, dataSize=1
# If the dividend was negative, start using the negated quotient
mov t5, t5, t4, (CECF,), dataSize=1
# Check the sign of the divisor
slli t0, %(op1)s, 1, flags=(ECF,), dataSize=1
# Negate the (possibly already negated) quotient
sub t4, t0, t5, dataSize=1
# If the divisor was negative, put the negated quotient in rax.
mov rax, rax, t4, (CECF,), dataSize=1
# Otherwise put the one that wasn't negated (at least here) in rax.
mov rax, rax, t5, (nCECF,), dataSize=1
};
'''
#
# Signed division
#
divcode += '''
def macroop IDIV_%(suffix)s
{
# Negate dividend
sub t1, t0, rax, flags=(ECF,)
ruflag t4, 3
sub t2, t0, rdx
sub t2, t2, t4
%(readOp1)s
#Find the sign of the divisor
slli t0, %(op1)s, 1, flags=(ECF,)
# Negate divisor
sub t3, t0, %(op1)s
# Put the divisor's absolute value into t3
mov t3, t3, %(op1)s, flags=(nCECF,)
#Find the sign of the dividend
slli t0, rdx, 1, flags=(ECF,)
# Put the dividend's absolute value into t1 and t2
mov t1, t1, rax, flags=(nCECF,)
mov t2, t2, rdx, flags=(nCECF,)
# Do the initial part of the division
div1 t2, t3
#These are split out so we can initialize the number of bits in the
#second register
div2i t4, t1, "env.dataSize * 8"
div2 t4, t1, t4
#Loop until we're out of bits to shift in
divLoopTop:
div2 t4, t1, t4
div2 t4, t1, t4
div2 t4, t1, t4
div2 t4, t1, t4, flags=(EZF,)
br label("divLoopTop"), flags=(nCEZF,)
#Unload the answer
divq t5
divr t6
# Fix up signs. The sign of the dividend is still lying around in ECF.
# The sign of the remainder, ah, is the same as the dividend. The sign
# of the quotient is negated if the signs of the divisor and dividend
# were different.
# Negate the remainder
sub t4, t0, t6
# If the dividend was negitive, put the negated remainder in rdx.
mov rdx, rdx, t4, (CECF,)
# Otherwise put the regular remainder in rdx.
mov rdx, rdx, t6, (nCECF,)
# Negate the quotient.
sub t4, t0, t5
# If the dividend was negative, start using the negated quotient
mov t5, t5, t4, (CECF,)
# Check the sign of the divisor
slli t0, %(op1)s, 1, flags=(ECF,)
# Negate the (possibly already negated) quotient
sub t4, t0, t5
# If the divisor was negative, put the negated quotient in rax.
mov rax, rax, t4, (CECF,)
# Otherwise put the one that wasn't negated (at least here) in rax.
mov rax, rax, t5, (nCECF,)
};
'''
microcode += divcode % {"suffix": "R",
"readOp1": "", "op1": "reg"}
microcode += divcode % {"suffix": "M",
"readOp1": sibRel % "t2", "op1": "t2"}
microcode += divcode % {"suffix": "P",
"readOp1": pcRel % "t2", "op1": "t2"}

76
simulators/gem5/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop PREFETCH_M
{
ld t0, seg, sib, disp, dataSize=1, prefetch=True
};
def macroop PREFETCH_P
{
rdip t7
ld t0, seg, riprel, disp, dataSize=1, prefetch=True
};
def macroop PREFETCH_T0_M
{
ld t0, seg, sib, disp, dataSize=1, prefetch=True
};
def macroop PREFETCH_T0_P
{
rdip t7
ld t0, seg, riprel, disp, dataSize=1, prefetch=True
};
'''
#let {{
# class LFENCE(Inst):
# "GenFault ${new UnimpInstFault}"
# class SFENCE(Inst):
# "GenFault ${new UnimpInstFault}"
# class MFENCE(Inst):
# "GenFault ${new UnimpInstFault}"
# class PREFETCHlevel(Inst):
# "GenFault ${new UnimpInstFault}"
# class PREFETCHW(Inst):
# "GenFault ${new UnimpInstFault}"
# class CLFLUSH(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

48
simulators/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["bit_scan",
"bit_test",
"bounds",
"compare",
"set_byte_on_condition",
"test"]
microcode = ""
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

355
simulators/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop BSR_R_R {
# Determine if the input was zero, and also move it to a temp reg.
mov t1, t1, t0, dataSize=8
and t1, regm, regm, flags=(ZF,)
br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0x0
# Bit 6
srli t3, t1, 32, dataSize=8, flags=(EZF,)
ori t4, reg, 0x20
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5
srli t3, t1, 16, dataSize=8, flags=(EZF,)
ori t4, reg, 0x10
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4
srli t3, t1, 8, dataSize=8, flags=(EZF,)
ori t4, reg, 0x8
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3
srli t3, t1, 4, dataSize=8, flags=(EZF,)
ori t4, reg, 0x4
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2
srli t3, t1, 2, dataSize=8, flags=(EZF,)
ori t4, reg, 0x2
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1
srli t3, t1, 1, dataSize=8, flags=(EZF,)
ori t4, reg, 0x1
mov reg, reg, t4, flags=(nCEZF,)
end:
fault "NoFault"
};
def macroop BSR_R_M {
mov t1, t1, t0, dataSize=8
ld t1, seg, sib, disp
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0x0
# Bit 6
srli t3, t1, 32, dataSize=8, flags=(EZF,)
ori t4, reg, 0x20
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5
srli t3, t1, 16, dataSize=8, flags=(EZF,)
ori t4, reg, 0x10
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4
srli t3, t1, 8, dataSize=8, flags=(EZF,)
ori t4, reg, 0x8
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3
srli t3, t1, 4, dataSize=8, flags=(EZF,)
ori t4, reg, 0x4
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2
srli t3, t1, 2, dataSize=8, flags=(EZF,)
ori t4, reg, 0x2
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1
srli t3, t1, 1, dataSize=8, flags=(EZF,)
ori t4, reg, 0x1
mov reg, reg, t4, flags=(nCEZF,)
end:
fault "NoFault"
};
def macroop BSR_R_P {
rdip t7
mov t1, t1, t0, dataSize=8
ld t1, seg, riprel, disp
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0x0
# Bit 6
srli t3, t1, 32, dataSize=8, flags=(EZF,)
ori t4, reg, 0x20
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5
srli t3, t1, 16, dataSize=8, flags=(EZF,)
ori t4, reg, 0x10
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4
srli t3, t1, 8, dataSize=8, flags=(EZF,)
ori t4, reg, 0x8
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3
srli t3, t1, 4, dataSize=8, flags=(EZF,)
ori t4, reg, 0x4
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2
srli t3, t1, 2, dataSize=8, flags=(EZF,)
ori t4, reg, 0x2
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1
srli t3, t1, 1, dataSize=8, flags=(EZF,)
ori t4, reg, 0x1
mov reg, reg, t4, flags=(nCEZF,)
end:
fault "NoFault"
};
def macroop BSF_R_R {
# Determine if the input was zero, and also move it to a temp reg.
mov t1, t1, t0, dataSize=8
and t1, regm, regm, flags=(ZF,)
br label("end"), flags=(CZF,)
# Zero out the result register
movi reg, reg, 0
subi t2, t1, 1
xor t1, t2, t1
# Bit 6
srli t3, t1, 32, dataSize=8, flags=(EZF,)
ori t4, reg, 32
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5
srli t3, t1, 16, dataSize=8, flags=(EZF,)
ori t4, reg, 16
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4
srli t3, t1, 8, dataSize=8, flags=(EZF,)
ori t4, reg, 8
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3
srli t3, t1, 4, dataSize=8, flags=(EZF,)
ori t4, reg, 4
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2
srli t3, t1, 2, dataSize=8, flags=(EZF,)
ori t4, reg, 2
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1
srli t3, t1, 1, dataSize=8, flags=(EZF,)
ori t4, reg, 1
mov reg, reg, t4, flags=(nCEZF,)
end:
fault "NoFault"
};
def macroop BSF_R_M {
mov t1, t1, t0, dataSize=8
ld t1, seg, sib, disp
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
br label("end"), flags=(CZF,)
# Zero out the result register
mov reg, reg, t0
subi t2, t1, 1
xor t1, t2, t1
# Bit 6
srli t3, t1, 32, dataSize=8, flags=(EZF,)
ori t4, reg, 32
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5
srli t3, t1, 16, dataSize=8, flags=(EZF,)
ori t4, reg, 16
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4
srli t3, t1, 8, dataSize=8, flags=(EZF,)
ori t4, reg, 8
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3
srli t3, t1, 4, dataSize=8, flags=(EZF,)
ori t4, reg, 4
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2
srli t3, t1, 2, dataSize=8, flags=(EZF,)
ori t4, reg, 2
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1
srli t3, t1, 1, dataSize=8, flags=(EZF,)
ori t4, reg, 1
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
end:
fault "NoFault"
};
def macroop BSF_R_P {
rdip t7
mov t1, t1, t0, dataSize=8
ld t1, seg, riprel, disp
# Determine if the input was zero, and also move it to a temp reg.
and t1, t1, t1, flags=(ZF,)
br label("end"), flags=(CZF,)
# Zero out the result register
mov reg, reg, t0
subi t2, t1, 1
xor t1, t2, t1
# Bit 6
srli t3, t1, 32, dataSize=8, flags=(EZF,)
ori t4, reg, 32
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 5
srli t3, t1, 16, dataSize=8, flags=(EZF,)
ori t4, reg, 16
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 4
srli t3, t1, 8, dataSize=8, flags=(EZF,)
ori t4, reg, 8
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 3
srli t3, t1, 4, dataSize=8, flags=(EZF,)
ori t4, reg, 4
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 2
srli t3, t1, 2, dataSize=8, flags=(EZF,)
ori t4, reg, 2
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
# Bit 1
srli t3, t1, 1, dataSize=8, flags=(EZF,)
ori t4, reg, 1
mov reg, reg, t4, flags=(nCEZF,)
mov t1, t1, t3, flags=(nCEZF,)
end:
fault "NoFault"
};
'''

422
simulators/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop BT_R_I {
sexti t0, reg, imm, flags=(CF,)
};
def macroop BT_M_I {
limm t1, imm, dataSize=asz
# This fudges just a tiny bit, but it's reasonable to expect the
# microcode generation logic to have the log of the various sizes
# floating around as well.
ld t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
};
def macroop BT_P_I {
rdip t7
limm t1, imm, dataSize=asz
ld t1, seg, riprel, disp, dataSize=asz
sexti t0, t1, imm, flags=(CF,)
};
def macroop BT_R_R {
sext t0, reg, regm, flags=(CF,)
};
def macroop BT_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
ld t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
};
def macroop BT_P_R {
rdip t7
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
ld t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
};
def macroop BTC_R_I {
sexti t0, reg, imm, flags=(CF,)
limm t1, 1
roli t1, t1, imm
xor reg, reg, t1
};
def macroop BTC_M_I {
limm t1, imm, dataSize=asz
# This fudges just a tiny bit, but it's reasonable to expect the
# microcode generation logic to have the log of the various sizes
# floating around as well.
limm t4, 1
roli t4, t4, imm
ldst t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t4
st t1, seg, sib, disp
};
def macroop BTC_P_I {
rdip t7, dataSize=asz
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
ldst t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t4
st t1, seg, riprel, disp
};
def macroop BTC_LOCKED_M_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t4
stul t1, seg, sib, disp
mfence
};
def macroop BTC_LOCKED_P_I {
rdip t7, dataSize=asz
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
xor t1, t1, t4
stul t1, seg, riprel, disp
mfence
};
def macroop BTC_R_R {
sext t0, reg, regm, flags=(CF,)
limm t1, 1
rol t1, t1, regm
xor reg, reg, t1
};
def macroop BTC_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
ldst t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t4
st t1, seg, [scale, index, t3], disp
};
def macroop BTC_P_R {
rdip t7, dataSize=asz
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
limm t4, 1
rol t4, t4, reg
ldst t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t4
st t1, seg, [dsz, t3, t7], disp
};
def macroop BTC_LOCKED_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t4
stul t1, seg, [scale, index, t3], disp
mfence
};
def macroop BTC_LOCKED_P_R {
rdip t7, dataSize=asz
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
xor t1, t1, t4
stul t1, seg, [dsz, t3, t7], disp
mfence
};
def macroop BTR_R_I {
sexti t0, reg, imm, flags=(CF,)
limm t1, "(uint64_t(-(2ULL)))"
roli t1, t1, imm
and reg, reg, t1
};
def macroop BTR_M_I {
limm t1, imm, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
roli t4, t4, imm
ldst t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t4
st t1, seg, sib, disp
};
def macroop BTR_P_I {
rdip t7, dataSize=asz
limm t1, imm, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
roli t4, t4, imm
ldst t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t4
st t1, seg, riprel, disp
};
def macroop BTR_LOCKED_M_I {
limm t1, imm, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
roli t4, t4, imm
mfence
ldstl t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t4
stul t1, seg, sib, disp
mfence
};
def macroop BTR_LOCKED_P_I {
rdip t7, dataSize=asz
limm t1, imm, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
roli t4, t4, imm
mfence
ldstl t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
and t1, t1, t4
stul t1, seg, riprel, disp
mfence
};
def macroop BTR_R_R {
sext t0, reg, regm, flags=(CF,)
limm t1, "(uint64_t(-(2ULL)))"
rol t1, t1, regm
and reg, reg, t1
};
def macroop BTR_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
rol t4, t4, reg
ldst t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
and t1, t1, t4
st t1, seg, [scale, index, t3], disp
};
def macroop BTR_P_R {
rdip t7, dataSize=asz
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
rol t4, t4, reg
ldst t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
and t1, t1, t4
st t1, seg, [dsz, t3, t7], disp
};
def macroop BTR_LOCKED_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
rol t4, t4, reg
mfence
ldstl t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
and t1, t1, t4
stul t1, seg, [scale, index, t3], disp
mfence
};
def macroop BTR_LOCKED_P_R {
rdip t7, dataSize=asz
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
limm t4, "(uint64_t(-(2ULL)))"
rol t4, t4, reg
mfence
ldstl t1, seg, [dsz, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
and t1, t1, t4
stul t1, seg, [dsz, t3, t7], disp
mfence
};
def macroop BTS_R_I {
sexti t0, reg, imm, flags=(CF,)
limm t1, 1
roli t1, t1, imm
or reg, reg, t1
};
def macroop BTS_M_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
ldst t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t4
st t1, seg, sib, disp
};
def macroop BTS_P_I {
rdip t7, dataSize=asz
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
ldst t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t4
st t1, seg, riprel, disp
};
def macroop BTS_LOCKED_M_I {
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, sib, disp
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t4
stul t1, seg, sib, disp
mfence
};
def macroop BTS_LOCKED_P_I {
rdip t7, dataSize=asz
limm t1, imm, dataSize=asz
limm t4, 1
roli t4, t4, imm
mfence
ldstl t1, seg, riprel, disp
sexti t0, t1, imm, flags=(CF,)
or t1, t1, t4
stul t1, seg, riprel, disp
mfence
};
def macroop BTS_R_R {
sext t0, reg, regm, flags=(CF,)
limm t1, 1
rol t1, t1, regm
or reg, reg, t1
};
def macroop BTS_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
ldst t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
or t1, t1, t4
st t1, seg, [scale, index, t3], disp
};
def macroop BTS_P_R {
rdip t7, dataSize=asz
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
ldst t1, seg, [1, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
or t1, t1, t4
st t1, seg, [1, t3, t7], disp
};
def macroop BTS_LOCKED_M_R {
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [scale, index, t3], disp
sext t0, t1, reg, flags=(CF,)
or t1, t1, t4
stul t1, seg, [scale, index, t3], disp
mfence
};
def macroop BTS_LOCKED_P_R {
rdip t7, dataSize=asz
srai t2, reg, 3, dataSize=asz
srai t3, t2, ldsz, dataSize=asz
lea t3, flatseg, [dsz, t3, base], dataSize=asz
limm t4, 1
rol t4, t4, reg
mfence
ldstl t1, seg, [1, t3, t7], disp
sext t0, t1, reg, flags=(CF,)
or t1, t1, t4
stul t1, seg, [1, t3, t7], disp
mfence
};
'''

51
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop BOUND_R_M {
ld t1, seg, sib, disp, dataSize="env.dataSize * 2"
srli t2, t1, "env.dataSize * 8"
sub t1, t1, reg, flags=(ECF,)
fault "new BoundRange", flags=(CECF,)
sub t2, reg, t2, flags=(ECF,)
fault "new BoundRange", flags=(CECF,)
};
def macroop BOUND_R_P {
fault "new UnimpInstFault"
};
'''

90
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop CMP_R_M
{
ld t1, seg, sib, disp
sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_R_P
{
rdip t7
ld t1, seg, riprel, disp
sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_M_I
{
limm t2, imm
ld t1, seg, sib, disp
sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_P_I
{
limm t2, imm
rdip t7
ld t1, seg, riprel, disp
sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_M_R
{
ld t1, seg, sib, disp
sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_P_R
{
rdip t7
ld t1, seg, riprel, disp
sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_R_R
{
sub t0, reg, regm, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_R_I
{
limm t1, imm
sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
'''

379
simulators/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/set_byte_on_condition.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop SALC_R
{
sbb reg, reg, reg, dataSize=1
};
def macroop SETZ_R
{
movi reg, reg, 1, flags=(CZF,)
movi reg, reg, 0, flags=(nCZF,)
};
def macroop SETZ_M
{
movi t1, t1, 1, flags=(CZF,)
movi t1, t1, 0, flags=(nCZF,)
st t1, seg, sib, disp
};
def macroop SETZ_P
{
rdip t7
movi t1, t1, 1, flags=(CZF,)
movi t1, t1, 0, flags=(nCZF,)
st t1, seg, riprel, disp
};
def macroop SETNZ_R
{
movi reg, reg, 1, flags=(nCZF,)
movi reg, reg, 0, flags=(CZF,)
};
def macroop SETNZ_M
{
movi t1, t1, 1, flags=(nCZF,)
movi t1, t1, 0, flags=(CZF,)
st t1, seg, sib, disp
};
def macroop SETNZ_P
{
rdip t7
movi t1, t1, 1, flags=(nCZF,)
movi t1, t1, 0, flags=(CZF,)
st t1, seg, riprel, disp
};
def macroop SETB_R
{
movi reg, reg, 1, flags=(CCF,)
movi reg, reg, 0, flags=(nCCF,)
};
def macroop SETB_M
{
movi t1, t1, 1, flags=(CCF,)
movi t1, t1, 0, flags=(nCCF,)
st t1, seg, sib, disp
};
def macroop SETB_P
{
rdip t7
movi t1, t1, 1, flags=(CCF,)
movi t1, t1, 0, flags=(nCCF,)
st t1, seg, riprel, disp
};
def macroop SETNB_R
{
movi reg, reg, 1, flags=(nCCF,)
movi reg, reg, 0, flags=(CCF,)
};
def macroop SETNB_M
{
movi t1, t1, 1, flags=(nCCF,)
movi t1, t1, 0, flags=(CCF,)
st t1, seg, sib, disp
};
def macroop SETNB_P
{
rdip t7
movi t1, t1, 1, flags=(nCCF,)
movi t1, t1, 0, flags=(CCF,)
st t1, seg, riprel, disp
};
def macroop SETBE_R
{
movi reg, reg, 1, flags=(CCvZF,)
movi reg, reg, 0, flags=(nCCvZF,)
};
def macroop SETBE_M
{
movi t1, t1, 1, flags=(CCvZF,)
movi t1, t1, 0, flags=(nCCvZF,)
st t1, seg, sib, disp
};
def macroop SETBE_P
{
rdip t7
movi t1, t1, 1, flags=(CCvZF,)
movi t1, t1, 0, flags=(nCCvZF,)
st t1, seg, riprel, disp
};
def macroop SETNBE_R
{
movi reg, reg, 1, flags=(nCCvZF,)
movi reg, reg, 0, flags=(CCvZF,)
};
def macroop SETNBE_M
{
movi t1, t1, 1, flags=(nCCvZF,)
movi t1, t1, 0, flags=(CCvZF,)
st t1, seg, sib, disp
};
def macroop SETNBE_P
{
rdip t7
movi t1, t1, 1, flags=(nCCvZF,)
movi t1, t1, 0, flags=(CCvZF,)
st t1, seg, riprel, disp
};
def macroop SETS_R
{
movi reg, reg, 1, flags=(CSF,)
movi reg, reg, 0, flags=(nCSF,)
};
def macroop SETS_M
{
movi t1, t1, 1, flags=(CSF,)
movi t1, t1, 0, flags=(nCSF,)
st t1, seg, sib, disp
};
def macroop SETS_P
{
rdip t7
movi t1, t1, 1, flags=(CSF,)
movi t1, t1, 0, flags=(nCSF,)
st t1, seg, riprel, disp
};
def macroop SETNS_R
{
movi reg, reg, 1, flags=(nCSF,)
movi reg, reg, 0, flags=(CSF,)
};
def macroop SETNS_M
{
movi t1, t1, 1, flags=(nCSF,)
movi t1, t1, 0, flags=(CSF,)
st t1, seg, sib, disp
};
def macroop SETNS_P
{
rdip t7
movi t1, t1, 1, flags=(nCSF,)
movi t1, t1, 0, flags=(CSF,)
st t1, seg, riprel, disp
};
def macroop SETP_R
{
movi reg, reg, 1, flags=(CPF,)
movi reg, reg, 0, flags=(nCPF,)
};
def macroop SETP_M
{
movi t1, t1, 1, flags=(CPF,)
movi t1, t1, 0, flags=(nCPF,)
st t1, seg, sib, disp
};
def macroop SETP_P
{
rdip t7
movi t1, t1, 1, flags=(CPF,)
movi t1, t1, 0, flags=(nCPF,)
st t1, seg, riprel, disp
};
def macroop SETNP_R
{
movi reg, reg, 1, flags=(nCPF,)
movi reg, reg, 0, flags=(CPF,)
};
def macroop SETNP_M
{
movi t1, t1, 1, flags=(nCPF,)
movi t1, t1, 0, flags=(CPF,)
st t1, seg, sib, disp
};
def macroop SETNP_P
{
rdip t7
movi t1, t1, 1, flags=(nCPF,)
movi t1, t1, 0, flags=(CPF,)
st t1, seg, riprel, disp
};
def macroop SETL_R
{
movi reg, reg, 1, flags=(CSxOF,)
movi reg, reg, 0, flags=(nCSxOF,)
};
def macroop SETL_M
{
movi t1, t1, 1, flags=(CSxOF,)
movi t1, t1, 0, flags=(nCSxOF,)
st t1, seg, sib, disp
};
def macroop SETL_P
{
rdip t7
movi t1, t1, 1, flags=(CSxOF,)
movi t1, t1, 0, flags=(nCSxOF,)
st t1, seg, riprel, disp
};
def macroop SETNL_R
{
movi reg, reg, 1, flags=(nCSxOF,)
movi reg, reg, 0, flags=(CSxOF,)
};
def macroop SETNL_M
{
movi t1, t1, 1, flags=(nCSxOF,)
movi t1, t1, 0, flags=(CSxOF,)
st t1, seg, sib, disp
};
def macroop SETNL_P
{
rdip t7
movi t1, t1, 1, flags=(nCSxOF,)
movi t1, t1, 0, flags=(CSxOF,)
st t1, seg, riprel, disp
};
def macroop SETLE_R
{
movi reg, reg, 1, flags=(CSxOvZF,)
movi reg, reg, 0, flags=(nCSxOvZF,)
};
def macroop SETLE_M
{
movi t1, t1, 1, flags=(CSxOvZF,)
movi t1, t1, 0, flags=(nCSxOvZF,)
st t1, seg, sib, disp
};
def macroop SETLE_P
{
rdip t7
movi t1, t1, 1, flags=(CSxOvZF,)
movi t1, t1, 0, flags=(nCSxOvZF,)
st t1, seg, riprel, disp
};
def macroop SETNLE_R
{
movi reg, reg, 1, flags=(nCSxOvZF,)
movi reg, reg, 0, flags=(CSxOvZF,)
};
def macroop SETNLE_M
{
movi t1, t1, 1, flags=(nCSxOvZF,)
movi t1, t1, 0, flags=(CSxOvZF,)
st t1, seg, sib, disp
};
def macroop SETNLE_P
{
rdip t7
movi t1, t1, 1, flags=(nCSxOvZF,)
movi t1, t1, 0, flags=(CSxOvZF,)
st t1, seg, riprel, disp
};
def macroop SETO_R
{
movi reg, reg, 1, flags=(COF,)
movi reg, reg, 0, flags=(nCOF,)
};
def macroop SETO_M
{
movi t1, t1, 1, flags=(COF,)
movi t1, t1, 0, flags=(nCOF,)
st t1, seg, sib, disp
};
def macroop SETO_P
{
rdip t7
movi t1, t1, 1, flags=(COF,)
movi t1, t1, 0, flags=(nCOF,)
st t1, seg, riprel, disp
};
def macroop SETNO_R
{
movi reg, reg, 1, flags=(nCOF,)
movi reg, reg, 0, flags=(COF,)
};
def macroop SETNO_M
{
movi t1, t1, 1, flags=(nCOF,)
movi t1, t1, 0, flags=(COF,)
st t1, seg, sib, disp
};
def macroop SETNO_P
{
rdip t7
movi t1, t1, 1, flags=(nCOF,)
movi t1, t1, 0, flags=(COF,)
st t1, seg, riprel, disp
};
'''

77
simulators/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/test.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop TEST_M_R
{
ld t1, seg, sib, disp
and t0, t1, reg, flags=(OF, SF, ZF, PF, CF)
};
def macroop TEST_P_R
{
rdip t7
ld t1, seg, riprel, disp
and t0, t1, reg, flags=(OF, SF, ZF, PF, CF)
};
def macroop TEST_R_R
{
and t0, reg, regm, flags=(OF, SF, ZF, PF, CF)
};
def macroop TEST_M_I
{
ld t1, seg, sib, disp
limm t2, imm
and t0, t1, t2, flags=(OF, SF, ZF, PF, CF)
};
def macroop TEST_P_I
{
rdip t7
ld t1, seg, riprel, disp
limm t2, imm
and t0, t1, t2, flags=(OF, SF, ZF, PF, CF)
};
def macroop TEST_R_I
{
limm t1, imm
and t0, reg, t1, flags=(OF, SF, ZF, PF, CF)
};
'''

48
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["call",
"conditional_jump",
"interrupts_and_exceptions",
"jump",
"loop",
"xreturn"]
microcode = ""
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

93
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop CALL_NEAR_I
{
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
limm t1, imm
rdip t7
# Check target of call
st t7, ss, [0, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
wrip t7, t1
};
def macroop CALL_NEAR_R
{
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
# Check target of call
st t1, ss, [0, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
wripi reg, 0
};
def macroop CALL_NEAR_M
{
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t7
ld t1, seg, sib, disp
# Check target of call
st t7, ss, [0, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
wripi t1, 0
};
def macroop CALL_NEAR_P
{
# Make the default data size of calls 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t7
ld t1, seg, riprel, disp
# Check target of call
st t7, ss, [0, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
wripi t1, 0
};
'''
#let {{
# class CALL(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

205
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop JZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CZF,)
};
def macroop JNZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCZF,)
};
def macroop JB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCF,)
};
def macroop JNB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCF,)
};
def macroop JBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCvZF,)
};
def macroop JNBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCvZF,)
};
def macroop JS_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSF,)
};
def macroop JNS_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSF,)
};
def macroop JP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CPF,)
};
def macroop JNP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCPF,)
};
def macroop JL_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSxOF,)
};
def macroop JNL_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSxOF,)
};
def macroop JLE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSxOvZF,)
};
def macroop JNLE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSxOvZF,)
};
def macroop JO_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(COF,)
};
def macroop JNO_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCOF,)
};
def macroop JRCX_I
{
rdip t1
add t0, t0, rcx, flags=(EZF,), dataSize=asz
wripi t1, imm, flags=(CEZF,)
};
'''

230
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop IRET_REAL {
.serializing
panic "Real mode iret isn't implemented!"
};
def macroop IRET_PROT {
.serializing
.adjust_env oszIn64Override
# Check for a nested task. This isn't supported at the moment.
rflag t1, 14; #NT bit
panic "Task switching with iret is unimplemented!", flags=(nCEZF,)
#t1 = temp_RIP
#t2 = temp_CS
#t3 = temp_RFLAGS
#t4 = handy m5 register
# Pop temp_RIP, temp_CS, and temp_RFLAGS
ld t1, ss, [1, t0, rsp], "0 * env.stackSize", dataSize=ssz
ld t2, ss, [1, t0, rsp], "1 * env.stackSize", dataSize=ssz
ld t3, ss, [1, t0, rsp], "2 * env.stackSize", dataSize=ssz
# Read the handy m5 register for use later
rdm5reg t4
###
### Handle if we're returning to virtual 8086 mode.
###
#IF ((temp_RFLAGS.VM=1) && (CPL=0) && (LEGACY_MODE))
# IRET_FROM_PROTECTED_TO_VIRTUAL
#temp_RFLAGS.VM != 1
rcri t0, t3, 18, flags=(ECF,)
br label("protToVirtFallThrough"), flags=(nCECF,)
#CPL=0
andi t0, t4, 0x30, flags=(EZF,)
br label("protToVirtFallThrough"), flags=(nCEZF,)
#(LEGACY_MODE)
rcri t0, t4, 1, flags=(ECF,)
br label("protToVirtFallThrough"), flags=(nCECF,)
panic "iret to virtual mode not supported"
protToVirtFallThrough:
#temp_CPL = temp_CS.rpl
andi t5, t2, 0x3
###
### Read in the info for the new CS segment.
###
#CS = READ_DESCRIPTOR (temp_CS, iret_chk)
andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
br label("processCSDescriptor"), flags=(CEZF,)
andi t6, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
br label("globalCSDescriptor"), flags=(CEZF,)
ld t8, tsl, [1, t0, t6], dataSize=8, atCPL0=True
br label("processCSDescriptor")
globalCSDescriptor:
ld t8, tsg, [1, t0, t6], dataSize=8, atCPL0=True
processCSDescriptor:
chks t2, t6, dataSize=8
###
### Get the new stack pointer and stack segment off the old stack if necessary,
### and piggyback on the logic to check the new RIP value.
###
#IF ((64BIT_MODE) || (temp_CPL!=CPL))
#{
#(64BIT_MODE)
andi t0, t4, 0xE, flags=(EZF,)
# Since we just found out we're in 64 bit mode, take advantage and
# do the appropriate RIP checks.
br label("doPopStackStuffAndCheckRIP"), flags=(CEZF,)
# Here, we know we're -not- in 64 bit mode, so we should do the
# appropriate/other RIP checks.
# if temp_RIP > CS.limit throw #GP(0)
rdlimit t6, cs, dataSize=8
sub t0, t1, t6, flags=(ECF,)
fault "new GeneralProtection(0)", flags=(CECF,)
#(temp_CPL!=CPL)
srli t7, t4, 4
xor t7, t7, t5
andi t0, t7, 0x3, flags=(EZF,)
br label("doPopStackStuff"), flags=(nCEZF,)
# We can modify user visible state here because we're know
# we're done with things that can fault.
addi rsp, rsp, "3 * env.stackSize"
br label("fallThroughPopStackStuff")
doPopStackStuffAndCheckRIP:
# Check if the RIP is canonical.
srai t7, t1, 47, flags=(EZF,), dataSize=ssz
# if t7 isn't 0 or -1, it wasn't canonical.
br label("doPopStackStuff"), flags=(CEZF,)
addi t0, t7, 1, flags=(EZF,), dataSize=ssz
fault "new GeneralProtection(0)", flags=(nCEZF,)
doPopStackStuff:
# POP.v temp_RSP
ld t6, ss, [1, t0, rsp], "3 * env.dataSize", dataSize=ssz
# POP.v temp_SS
ld t9, ss, [1, t0, rsp], "4 * env.dataSize", dataSize=ssz
# SS = READ_DESCRIPTOR (temp_SS, ss_chk)
andi t0, t9, 0xFC, flags=(EZF,), dataSize=2
br label("processSSDescriptor"), flags=(CEZF,)
andi t7, t9, 0xF8, dataSize=8
andi t0, t9, 0x4, flags=(EZF,), dataSize=2
br label("globalSSDescriptor"), flags=(CEZF,)
ld t7, tsl, [1, t0, t7], dataSize=8, atCPL0=True
br label("processSSDescriptor")
globalSSDescriptor:
ld t7, tsg, [1, t0, t7], dataSize=8, atCPL0=True
processSSDescriptor:
chks t9, t7, dataSize=8
# This actually updates state which is wrong. It should wait until we know
# we're not going to fault. Unfortunately, that's hard to do.
wrdl ss, t7, t9
wrsel ss, t9
###
### From this point downwards, we can't fault. We can update user visible state.
###
# RSP.s = temp_RSP
mov rsp, rsp, t6, dataSize=ssz
#}
fallThroughPopStackStuff:
# Update CS
wrdl cs, t8, t2
wrsel cs, t2
#CPL = temp_CPL
#IF (changing CPL)
#{
srli t7, t4, 4
xor t7, t7, t5
andi t0, t7, 0x3, flags=(EZF,)
br label("skipSegmentSquashing"), flags=(CEZF,)
# The attribute register needs to keep track of more info before this will
# work the way it needs to.
# FOR (seg = ES, DS, FS, GS)
# IF ((seg.attr.dpl < cpl && ((seg.attr.type = 'data')
# || (seg.attr.type = 'non-conforming-code')))
# {
# seg = NULL
# }
#}
skipSegmentSquashing:
# Ignore this for now.
#RFLAGS.v = temp_RFLAGS
wrflags t0, t3
# VIF,VIP,IOPL only changed if (old_CPL = 0)
# IF only changed if (old_CPL <= old_RFLAGS.IOPL)
# VM unchanged
# RF cleared
#RIP = temp_RIP
wrip t0, t1, dataSize=ssz
};
def macroop IRET_VIRT {
panic "Virtual mode iret isn't implemented!"
};
'''
#let {{
# class INT(Inst):
# "GenFault ${new UnimpInstFault}"
# class INTO(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

174
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop JMP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2
};
def macroop JMP_R
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
wripi reg, 0
};
def macroop JMP_M
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, seg, sib, disp
wripi t1, 0
};
def macroop JMP_P
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t7
ld t1, seg, riprel, disp
wripi t1, 0
};
def macroop JMP_FAR_M
{
limm t1, 0, dataSize=8
limm t2, 0, dataSize=8
lea t1, seg, sib, disp, dataSize=asz
ld t2, seg, [1, t0, t1], dsz
ld t1, seg, [1, t0, t1]
br rom_label("jmpFarWork")
};
def macroop JMP_FAR_P
{
limm t1, 0, dataSize=8
limm t2, 0, dataSize=8
rdip t7, dataSize=asz
lea t1, seg, riprel, disp, dataSize=asz
ld t2, seg, [1, t0, t1], dsz
ld t1, seg, [1, t0, t1]
br rom_label("jmpFarWork")
};
def macroop JMP_FAR_I
{
# Put the whole far pointer into a register.
limm t2, imm, dataSize=8
# Figure out the width of the offset.
limm t3, dsz, dataSize=8
slli t3, t3, 3, dataSize=8
# Get the offset into t1.
mov t1, t0, t2
# Get the selector into t2.
srl t2, t2, t3, dataSize=8
mov t2, t0, t2, dataSize=2
br rom_label("jmpFarWork")
};
def rom
{
extern jmpFarWork:
# t1 has the offset and t2 has the new selector.
# This is intended to run in protected mode.
andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
fault "new GeneralProtection(0)", flags=(CEZF,)
andi t3, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
br rom_local_label("farJmpGlobalDescriptor"), flags=(CEZF,)
ld t4, tsl, [1, t0, t3], dataSize=8, addressSize=8, atCPL0=True
br rom_local_label("farJmpProcessDescriptor")
farJmpGlobalDescriptor:
ld t4, tsg, [1, t0, t3], dataSize=8, addressSize=8, atCPL0=True
farJmpProcessDescriptor:
rcri t0, t4, 13, flags=(ECF,), dataSize=2
br rom_local_label("farJmpSystemDescriptor"), flags=(nCECF,)
chks t2, t4, CSCheck, dataSize=8
wrdl cs, t4, t2
wrsel cs, t2
wrip t0, t1
eret
farJmpSystemDescriptor:
panic "Far jumps to system descriptors aren't implemented"
eret
};
def macroop JMP_FAR_REAL_M
{
lea t1, seg, sib, disp, dataSize=asz
ld t2, seg, [1, t0, t1], dsz
ld t1, seg, [1, t0, t1]
zexti t3, t1, 15, dataSize=8
slli t3, t3, 4, dataSize=8
wrsel cs, t1, dataSize=2
wrbase cs, t3
wrip t0, t2, dataSize=asz
};
def macroop JMP_FAR_REAL_P
{
panic "Real mode far jump executed in 64 bit mode!"
};
def macroop JMP_FAR_REAL_I
{
# Put the whole far pointer into a register.
limm t2, imm, dataSize=8
# Figure out the width of the offset.
limm t3, dsz, dataSize=8
slli t3, t3, 3, dataSize=8
# Get the selector into t1.
sll t1, t2, t3, dataSize=8
mov t1, t0, t1, dataSize=2
# And get the offset into t2
mov t2, t0, t2
slli t3, t3, 4, dataSize=8
wrsel cs, t1, dataSize=2
wrbase cs, t3
wrip t0, t2, dataSize=asz
};
'''

56
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop LOOP_I {
rdip t1
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
wripi t1, imm, flags=(nCEZF,)
};
def macroop LOOPNE_I {
rdip t1
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
wripi t1, imm, flags=(CSTRnZnEZF,)
};
def macroop LOOPE_I {
rdip t1
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
wripi t1, imm, flags=(CSTRZnEZF,)
};
'''

103
simulators/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop RET_NEAR
{
# Make the default data size of rets 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ss, [1, t0, rsp]
# Check address of return
addi rsp, rsp, dsz
wripi t1, 0
};
def macroop RET_NEAR_I
{
# Make the default data size of rets 64 bits in 64 bit mode
.adjust_env oszIn64Override
limm t2, imm
ld t1, ss, [1, t0, rsp]
# Check address of return
addi rsp, rsp, dsz
add rsp, rsp, t2
wripi t1, 0
};
def macroop RET_FAR {
.adjust_env oszIn64Override
# Get the return RIP
ld t1, ss, [1, t0, rsp]
# Get the return CS
ld t2, ss, [1, t0, rsp], ssz
# Get the rpl
andi t3, t2, 0x3
# Get the cpl
# Here we'd check if we're changing priviledge levels. We'll just hope
# that doesn't happen yet.
# Do stuff if they're equal
andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t3, t2, 0xF8, dataSize=8
andi t0, t2, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t3], dataSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t3], dataSize=8
processDescriptor:
chks t2, t3, IretCheck, dataSize=8
# There should be validity checks on the RIP checks here, but I'll do
# that later.
wrdl cs, t3, t2
wrsel cs, t2
wrip t0, t1
br label("end")
# Do other stuff if they're not.
end:
fault "NoFault"
};
'''

48
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["ascii_adjust",
"bcd_adjust",
"endian_conversion",
"extract_sign_mask",
"sign_extension",
"translate"]
microcode = ""
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

48
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = ""
#let {{
# class AAA(Inst):
# "GenFault ${new UnimpInstFault}"
# class AAD(Inst):
# "GenFault ${new UnimpInstFault}"
# class AAM(Inst):
# "GenFault ${new UnimpInstFault}"
# class AAS(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

44
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = ""
#let {{
# class DAA(Inst):
# "GenFault ${new UnimpInstFault}"
# class DAS(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

60
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop BSWAP_D_R
{
roli reg, reg, 8, dataSize=2
roli reg, reg, 16, dataSize=4
roli reg, reg, 8, dataSize=2
};
def macroop BSWAP_Q_R
{
roli reg, reg, 8, dataSize=2
roli t1, reg, 16, dataSize=4
# Top 4 bytes of t1 are now zero
roli t1, t1, 8, dataSize=2
roli t1, t1, 32, dataSize=8
srli t2, reg, 32, dataSize=8
roli t2, t2, 8, dataSize=2
roli t2, t2, 16, dataSize=4
# Top 4 bytes of t2 are now zero
roli t2, t2, 8, dataSize=2
or reg, t1, t2, dataSize=8
};
'''

44
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = ""
#let {{
# class MOVMSKPS(Inst):
# "GenFault ${new UnimpInstFault}"
# class MOVMSKPD(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

49
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop CDQE_R {
sexti reg, reg, "env.dataSize * 4 - 1"
};
def macroop CQO_R_R {
# A shift might be slower than, for example, an explicit sign extension,
# so it might be worthwhile to try to find an alternative.
mov regm, regm, reg
srai regm, regm, "env.dataSize * 8 - 1"
};
'''

46
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop XLAT {
zexti t1, rax, 7, dataSize=8
# Here, t1 can be used directly. The value of al is supposed to be treated
# as unsigned. Since we zero extended it from 8 bits above and the address
# size has to be at least 16 bits, t1 will not be sign extended.
ld rax, seg, [1, rbx, t1], dataSize=1
};
'''

46
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["conditional_move",
"move",
"stack_operations",
"xchg"]
microcode = ""
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

374
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop CMOVZ_R_R
{
mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, regm, flags=(CZF,)
};
def macroop CMOVZ_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVZ_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCZF,)
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVNZ_R_R
{
mov reg, reg, reg, flags=(CZF,)
mov reg, reg, regm, flags=(nCZF,)
};
def macroop CMOVNZ_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CZF,)
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVNZ_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CZF,)
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVB_R_R
{
mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, regm, flags=(CCF,)
};
def macroop CMOVB_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVB_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCCF,)
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVNB_R_R
{
mov reg, reg, reg, flags=(CCF,)
mov reg, reg, regm, flags=(nCCF,)
};
def macroop CMOVNB_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CCF,)
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVNB_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CCF,)
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVBE_R_R
{
mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, regm, flags=(CCvZF,)
};
def macroop CMOVBE_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVBE_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCCvZF,)
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVNBE_R_R
{
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, regm, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVS_R_R
{
mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, regm, flags=(CSF,)
};
def macroop CMOVS_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVS_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCSF,)
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVNS_R_R
{
mov reg, reg, reg, flags=(CSF,)
mov reg, reg, regm, flags=(nCSF,)
};
def macroop CMOVNS_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CSF,)
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVNS_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CSF,)
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVP_R_R
{
mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, regm, flags=(CPF,)
};
def macroop CMOVP_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVP_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCPF,)
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVNP_R_R
{
mov reg, reg, reg, flags=(CPF,)
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVNP_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CPF,)
mov reg, reg, t1, flags=(nCPF,)
};
def macroop CMOVNP_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CPF,)
mov reg, reg, t1, flags=(nCPF,)
};
def macroop CMOVL_R_R
{
mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, regm, flags=(CSxOF,)
};
def macroop CMOVL_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVL_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCSxOF,)
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVNL_R_R
{
mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, regm, flags=(nCSxOF,)
};
def macroop CMOVNL_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVNL_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CSxOF,)
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVLE_R_R
{
mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, regm, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCSxOvZF,)
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVNLE_R_R
{
mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, regm, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CSxOvZF,)
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVO_R_R
{
mov reg, reg, reg, flags=(nCOF,)
mov reg, reg, regm, flags=(COF,)
};
def macroop CMOVO_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(nCOF,)
mov reg, reg, t1, flags=(COF,)
};
def macroop CMOVO_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(nCOF,)
mov reg, reg, t1, flags=(COF,)
};
def macroop CMOVNO_R_R
{
mov reg, reg, reg, flags=(COF,)
mov reg, reg, regm, flags=(nCOF,)
};
def macroop CMOVNO_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(COF,)
mov reg, reg, t1, flags=(nCOF,)
};
def macroop CMOVNO_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(COF,)
mov reg, reg, t1, flags=(nCOF,)
};
'''

377
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
#
# Regular moves
#
def macroop MOV_R_MI {
limm t1, imm, dataSize=asz
ld reg, seg, [1, t0, t1]
};
def macroop MOV_MI_R {
limm t1, imm, dataSize=asz
st reg, seg, [1, t0, t1]
};
def macroop MOV_R_R {
mov reg, reg, regm
};
def macroop MOV_M_R {
st reg, seg, sib, disp
};
def macroop MOV_P_R {
rdip t7
st reg, seg, riprel, disp
};
def macroop MOV_R_M {
ld reg, seg, sib, disp
};
def macroop MOV_R_P {
rdip t7
ld reg, seg, riprel, disp
};
def macroop MOV_R_I {
limm reg, imm
};
def macroop MOV_M_I {
limm t1, imm
st t1, seg, sib, disp
};
def macroop MOV_P_I {
rdip t7
limm t1, imm
st t1, seg, riprel, disp
};
#
# Sign extending moves
#
def macroop MOVSXD_R_R {
sexti reg, regm, 31
};
def macroop MOVSXD_R_M {
ld t1, seg, sib, disp, dataSize=4
sexti reg, t1, 31
};
def macroop MOVSXD_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=4
sexti reg, t1, 31
};
def macroop MOVSX_B_R_R {
mov t1, t1, regm, dataSize=1
sexti reg, t1, 7
};
def macroop MOVSX_B_R_M {
ld t1, seg, sib, disp, dataSize=1
sexti reg, t1, 7
};
def macroop MOVSX_B_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=1
sexti reg, t1, 7
};
def macroop MOVSX_W_R_R {
sexti reg, regm, 15
};
def macroop MOVSX_W_R_M {
ld reg, seg, sib, disp, dataSize=2
sexti reg, reg, 15
};
def macroop MOVSX_W_R_P {
rdip t7
ld reg, seg, riprel, disp, dataSize=2
sexti reg, reg, 15
};
#
# Zero extending moves
#
def macroop MOVZX_B_R_R {
mov t1, t1, regm, dataSize=1
zexti reg, t1, 7
};
def macroop MOVZX_B_R_M {
ld t1, seg, sib, disp, dataSize=1
zexti reg, t1, 7
};
def macroop MOVZX_B_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=1
zexti reg, t1, 7
};
def macroop MOVZX_W_R_R {
zexti reg, regm, 15
};
def macroop MOVZX_W_R_M {
ld t1, seg, sib, disp, dataSize=2
zexti reg, t1, 15
};
def macroop MOVZX_W_R_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=2
zexti reg, t1, 15
};
def macroop MOV_C_R {
.serializing
.adjust_env maxOsz
wrcr reg, regm
};
def macroop MOV_R_C {
.serializing
.adjust_env maxOsz
rdcr reg, regm
};
def macroop MOV_D_R {
.serializing
.adjust_env maxOsz
wrdr reg, regm
};
def macroop MOV_R_D {
.adjust_env maxOsz
rddr reg, regm
};
def macroop MOV_R_S {
rdsel reg, regm
};
def macroop MOV_M_S {
rdsel t1, reg
st t1, seg, sib, disp, dataSize=2
};
def macroop MOV_P_S {
rdip t7
rdsel t1, reg
st t1, seg, riprel, disp, dataSize=2
};
def macroop MOV_REAL_S_R {
zexti t2, regm, 15, dataSize=8
slli t3, t2, 4, dataSize=8
wrsel reg, regm
wrbase reg, t3
};
def macroop MOV_REAL_S_M {
ld t1, seg, sib, disp, dataSize=2
zexti t2, t1, 15, dataSize=8
slli t3, t2, 4, dataSize=8
wrsel reg, t1
wrbase reg, t3
};
def macroop MOV_REAL_S_P {
panic "RIP relative addressing shouldn't happen in real mode"
};
def macroop MOV_S_R {
andi t0, regm, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t2, regm, 0xF8, dataSize=8
andi t0, regm, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
chks regm, t3, dataSize=8
wrdl reg, t3, regm
wrsel reg, regm
};
def macroop MOV_S_M {
ld t1, seg, sib, disp, dataSize=2
andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t2, t1, 0xF8, dataSize=8
andi t0, t1, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
chks t1, t3, dataSize=8
wrdl reg, t3, t1
wrsel reg, t1
};
def macroop MOV_S_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=2
andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t2, t1, 0xF8, dataSize=8
andi t0, t1, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
chks t1, t3, dataSize=8
wrdl reg, t3, t1
wrsel reg, t1
};
def macroop MOVSS_S_R {
andi t0, regm, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t2, regm, 0xF8, dataSize=8
andi t0, regm, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
chks regm, t3, SSCheck, dataSize=8
wrdl reg, t3, regm
wrsel reg, regm
};
def macroop MOVSS_S_M {
ld t1, seg, sib, disp, dataSize=2
andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t2, t1, 0xF8, dataSize=8
andi t0, t1, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
chks t1, t3, SSCheck, dataSize=8
wrdl reg, t3, t1
wrsel reg, t1
};
def macroop MOVSS_S_P {
rdip t7
ld t1, seg, riprel, disp, dataSize=2
andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
br label("processDescriptor"), flags=(CEZF,)
andi t2, t1, 0xF8, dataSize=8
andi t0, t1, 0x4, flags=(EZF,), dataSize=2
br label("globalDescriptor"), flags=(CEZF,)
ld t3, tsl, [1, t0, t2], dataSize=8, addressSize=8
br label("processDescriptor")
globalDescriptor:
ld t3, tsg, [1, t0, t2], dataSize=8, addressSize=8
processDescriptor:
chks t1, t3, SSCheck, dataSize=8
wrdl reg, t3, t1
wrsel reg, t1
};
def macroop MOVNTI_M_R {
st reg, seg, sib, disp
};
def macroop MOVNTI_P_R {
rdip t7
st reg, seg, riprel, disp
};
def macroop MOVD_XMM_R {
mov2fp xmml, regm, srcSize=dsz, destSize=8
lfpimm xmmh, 0
};
def macroop MOVD_XMM_M {
ldfp xmml, seg, sib, disp, dataSize=dsz
lfpimm xmmh, 0
};
def macroop MOVD_XMM_P {
rdip t7
ldfp xmml, seg, riprel, disp, dataSize=dsz
lfpimm xmmh, 0
};
def macroop MOVD_R_XMM {
mov2int reg, xmmlm, size=dsz
};
def macroop MOVD_M_XMM {
stfp xmml, seg, sib, disp, dataSize=dsz
};
def macroop MOVD_P_XMM {
rdip t7
stfp xmml, seg, riprel, disp, dataSize=dsz
};
'''
#let {{
# class MOVD(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

193
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py Normal file
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# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop POP_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ss, [1, t0, rsp], dataSize=ssz
addi rsp, rsp, ssz, dataSize=asz
mov reg, reg, t1
};
def macroop POP_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ss, [1, t0, rsp], dataSize=ssz
cda seg, sib, disp, dataSize=ssz
addi rsp, rsp, ssz, dataSize=asz
st t1, seg, sib, disp, dataSize=ssz
};
def macroop POP_P {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t7
ld t1, ss, [1, t0, rsp], dataSize=ssz
cda seg, sib, disp, dataSize=ssz
addi rsp, rsp, ssz, dataSize=asz
st t1, seg, riprel, disp, dataSize=ssz
};
def macroop PUSH_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
st reg, ss, [1, t0, rsp], "-env.stackSize", dataSize=ssz
subi rsp, rsp, ssz
};
def macroop PUSH_I {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
limm t1, imm
st t1, ss, [1, t0, rsp], "-env.stackSize", dataSize=ssz
subi rsp, rsp, ssz
};
def macroop PUSH_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, seg, sib, disp, dataSize=ssz
st t1, ss, [1, t0, rsp], "-env.stackSize", dataSize=ssz
subi rsp, rsp, ssz
};
def macroop PUSH_P {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t7
ld t1, seg, riprel, disp, dataSize=ssz
st t1, ss, [1, t0, rsp], "-env.stackSize", dataSize=ssz
subi rsp, rsp, ssz
};
def macroop PUSHA {
# Check all the stack addresses. We'll assume that if the beginning and
# end are ok, then the stuff in the middle should be as well.
cda ss, [1, t0, rsp], "-env.stackSize", dataSize=ssz
cda ss, [1, t0, rsp], "-8 * env.stackSize", dataSize=ssz
st rax, ss, [1, t0, rsp], "1 * -env.stackSize", dataSize=ssz
st rcx, ss, [1, t0, rsp], "2 * -env.stackSize", dataSize=ssz
st rdx, ss, [1, t0, rsp], "3 * -env.stackSize", dataSize=ssz
st rbx, ss, [1, t0, rsp], "4 * -env.stackSize", dataSize=ssz
st rsp, ss, [1, t0, rsp], "5 * -env.stackSize", dataSize=ssz
st rbp, ss, [1, t0, rsp], "6 * -env.stackSize", dataSize=ssz
st rsi, ss, [1, t0, rsp], "7 * -env.stackSize", dataSize=ssz
st rdi, ss, [1, t0, rsp], "8 * -env.stackSize", dataSize=ssz
subi rsp, rsp, "8 * env.stackSize"
};
def macroop POPA {
# Check all the stack addresses. We'll assume that if the beginning and
# end are ok, then the stuff in the middle should be as well.
ld t1, ss, [1, t0, rsp], "0 * env.stackSize", dataSize=ssz
ld t2, ss, [1, t0, rsp], "7 * env.stackSize", dataSize=ssz
mov rdi, rdi, t1, dataSize=ssz
ld rsi, ss, [1, t0, rsp], "1 * env.stackSize", dataSize=ssz
ld rbp, ss, [1, t0, rsp], "2 * env.stackSize", dataSize=ssz
ld rbx, ss, [1, t0, rsp], "4 * env.stackSize", dataSize=ssz
ld rdx, ss, [1, t0, rsp], "5 * env.stackSize", dataSize=ssz
ld rcx, ss, [1, t0, rsp], "6 * env.stackSize", dataSize=ssz
mov rax, rax, t2, dataSize=ssz
addi rsp, rsp, "8 * env.stackSize", dataSize=asz
};
def macroop LEAVE {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
mov t1, t1, rbp, dataSize=ssz
ld rbp, ss, [1, t0, t1], dataSize=ssz
mov rsp, rsp, t1, dataSize=ssz
addi rsp, rsp, ssz, dataSize=ssz
};
def macroop ENTER_I_I {
.adjust_env oszIn64Override
# This needs to check all the addresses it writes to before it actually
# writes any values.
# Pull the different components out of the immediate
limm t1, imm, dataSize=8
zexti t2, t1, 15, dataSize=8
srli t1, t1, 16, dataSize=8
zexti t1, t1, 5, dataSize=8
# t1 is now the masked nesting level, and t2 is the amount of storage.
# Push rbp.
st rbp, ss, [1, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
# Save the stack pointer for later
mov t6, t6, rsp
# If the nesting level is zero, skip all this stuff.
sub t0, t1, t0, flags=(EZF,), dataSize=2
br label("skipLoop"), flags=(CEZF,)
# If the level was 1, only push the saved rbp
subi t0, t1, 1, flags=(EZF,)
br label("bottomOfLoop"), flags=(CEZF,)
limm t4, "ULL(-1)", dataSize=8
topOfLoop:
ld t5, ss, [dsz, t4, rbp]
st t5, ss, [1, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
# If we're not done yet, loop
subi t4, t4, 1, dataSize=8
add t0, t4, t1, flags=(EZF,)
br label("topOfLoop"), flags=(nCEZF,)
bottomOfLoop:
# Push the old rbp onto the stack
st t6, ss, [1, t0, rsp], "-env.dataSize"
subi rsp, rsp, ssz
skipLoop:
sub rsp, rsp, t2, dataSize=ssz
mov rbp, rbp, t6
};
'''

107
simulators/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
# All the memory versions need to use LOCK, regardless of if it was set
def macroop XCHG_R_R
{
# Use the xor trick instead of moves to reduce register pressure.
# This probably doesn't make much of a difference, but it's easy.
xor reg, reg, regm
xor regm, regm, reg
xor reg, reg, regm
};
def macroop XCHG_R_M
{
mfence
ldstl t1, seg, sib, disp
stul reg, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_R_P
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
stul reg, seg, riprel, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_M_R
{
mfence
ldstl t1, seg, sib, disp
stul reg, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
stul reg, seg, riprel, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_LOCKED_M_R
{
mfence
ldstl t1, seg, sib, disp
stul reg, seg, sib, disp
mfence
mov reg, reg, t1
};
def macroop XCHG_LOCKED_P_R
{
rdip t7
mfence
ldstl t1, seg, riprel, disp
stul reg, seg, riprel, disp
mfence
mov reg, reg, t1
};
'''

45
simulators/gem5/src/arch/x86/isa/insts/general_purpose/flags/__init__.py Normal file
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# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
categories = ["load_and_store",
"push_and_pop",
"set_and_clear"]
microcode = ""
for category in categories:
exec "import %s as cat" % category
microcode += cat.microcode

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