Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
118
simulators/gem5/src/arch/mips/isa/base.isa
Normal file
118
simulators/gem5/src/arch/mips/isa/base.isa
Normal file
@ -0,0 +1,118 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Base class for MIPS instructions, and some support functions
|
||||
//
|
||||
|
||||
//Outputs to decoder.hh
|
||||
output header {{
|
||||
|
||||
using namespace MipsISA;
|
||||
|
||||
/**
|
||||
* Base class for all MIPS static instructions.
|
||||
*/
|
||||
class MipsStaticInst : public StaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
// Constructor
|
||||
MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
|
||||
: StaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
/// Print a register name for disassembly given the unique
|
||||
/// dependence tag number (FP or int).
|
||||
void printReg(std::ostream &os, int reg) const;
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
public:
|
||||
void
|
||||
advancePC(MipsISA::PCState &pc) const
|
||||
{
|
||||
pc.advance();
|
||||
}
|
||||
};
|
||||
|
||||
}};
|
||||
|
||||
//Ouputs to decoder.cc
|
||||
output decoder {{
|
||||
|
||||
void MipsStaticInst::printReg(std::ostream &os, int reg) const
|
||||
{
|
||||
if (reg < FP_Base_DepTag) {
|
||||
ccprintf(os, "r%d", reg);
|
||||
}
|
||||
else {
|
||||
ccprintf(os, "f%d", reg - FP_Base_DepTag);
|
||||
}
|
||||
}
|
||||
|
||||
std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
// Need to find standard way to not print
|
||||
// this info. Maybe add bool variable to
|
||||
// class?
|
||||
if (strcmp(mnemonic, "syscall") != 0) {
|
||||
if(_numDestRegs > 0){
|
||||
printReg(ss, _destRegIdx[0]);
|
||||
}
|
||||
|
||||
if(_numSrcRegs > 0) {
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
if(_numSrcRegs > 1) {
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[1]);
|
||||
}
|
||||
}
|
||||
|
||||
// Should we define a separate inst. class
|
||||
// just for two insts?
|
||||
if (strcmp(mnemonic, "sll") == 0 || strcmp(mnemonic, "sra") == 0) {
|
||||
ccprintf(ss,", %d",SA);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
}};
|
||||
|
||||
124
simulators/gem5/src/arch/mips/isa/bitfields.isa
Normal file
124
simulators/gem5/src/arch/mips/isa/bitfields.isa
Normal file
@ -0,0 +1,124 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
// Jaidev Patwardhan
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Bitfield definitions.
|
||||
//
|
||||
|
||||
def bitfield OPCODE <31:26>;
|
||||
def bitfield OPCODE_HI <31:29>;
|
||||
def bitfield OPCODE_LO <28:26>;
|
||||
|
||||
def bitfield REGIMM <20:16>;
|
||||
def bitfield REGIMM_HI <20:19>;
|
||||
def bitfield REGIMM_LO <18:16>;
|
||||
|
||||
def bitfield FUNCTION < 5: 0>;
|
||||
def bitfield FUNCTION_HI < 5: 3>;
|
||||
def bitfield FUNCTION_LO < 2: 0>;
|
||||
|
||||
def bitfield RS <25:21>;
|
||||
def bitfield RS_MSB <25:25>;
|
||||
def bitfield RS_HI <25:24>;
|
||||
def bitfield RS_LO <23:21>;
|
||||
def bitfield RS_SRL <25:22>;
|
||||
def bitfield RS_RT <25:16>;
|
||||
def bitfield RT <20:16>;
|
||||
def bitfield RT_HI <20:19>;
|
||||
def bitfield RT_LO <18:16>;
|
||||
def bitfield RT_RD <20:11>;
|
||||
def bitfield RD <15:11>;
|
||||
|
||||
def bitfield INTIMM <15: 0>;
|
||||
def bitfield RS_RT_INTIMM <25: 0>;
|
||||
|
||||
// Floating-point operate format
|
||||
def bitfield FMT <25:21>;
|
||||
def bitfield FR <25:21>;
|
||||
def bitfield FT <20:16>;
|
||||
def bitfield FS <15:11>;
|
||||
def bitfield FD <10:6>;
|
||||
|
||||
def bitfield ND <17:17>;
|
||||
def bitfield TF <16:16>;
|
||||
def bitfield MOVCI <16:16>;
|
||||
def bitfield MOVCF <16:16>;
|
||||
def bitfield SRL <21:21>;
|
||||
def bitfield SRLV < 6: 6>;
|
||||
def bitfield SA <10: 6>;
|
||||
|
||||
// Floating Point Condition Codes
|
||||
def bitfield CC <10:8>;
|
||||
def bitfield BRANCH_CC <20:18>;
|
||||
|
||||
// CP0 Register Select
|
||||
def bitfield SEL < 2: 0>;
|
||||
|
||||
// INTERRUPTS
|
||||
def bitfield SC < 5: 5>;
|
||||
|
||||
// Branch format
|
||||
def bitfield OFFSET <15: 0>; // displacement
|
||||
|
||||
// Jmp format
|
||||
def bitfield JMPTARG <25: 0>;
|
||||
def bitfield HINT <10: 6>;
|
||||
|
||||
def bitfield SYSCALLCODE <25: 6>;
|
||||
def bitfield TRAPCODE <15:13>;
|
||||
|
||||
// EXT/INS instructions
|
||||
def bitfield MSB <15:11>;
|
||||
def bitfield LSB <10: 6>;
|
||||
|
||||
// M5 instructions
|
||||
def bitfield M5FUNC <7:0>;
|
||||
|
||||
// DSP instructions
|
||||
def bitfield OP <10:6>;
|
||||
def bitfield OP_HI <10:9>;
|
||||
def bitfield OP_LO <8:6>;
|
||||
def bitfield DSPSA <23:21>;
|
||||
def bitfield HILOSA <25:20>;
|
||||
def bitfield RDDSPMASK <21:16>;
|
||||
def bitfield WRDSPMASK <16:11>;
|
||||
def bitfield ACSRC <22:21>;
|
||||
def bitfield ACDST <12:11>;
|
||||
def bitfield BP <12:11>;
|
||||
|
||||
// MT Instructions
|
||||
def bitfield POS <10: 6>;
|
||||
def bitfield MT_U <5:5>;
|
||||
def bitfield MT_H <4:4>;
|
||||
|
||||
//Cache Ops
|
||||
def bitfield CACHE_OP <20:16>;
|
||||
2521
simulators/gem5/src/arch/mips/isa/decoder.isa
Normal file
2521
simulators/gem5/src/arch/mips/isa/decoder.isa
Normal file
File diff suppressed because it is too large
Load Diff
99
simulators/gem5/src/arch/mips/isa/formats/basic.isa
Normal file
99
simulators/gem5/src/arch/mips/isa/formats/basic.isa
Normal file
@ -0,0 +1,99 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Steve Reinhardt
|
||||
// Korey Sewell
|
||||
|
||||
// Declarations for execute() methods.
|
||||
def template BasicExecDeclare {{
|
||||
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
|
||||
}};
|
||||
|
||||
// Basic instruction class declaration template.
|
||||
def template BasicDeclare {{
|
||||
/**
|
||||
* Static instruction class for "%(mnemonic)s".
|
||||
*/
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
/// Constructor.
|
||||
%(class_name)s(MachInst machInst);
|
||||
%(BasicExecDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
// Basic instruction class constructor template.
|
||||
def template BasicConstructor {{
|
||||
inline %(class_name)s::%(class_name)s(MachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
|
||||
{
|
||||
%(constructor)s;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
// Basic instruction class execute method template.
|
||||
def template BasicExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(code)s;
|
||||
if(fault == NoFault){
|
||||
%(op_wb)s;
|
||||
}
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Basic decode template.
|
||||
def template BasicDecode {{
|
||||
return new %(class_name)s(machInst);
|
||||
}};
|
||||
|
||||
// Basic decode template, passing mnemonic in as string arg to constructor.
|
||||
def template BasicDecodeWithMnemonic {{
|
||||
return new %(class_name)s("%(mnemonic)s", machInst);
|
||||
}};
|
||||
|
||||
// The most basic instruction format...
|
||||
def format BasicOp(code, *flags) {{
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
329
simulators/gem5/src/arch/mips/isa/formats/branch.isa
Normal file
329
simulators/gem5/src/arch/mips/isa/formats/branch.isa
Normal file
@ -0,0 +1,329 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Control transfer instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
|
||||
#include <iostream>
|
||||
using namespace std;
|
||||
|
||||
/**
|
||||
* Base class for instructions whose disassembly is not purely a
|
||||
* function of the machine instruction (i.e., it depends on the
|
||||
* PC). This class overrides the disassemble() method to check
|
||||
* the PC and symbol table values before re-using a cached
|
||||
* disassembly string. This is necessary for branches and jumps,
|
||||
* where the disassembly string includes the target address (which
|
||||
* may depend on the PC and/or symbol table).
|
||||
*/
|
||||
class PCDependentDisassembly : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
/// Cached program counter from last disassembly
|
||||
mutable Addr cachedPC;
|
||||
|
||||
/// Cached symbol table pointer from last disassembly
|
||||
mutable const SymbolTable *cachedSymtab;
|
||||
|
||||
/// Constructor
|
||||
PCDependentDisassembly(const char *mnem, MachInst _machInst,
|
||||
OpClass __opClass)
|
||||
: MipsStaticInst(mnem, _machInst, __opClass),
|
||||
cachedPC(0), cachedSymtab(0)
|
||||
{
|
||||
}
|
||||
|
||||
const std::string &
|
||||
disassemble(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for branches (PC-relative control transfers),
|
||||
* conditional or unconditional.
|
||||
*/
|
||||
class Branch : public PCDependentDisassembly
|
||||
{
|
||||
protected:
|
||||
/// target address (signed) Displacement .
|
||||
int32_t disp;
|
||||
|
||||
/// Constructor.
|
||||
Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
|
||||
: PCDependentDisassembly(mnem, _machInst, __opClass),
|
||||
disp(OFFSET << 2)
|
||||
{
|
||||
//If Bit 17 is 1 then Sign Extend
|
||||
if ( (disp & 0x00020000) > 0 ) {
|
||||
disp |= 0xFFFE0000;
|
||||
}
|
||||
}
|
||||
|
||||
MipsISA::PCState branchTarget(const MipsISA::PCState &branchPC) const;
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for jumps (register-indirect control transfers). In
|
||||
* the Mips ISA, these are always unconditional.
|
||||
*/
|
||||
class Jump : public PCDependentDisassembly
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Displacement to target address (signed).
|
||||
int32_t disp;
|
||||
|
||||
uint32_t target;
|
||||
|
||||
public:
|
||||
/// Constructor
|
||||
Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
|
||||
: PCDependentDisassembly(mnem, _machInst, __opClass),
|
||||
disp(JMPTARG << 2)
|
||||
{
|
||||
}
|
||||
|
||||
MipsISA::PCState branchTarget(ThreadContext *tc) const;
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
MipsISA::PCState
|
||||
Branch::branchTarget(const MipsISA::PCState &branchPC) const
|
||||
{
|
||||
MipsISA::PCState target = branchPC;
|
||||
target.advance();
|
||||
target.npc(branchPC.pc() + sizeof(MachInst) + disp);
|
||||
target.nnpc(target.npc() + sizeof(MachInst));
|
||||
return target;
|
||||
}
|
||||
|
||||
MipsISA::PCState
|
||||
Jump::branchTarget(ThreadContext *tc) const
|
||||
{
|
||||
MipsISA::PCState target = tc->pcState();
|
||||
Addr pc = target.pc();
|
||||
target.advance();
|
||||
target.npc((pc & 0xF0000000) | disp);
|
||||
target.nnpc(target.npc() + sizeof(MachInst));
|
||||
return target;
|
||||
}
|
||||
|
||||
const std::string &
|
||||
PCDependentDisassembly::disassemble(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
if (!cachedDisassembly ||
|
||||
pc != cachedPC || symtab != cachedSymtab)
|
||||
{
|
||||
if (cachedDisassembly)
|
||||
delete cachedDisassembly;
|
||||
|
||||
cachedDisassembly =
|
||||
new std::string(generateDisassembly(pc, symtab));
|
||||
cachedPC = pc;
|
||||
cachedSymtab = symtab;
|
||||
}
|
||||
|
||||
return *cachedDisassembly;
|
||||
}
|
||||
|
||||
std::string
|
||||
Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
// There's only one register arg (RA), but it could be
|
||||
// either a source (the condition for conditional
|
||||
// branches) or a destination (the link reg for
|
||||
// unconditional branches)
|
||||
if (_numSrcRegs == 1) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
ss << ", ";
|
||||
} else if(_numSrcRegs == 2) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[1]);
|
||||
ss << ", ";
|
||||
}
|
||||
|
||||
Addr target = pc + 4 + disp;
|
||||
|
||||
std::string str;
|
||||
if (symtab && symtab->findSymbol(target, str))
|
||||
ss << str;
|
||||
else
|
||||
ccprintf(ss, "0x%x", target);
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
std::string
|
||||
Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
if ( strcmp(mnemonic,"jal") == 0 ) {
|
||||
Addr npc = pc + 4;
|
||||
ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
|
||||
} else if (_numSrcRegs == 0) {
|
||||
std::string str;
|
||||
if (symtab && symtab->findSymbol(disp, str))
|
||||
ss << str;
|
||||
else
|
||||
ccprintf(ss, "0x%x", disp);
|
||||
} else if (_numSrcRegs == 1) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
} else if(_numSrcRegs == 2) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[1]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
}};
|
||||
|
||||
def format Branch(code, *opt_flags) {{
|
||||
not_taken_code = 'NNPC = NNPC; NPC = NPC;'
|
||||
|
||||
#Build Instruction Flags
|
||||
#Use Link & Likely Flags to Add Link/Condition Code
|
||||
inst_flags = ('IsDirectControl', )
|
||||
for x in opt_flags:
|
||||
if x == 'Link':
|
||||
code += 'R31 = NNPC;\n'
|
||||
elif x == 'Likely':
|
||||
not_taken_code = 'NNPC = NPC; NPC = PC;'
|
||||
inst_flags += ('IsCondDelaySlot', )
|
||||
else:
|
||||
inst_flags += (x, )
|
||||
|
||||
#Take into account uncond. branch instruction
|
||||
if 'cond = 1' in code:
|
||||
inst_flags += ('IsUncondControl', )
|
||||
else:
|
||||
inst_flags += ('IsCondControl', )
|
||||
|
||||
#Condition code
|
||||
code = '''
|
||||
bool cond;
|
||||
%(code)s
|
||||
if (cond) {
|
||||
NNPC = NPC + disp;
|
||||
} else {
|
||||
%(not_taken_code)s
|
||||
}
|
||||
''' % { "code" : code, "not_taken_code" : not_taken_code }
|
||||
|
||||
iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format DspBranch(code, *opt_flags) {{
|
||||
not_taken_code = 'NNPC = NNPC; NPC = NPC;'
|
||||
|
||||
#Build Instruction Flags
|
||||
#Use Link & Likely Flags to Add Link/Condition Code
|
||||
inst_flags = ('IsDirectControl', )
|
||||
for x in opt_flags:
|
||||
if x == 'Link':
|
||||
code += 'R32 = NNPC;'
|
||||
elif x == 'Likely':
|
||||
not_taken_code = 'NNPC = NPC, NPC = PC;'
|
||||
inst_flags += ('IsCondDelaySlot', )
|
||||
else:
|
||||
inst_flags += (x, )
|
||||
|
||||
#Take into account uncond. branch instruction
|
||||
if 'cond = 1' in code:
|
||||
inst_flags += ('IsUncondControl', )
|
||||
else:
|
||||
inst_flags += ('IsCondControl', )
|
||||
|
||||
#Condition code
|
||||
code = '''
|
||||
bool cond;
|
||||
uint32_t dspctl = DSPControl;
|
||||
%(code)s
|
||||
if (cond) {
|
||||
NNPC = NPC + disp;
|
||||
} else {
|
||||
%(not_taken_code)s
|
||||
}
|
||||
''' % { "code" : code, "not_taken_code" : not_taken_code }
|
||||
|
||||
iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format Jump(code, *opt_flags) {{
|
||||
#Build Instruction Flags
|
||||
#Use Link Flag to Add Link Code
|
||||
inst_flags = ('IsIndirectControl', 'IsUncondControl')
|
||||
for x in opt_flags:
|
||||
if x == 'Link':
|
||||
code = '''
|
||||
R31 = NNPC;
|
||||
''' + code
|
||||
elif x == 'ClearHazards':
|
||||
code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
|
||||
else:
|
||||
inst_flags += (x, )
|
||||
|
||||
iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
|
||||
|
||||
|
||||
247
simulators/gem5/src/arch/mips/isa/formats/control.isa
Normal file
247
simulators/gem5/src/arch/mips/isa/formats/control.isa
Normal file
@ -0,0 +1,247 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
// Jaidev Patwardhan
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Coprocessor instructions
|
||||
//
|
||||
|
||||
//Outputs to decoder.hh
|
||||
output header {{
|
||||
|
||||
class CP0Control : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
class CP0TLB : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
|
||||
class CP1Control : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
}};
|
||||
|
||||
// Basic instruction class execute method template.
|
||||
def template CP0Execute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
if (isCoprocessorEnabled(xc, 0)) {
|
||||
%(code)s;
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
} else {
|
||||
fault = new CoprocessorUnusableFault(0);
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template CP1Execute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
if (isCoprocessorEnabled(xc, 1)) {
|
||||
%(code)s;
|
||||
} else {
|
||||
fault = new CoprocessorUnusableFault(1);
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
// Basic instruction class execute method template.
|
||||
def template ControlTLBExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
if (FullSystem) {
|
||||
if (isCoprocessor0Enabled(xc)) {
|
||||
if(isMMUTLB(xc)){
|
||||
%(code)s;
|
||||
} else {
|
||||
fault = new ReservedInstructionFault();
|
||||
}
|
||||
} else {
|
||||
fault = new CoprocessorUnusableFault(0);
|
||||
}
|
||||
} else { // Syscall Emulation Mode - No TLB Instructions
|
||||
fault = new ReservedInstructionFault();
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
//Outputs to decoder.cc
|
||||
output decoder {{
|
||||
std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
|
||||
return ss.str();
|
||||
}
|
||||
std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
|
||||
return ss.str();
|
||||
}
|
||||
std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
bool
|
||||
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
|
||||
{
|
||||
if (!FullSystem)
|
||||
return true;
|
||||
|
||||
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
|
||||
if (cop_num == 0) {
|
||||
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
|
||||
// In Stat, EXL, ERL or CU0 set, CP0 accessible
|
||||
// In Dbg, DM bit set, CP0 accessible
|
||||
// In Stat, KSU = 0, kernel mode is base mode
|
||||
return (Stat & 0x10000006) ||
|
||||
(Dbg & 0x40000000) ||
|
||||
!(Stat & 0x00000018);
|
||||
} else if (cop_num < 4) {
|
||||
return Stat & (0x10000000 << cop_num); // CU is reset
|
||||
} else {
|
||||
panic("Invalid Coprocessor Number Specified");
|
||||
}
|
||||
}
|
||||
|
||||
bool inline
|
||||
isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
if (FullSystem) {
|
||||
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
|
||||
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
|
||||
// In Stat, EXL, ERL or CU0 set, CP0 accessible
|
||||
// In Dbg, DM bit set, CP0 accessible
|
||||
// In Stat KSU = 0, kernel mode is base mode
|
||||
return (Stat & 0x10000006) || (Dbg & 0x40000000) ||
|
||||
!(Stat & 0x00000018);
|
||||
} else {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
isMMUTLB(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
|
||||
return FullSystem && (Config & 0x380) == 0x80;
|
||||
}
|
||||
}};
|
||||
|
||||
def format CP0Control(code, *flags) {{
|
||||
flags += ('IsNonSpeculative', )
|
||||
iop = InstObjParams(name, Name, 'CP0Control', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = CP0Execute.subst(iop)
|
||||
}};
|
||||
def format CP0TLB(code, *flags) {{
|
||||
flags += ('IsNonSpeculative', )
|
||||
iop = InstObjParams(name, Name, 'CP0Control', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = ControlTLBExecute.subst(iop)
|
||||
}};
|
||||
def format CP1Control(code, *flags) {{
|
||||
flags += ('IsNonSpeculative', )
|
||||
iop = InstObjParams(name, Name, 'CP1Control', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = CP1Execute.subst(iop)
|
||||
}};
|
||||
|
||||
|
||||
213
simulators/gem5/src/arch/mips/isa/formats/dsp.isa
Executable file
213
simulators/gem5/src/arch/mips/isa/formats/dsp.isa
Executable file
@ -0,0 +1,213 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
// Brett Miller
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// DSP integer operate instructions
|
||||
//
|
||||
output header {{
|
||||
#include <iostream>
|
||||
using namespace std;
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class DspIntOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
};
|
||||
|
||||
class DspHiLoOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
};
|
||||
}};
|
||||
|
||||
// Dsp instruction class execute method template.
|
||||
def template DspExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
|
||||
if (isDspPresent(xc))
|
||||
{
|
||||
if (isDspEnabled(xc))
|
||||
{
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
}
|
||||
else
|
||||
{
|
||||
fault = new DspStateDisabledFault();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
fault = new ReservedInstructionFault();
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// DspHiLo instruction class execute method template.
|
||||
def template DspHiLoExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
|
||||
if (isDspPresent(xc))
|
||||
{
|
||||
if (isDspEnabled(xc))
|
||||
{
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
}
|
||||
else
|
||||
{
|
||||
fault = new DspStateDisabledFault();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
fault = new ReservedInstructionFault();
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
//If there are 2 Destination Registers then
|
||||
//concatenate the values for the traceData
|
||||
if(traceData && _numDestRegs == 2) {
|
||||
// FIXME - set the trace value correctly here
|
||||
//uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL;
|
||||
//traceData->setData(hilo_final_val);
|
||||
}
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
//Outputs to decoder.cc
|
||||
output decoder {{
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
bool
|
||||
isDspEnabled(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
bool
|
||||
isDspPresent(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
|
||||
}
|
||||
}};
|
||||
|
||||
// add code to fetch the DSPControl register
|
||||
// and write it back after execution, giving
|
||||
// the instruction the opportunity to modify
|
||||
// it if necessary
|
||||
def format DspIntOp(code, *opt_flags) {{
|
||||
|
||||
decl_code = 'uint32_t dspctl;\n'
|
||||
decl_code += 'dspctl = DSPControl;\n'
|
||||
|
||||
write_code = 'DSPControl = dspctl;\n'
|
||||
|
||||
code = decl_code + code + write_code
|
||||
|
||||
opt_flags += ('IsDspOp',)
|
||||
|
||||
iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = DspExecute.subst(iop)
|
||||
}};
|
||||
|
||||
// add code to fetch the DSPControl register
|
||||
// and write it back after execution, giving
|
||||
// the instruction the opportunity to modify
|
||||
// it if necessary; also, fetch the appropriate
|
||||
// HI/LO register pair, based on the AC
|
||||
// instruction field.
|
||||
|
||||
def format DspHiLoOp(code, *opt_flags) {{
|
||||
|
||||
decl_code = 'int64_t dspac;\n'
|
||||
decl_code += 'uint32_t dspctl;\n'
|
||||
|
||||
fetch_code = 'dspctl = DSPControl;\n'
|
||||
fetch_code += 'dspac = HI_RD_SEL;\n'
|
||||
fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n'
|
||||
|
||||
write_code = 'DSPControl = dspctl;\n'
|
||||
write_code += 'HI_RD_SEL = dspac<63:32>;\n'
|
||||
write_code += 'LO_RD_SEL = dspac<31:0>;\n'
|
||||
|
||||
code = decl_code + fetch_code + code + write_code
|
||||
|
||||
opt_flags += ('IsDspOp',)
|
||||
|
||||
iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = DspHiLoExecute.subst(iop)
|
||||
|
||||
}};
|
||||
|
||||
|
||||
|
||||
69
simulators/gem5/src/arch/mips/isa/formats/formats.isa
Normal file
69
simulators/gem5/src/arch/mips/isa/formats/formats.isa
Normal file
@ -0,0 +1,69 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
//Templates from this format are used later
|
||||
//Include the basic format
|
||||
##include "basic.isa"
|
||||
|
||||
//Include the basic format
|
||||
##include "noop.isa"
|
||||
|
||||
//Include utility functions
|
||||
##include "util.isa"
|
||||
|
||||
//Include the control/cp0/cp1 formats
|
||||
##include "control.isa"
|
||||
|
||||
//Include the integer formats
|
||||
##include "int.isa"
|
||||
|
||||
//Include the DSP integer format
|
||||
##include "dsp.isa"
|
||||
|
||||
//Include the floatOp format
|
||||
##include "fp.isa"
|
||||
|
||||
//Include the mem format
|
||||
##include "mem.isa"
|
||||
|
||||
//Include the mem format
|
||||
##include "mt.isa"
|
||||
|
||||
//Include the trap format
|
||||
##include "trap.isa"
|
||||
|
||||
//Include the branch format
|
||||
##include "branch.isa"
|
||||
|
||||
//Include the noop format
|
||||
##include "unimp.isa"
|
||||
|
||||
//Include the noop format
|
||||
##include "unknown.isa"
|
||||
370
simulators/gem5/src/arch/mips/isa/formats/fp.isa
Normal file
370
simulators/gem5/src/arch/mips/isa/formats/fp.isa
Normal file
@ -0,0 +1,370 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Floating Point operate instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for FP operations.
|
||||
*/
|
||||
class FPOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
//std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
//needs function to check for fpEnable or not
|
||||
};
|
||||
|
||||
class FPCompareOp : public FPOp
|
||||
{
|
||||
protected:
|
||||
FPCompareOp(const char *mnem, MachInst _machInst, OpClass __opClass) : FPOp(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string FPCompareOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
ccprintf(ss,"%d",CC);
|
||||
|
||||
if(_numSrcRegs > 0) {
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
if(_numSrcRegs > 1) {
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[1]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
|
||||
{
|
||||
//@TODO: Implement correct CP0 checks to see if the CP1
|
||||
// unit is enable or not
|
||||
if (!isCoprocessorEnabled(xc, 1))
|
||||
return new CoprocessorUnusableFault(1);
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
//If any operand is Nan return the appropriate QNaN
|
||||
template <class T>
|
||||
bool
|
||||
fpNanOperands(FPOp *inst, %(CPU_exec_context)s *xc, const T &src_type,
|
||||
Trace::InstRecord *traceData)
|
||||
{
|
||||
uint64_t mips_nan = 0;
|
||||
assert(sizeof(T) == 4);
|
||||
|
||||
for (int i = 0; i < inst->numSrcRegs(); i++) {
|
||||
uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0);
|
||||
|
||||
if (isNan(&src_bits, 32) ) {
|
||||
mips_nan = MIPS32_QNAN;
|
||||
xc->setFloatRegOperandBits(inst, 0, mips_nan);
|
||||
if (traceData) { traceData->setData(mips_nan); }
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
template <class T>
|
||||
bool
|
||||
fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
|
||||
Trace::InstRecord *traceData)
|
||||
{
|
||||
uint64_t mips_nan = 0;
|
||||
T src_op = dest_val;
|
||||
assert(sizeof(T) == 4);
|
||||
|
||||
if (isNan(&src_op, 32)) {
|
||||
mips_nan = MIPS32_QNAN;
|
||||
|
||||
//Set value to QNAN
|
||||
cpu->setFloatRegOperandBits(inst, 0, mips_nan);
|
||||
|
||||
//Read FCSR from FloatRegFile
|
||||
uint32_t fcsr_bits =
|
||||
cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
|
||||
|
||||
uint32_t new_fcsr = genInvalidVector(fcsr_bits);
|
||||
|
||||
//Write FCSR from FloatRegFile
|
||||
cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
|
||||
|
||||
if (traceData) { traceData->setData(mips_nan); }
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void
|
||||
fpResetCauseBits(%(CPU_exec_context)s *cpu)
|
||||
{
|
||||
//Read FCSR from FloatRegFile
|
||||
uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
|
||||
|
||||
// TODO: Use utility function here
|
||||
fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
|
||||
|
||||
//Write FCSR from FloatRegFile
|
||||
cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
|
||||
}
|
||||
}};
|
||||
|
||||
def template FloatingPointExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
|
||||
|
||||
//When is the right time to reset cause bits?
|
||||
//start of every instruction or every cycle?
|
||||
if (FullSystem)
|
||||
fpResetCauseBits(xc);
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
//Check if any FP operand is a NaN value
|
||||
if (!fpNanOperands((FPOp*)this, xc, Fd, traceData)) {
|
||||
%(code)s;
|
||||
|
||||
//Change this code for Full-System/Sycall Emulation
|
||||
//separation
|
||||
//----
|
||||
//Should Full System-Mode throw a fault here?
|
||||
//----
|
||||
//Check for IEEE 754 FP Exceptions
|
||||
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
|
||||
bool invalid_op = false;
|
||||
if (FullSystem) {
|
||||
invalid_op =
|
||||
fpInvalidOp((FPOp*)this, xc, Fd, traceData);
|
||||
}
|
||||
if (!invalid_op && fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for float point operate instructions:
|
||||
def format FloatOp(code, *flags) {{
|
||||
iop = InstObjParams(name, Name, 'FPOp', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = FloatingPointExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format FloatCompareOp(cond_code, *flags) {{
|
||||
import sys
|
||||
|
||||
code = 'bool cond;\n'
|
||||
if '_sf' in cond_code or 'SinglePrecision' in flags:
|
||||
if 'QnanException' in flags:
|
||||
code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n'
|
||||
code += '\tFCSR = genInvalidVector(FCSR);\n'
|
||||
code += '\treturn NoFault;'
|
||||
code += '}\n else '
|
||||
code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n'
|
||||
elif '_df' in cond_code or 'DoublePrecision' in flags:
|
||||
if 'QnanException' in flags:
|
||||
code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n'
|
||||
code += '\tFCSR = genInvalidVector(FCSR);\n'
|
||||
code += '\treturn NoFault;'
|
||||
code += '}\n else '
|
||||
code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n'
|
||||
else:
|
||||
sys.exit('Decoder Failed: Can\'t Determine Operand Type\n')
|
||||
|
||||
if 'UnorderedTrue' in flags:
|
||||
code += 'cond = 1;\n'
|
||||
elif 'UnorderedFalse' in flags:
|
||||
code += 'cond = 0;\n'
|
||||
else:
|
||||
sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
|
||||
|
||||
code += '} else {\n'
|
||||
code += cond_code + '}'
|
||||
code += 'FCSR = genCCVector(FCSR, CC, cond);\n'
|
||||
|
||||
iop = InstObjParams(name, Name, 'FPCompareOp', code)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format FloatConvertOp(code, *flags) {{
|
||||
import sys
|
||||
|
||||
#Determine Source Type
|
||||
convert = 'fpConvert('
|
||||
if '_sf' in code:
|
||||
code = 'float ' + code + '\n'
|
||||
convert += 'SINGLE_TO_'
|
||||
elif '_df' in code:
|
||||
code = 'double ' + code + '\n'
|
||||
convert += 'DOUBLE_TO_'
|
||||
elif '_uw' in code:
|
||||
code = 'uint32_t ' + code + '\n'
|
||||
convert += 'WORD_TO_'
|
||||
elif '_ud' in code:
|
||||
code = 'uint64_t ' + code + '\n'
|
||||
convert += 'LONG_TO_'
|
||||
else:
|
||||
sys.exit("Error Determining Source Type for Conversion")
|
||||
|
||||
#Determine Destination Type
|
||||
if 'ToSingle' in flags:
|
||||
code += 'Fd_uw = ' + convert + 'SINGLE, '
|
||||
elif 'ToDouble' in flags:
|
||||
code += 'Fd_ud = ' + convert + 'DOUBLE, '
|
||||
elif 'ToWord' in flags:
|
||||
code += 'Fd_uw = ' + convert + 'WORD, '
|
||||
elif 'ToLong' in flags:
|
||||
code += 'Fd_ud = ' + convert + 'LONG, '
|
||||
else:
|
||||
sys.exit("Error Determining Destination Type for Conversion")
|
||||
|
||||
#Figure out how to round value
|
||||
if 'Ceil' in flags:
|
||||
code += 'ceil(val)); '
|
||||
elif 'Floor' in flags:
|
||||
code += 'floor(val)); '
|
||||
elif 'Round' in flags:
|
||||
code += 'roundFP(val, 0)); '
|
||||
elif 'Trunc' in flags:
|
||||
code += 'truncFP(val));'
|
||||
else:
|
||||
code += 'val); '
|
||||
|
||||
iop = InstObjParams(name, Name, 'FPOp', code)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format FloatAccOp(code, *flags) {{
|
||||
iop = InstObjParams(name, Name, 'FPOp', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
// Primary format for float64 operate instructions:
|
||||
def format Float64Op(code, *flags) {{
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{
|
||||
import sys
|
||||
|
||||
code = 'bool cond1, cond2;\n'
|
||||
code += 'bool code_block1, code_block2;\n'
|
||||
code += 'code_block1 = code_block2 = true;\n'
|
||||
|
||||
if 'QnanException' in flags:
|
||||
code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n'
|
||||
code += '\tFCSR = genInvalidVector(FCSR);\n'
|
||||
code += 'code_block1 = false;'
|
||||
code += '}\n'
|
||||
code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n'
|
||||
code += '\tFCSR = genInvalidVector(FCSR);\n'
|
||||
code += 'code_block2 = false;'
|
||||
code += '}\n'
|
||||
|
||||
code += 'if (code_block1) {'
|
||||
code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n'
|
||||
if 'UnorderedTrue' in flags:
|
||||
code += 'cond1 = 1;\n'
|
||||
elif 'UnorderedFalse' in flags:
|
||||
code += 'cond1 = 0;\n'
|
||||
else:
|
||||
sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
|
||||
code += '} else {\n'
|
||||
code += cond_code1
|
||||
code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n'
|
||||
|
||||
code += 'if (code_block2) {'
|
||||
code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n'
|
||||
if 'UnorderedTrue' in flags:
|
||||
code += 'cond2 = 1;\n'
|
||||
elif 'UnorderedFalse' in flags:
|
||||
code += 'cond2 = 0;\n'
|
||||
else:
|
||||
sys.exit('Decoder Failed: Float Compare Instruction Needs A Unordered Flag\n')
|
||||
code += '} else {\n'
|
||||
code += cond_code2
|
||||
code += 'FCSR = genCCVector(FCSR, CC, cond2);}\n}'
|
||||
|
||||
iop = InstObjParams(name, Name, 'FPCompareOp', code)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
381
simulators/gem5/src/arch/mips/isa/formats/int.isa
Normal file
381
simulators/gem5/src/arch/mips/isa/formats/int.isa
Normal file
@ -0,0 +1,381 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Integer operate instructions
|
||||
//
|
||||
output header {{
|
||||
#include <iostream>
|
||||
using namespace std;
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class IntOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
|
||||
class HiLoOp: public IntOp
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
IntOp(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
class HiLoRsSelOp: public HiLoOp
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
HiLoOp(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
class HiLoRdSelOp: public HiLoOp
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
HiLoOp(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
class HiLoRdSelValOp: public HiLoOp
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
HiLoOp(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
class IntImmOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
int16_t imm;
|
||||
int32_t sextImm;
|
||||
uint32_t zextImm;
|
||||
|
||||
/// Constructor
|
||||
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
|
||||
sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
|
||||
{
|
||||
//If Bit 15 is 1 then Sign Extend
|
||||
int32_t temp = sextImm & 0x00008000;
|
||||
if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
|
||||
sextImm |= 0xFFFF0000;
|
||||
}
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
|
||||
};
|
||||
|
||||
}};
|
||||
|
||||
// HiLo instruction class execute method template.
|
||||
def template HiLoExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// HiLoRsSel instruction class execute method template.
|
||||
def template HiLoRsSelExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
|
||||
if( ACSRC > 0 && !isDspEnabled(xc) )
|
||||
{
|
||||
fault = new DspStateDisabledFault();
|
||||
}
|
||||
else
|
||||
{
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// HiLoRdSel instruction class execute method template.
|
||||
def template HiLoRdSelExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(op_decl)s;
|
||||
|
||||
if( ACDST > 0 && !isDspEnabled(xc) )
|
||||
{
|
||||
fault = new DspStateDisabledFault();
|
||||
}
|
||||
else
|
||||
{
|
||||
%(op_rd)s;
|
||||
%(code)s;
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
//Outputs to decoder.cc
|
||||
output decoder {{
|
||||
std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
// just print the first dest... if there's a second one,
|
||||
// it's generally implicit
|
||||
if (_numDestRegs > 0) {
|
||||
printReg(ss, _destRegIdx[0]);
|
||||
ss << ", ";
|
||||
}
|
||||
|
||||
// just print the first two source regs... if there's
|
||||
// a third one, it's a read-modify-write dest (Rc),
|
||||
// e.g. for CMOVxx
|
||||
if (_numSrcRegs > 0) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
if (_numSrcRegs > 1) {
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[1]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
//Destination Registers are implicit for HI/LO ops
|
||||
if (_numSrcRegs > 0) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
if (_numSrcRegs > 1) {
|
||||
ss << ", ";
|
||||
printReg(ss, _srcRegIdx[1]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
|
||||
printReg(ss, _destRegIdx[0]);
|
||||
} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
|
||||
printReg(ss, _destRegIdx[0]);
|
||||
} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
|
||||
printReg(ss, _destRegIdx[0]);
|
||||
} else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
ccprintf(ss, "%-10s ", mnemonic);
|
||||
|
||||
if (_numDestRegs > 0) {
|
||||
printReg(ss, _destRegIdx[0]);
|
||||
}
|
||||
|
||||
ss << ", ";
|
||||
|
||||
if (_numSrcRegs > 0) {
|
||||
printReg(ss, _srcRegIdx[0]);
|
||||
ss << ", ";
|
||||
}
|
||||
|
||||
if(strcmp(mnemonic,"lui") == 0)
|
||||
ccprintf(ss, "0x%x ", sextImm);
|
||||
else
|
||||
ss << (int) sextImm;
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
||||
}};
|
||||
|
||||
def format IntOp(code, *opt_flags) {{
|
||||
iop = InstObjParams(name, Name, 'IntOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = RegNopCheckDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format IntImmOp(code, *opt_flags) {{
|
||||
iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = ImmNopCheckDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format HiLoRsSelOp(code, *opt_flags) {{
|
||||
iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = HiLoRsSelExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format HiLoRdSelOp(code, *opt_flags) {{
|
||||
iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = HiLoRdSelExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format HiLoRdSelValOp(code, *opt_flags) {{
|
||||
|
||||
if '_sd' in code:
|
||||
code = 'int64_t ' + code
|
||||
elif '_ud' in code:
|
||||
code = 'uint64_t ' + code
|
||||
|
||||
code += 'HI_RD_SEL = val<63:32>;\n'
|
||||
code += 'LO_RD_SEL = val<31:0>;\n'
|
||||
|
||||
iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = HiLoRdSelExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format HiLoOp(code, *opt_flags) {{
|
||||
iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = HiLoExecute.subst(iop)
|
||||
}};
|
||||
596
simulators/gem5/src/arch/mips/isa/formats/mem.isa
Normal file
596
simulators/gem5/src/arch/mips/isa/formats/mem.isa
Normal file
@ -0,0 +1,596 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Steve Reinhardt
|
||||
// Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Memory-format instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for general Mips memory-format instructions.
|
||||
*/
|
||||
class Memory : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
/// Memory request flags. See mem_req_base.hh.
|
||||
Request::Flags memAccessFlags;
|
||||
|
||||
/// Displacement for EA calculation (signed).
|
||||
int32_t disp;
|
||||
|
||||
/// Constructor
|
||||
Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
|
||||
: MipsStaticInst(mnem, _machInst, __opClass),
|
||||
disp(sext<16>(OFFSET))
|
||||
{
|
||||
}
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for a few miscellaneous memory-format insts
|
||||
* that don't interpret the disp field
|
||||
*/
|
||||
class MemoryNoDisp : public Memory
|
||||
{
|
||||
protected:
|
||||
/// Constructor
|
||||
MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
|
||||
: Memory(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
|
||||
output decoder {{
|
||||
std::string
|
||||
Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
|
||||
flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
|
||||
}
|
||||
|
||||
std::string
|
||||
MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
|
||||
flags[IsFloating] ? 'f' : 'r',
|
||||
flags[IsFloating] ? FD : RD,
|
||||
RS, RT);
|
||||
}
|
||||
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
/** return data in cases where there the size of data is only
|
||||
known in the packet
|
||||
*/
|
||||
uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) {
|
||||
switch (packet->getSize())
|
||||
{
|
||||
case 1:
|
||||
return packet->get<uint8_t>();
|
||||
|
||||
case 2:
|
||||
return packet->get<uint16_t>();
|
||||
|
||||
case 4:
|
||||
return packet->get<uint32_t>();
|
||||
|
||||
case 8:
|
||||
return packet->get<uint64_t>();
|
||||
|
||||
default:
|
||||
std::cerr << "bad store data size = " << packet->getSize() << std::endl;
|
||||
|
||||
assert(0);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}};
|
||||
|
||||
def template LoadStoreDeclare {{
|
||||
/**
|
||||
* Static instruction class for "%(mnemonic)s".
|
||||
*/
|
||||
class %(class_name)s : public %(base_class)s
|
||||
{
|
||||
public:
|
||||
|
||||
/// Constructor.
|
||||
%(class_name)s(ExtMachInst machInst);
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
%(EACompDeclare)s
|
||||
|
||||
%(InitiateAccDeclare)s
|
||||
|
||||
%(CompleteAccDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
def template EACompDeclare {{
|
||||
Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
|
||||
}};
|
||||
|
||||
def template InitiateAccDeclare {{
|
||||
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
|
||||
}};
|
||||
|
||||
|
||||
def template CompleteAccDeclare {{
|
||||
Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
|
||||
}};
|
||||
|
||||
def template LoadStoreConstructor {{
|
||||
inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
|
||||
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
|
||||
{
|
||||
%(constructor)s;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
def template EACompExecute {{
|
||||
Fault
|
||||
%(class_name)s::eaComp(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
if (this->isFloating()) {
|
||||
%(fp_enable_check)s;
|
||||
|
||||
if(fault != NoFault)
|
||||
return fault;
|
||||
}
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
// NOTE: Trace Data is written using execute or completeAcc templates
|
||||
if (fault == NoFault) {
|
||||
xc->setEA(EA);
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template LoadExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
if (this->isFloating()) {
|
||||
%(fp_enable_check)s;
|
||||
|
||||
if(fault != NoFault)
|
||||
return fault;
|
||||
}
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
def template LoadInitiateAcc {{
|
||||
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
if (this->isFloating()) {
|
||||
%(fp_enable_check)s;
|
||||
|
||||
if(fault != NoFault)
|
||||
return fault;
|
||||
}
|
||||
|
||||
%(op_src_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template LoadCompleteAcc {{
|
||||
Fault %(class_name)s::completeAcc(Packet *pkt,
|
||||
%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
if (this->isFloating()) {
|
||||
%(fp_enable_check)s;
|
||||
|
||||
if(fault != NoFault)
|
||||
return fault;
|
||||
}
|
||||
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
getMem(pkt, Mem, traceData);
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template StoreExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
|
||||
NULL);
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
def template StoreFPExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
if(fault != NoFault)
|
||||
return fault;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
|
||||
NULL);
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template StoreCondExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
uint64_t write_result = 0;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
|
||||
&write_result);
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template StoreInitiateAcc {{
|
||||
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
|
||||
NULL);
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
def template StoreCompleteAcc {{
|
||||
Fault %(class_name)s::completeAcc(Packet *pkt,
|
||||
%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
return NoFault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template StoreCondCompleteAcc {{
|
||||
Fault %(class_name)s::completeAcc(Packet *pkt,
|
||||
%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_dest_decl)s;
|
||||
|
||||
uint64_t write_result = pkt->req->getExtraData();
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template MiscExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA M5_VAR_USED = 0;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template MiscInitiateAcc {{
|
||||
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
panic("Misc instruction does not support split access method!");
|
||||
return NoFault;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
def template MiscCompleteAcc {{
|
||||
Fault %(class_name)s::completeAcc(Packet *pkt,
|
||||
%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
panic("Misc instruction does not support split access method!");
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
}};
|
||||
|
||||
def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
decode_template = ImmNopCheckDecode,
|
||||
exec_template_base = 'Load')
|
||||
}};
|
||||
|
||||
|
||||
def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
exec_template_base = 'Store')
|
||||
}};
|
||||
|
||||
def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
inst_flags += ['IsIndexed']
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
decode_template = ImmNopCheckDecode,
|
||||
exec_template_base = 'Load')
|
||||
}};
|
||||
|
||||
def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
inst_flags += ['IsIndexed']
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
exec_template_base = 'Store')
|
||||
}};
|
||||
|
||||
def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
inst_flags += ['IsIndexed', 'IsFloating']
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
decode_template = ImmNopCheckDecode,
|
||||
exec_template_base = 'Load')
|
||||
}};
|
||||
|
||||
def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
inst_flags += ['IsIndexed', 'IsFloating']
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
exec_template_base = 'Store')
|
||||
}};
|
||||
|
||||
|
||||
def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
decl_code = '''
|
||||
uint32_t mem_word = Mem_uw;
|
||||
uint32_t unalign_addr = Rs + disp;
|
||||
uint32_t byte_offset = unalign_addr & 3;
|
||||
if (GuestByteOrder == BigEndianByteOrder)
|
||||
byte_offset ^= 3;
|
||||
'''
|
||||
|
||||
memacc_code = decl_code + memacc_code
|
||||
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
decode_template = ImmNopCheckDecode,
|
||||
exec_template_base = 'Load')
|
||||
}};
|
||||
|
||||
def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
decl_code = '''
|
||||
uint32_t mem_word = 0;
|
||||
uint32_t unaligned_addr = Rs + disp;
|
||||
uint32_t byte_offset = unaligned_addr & 3;
|
||||
if (GuestByteOrder == BigEndianByteOrder)
|
||||
byte_offset ^= 3;
|
||||
fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
|
||||
'''
|
||||
memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
|
||||
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
exec_template_base = 'Store')
|
||||
}};
|
||||
|
||||
def format Prefetch(ea_code = {{ EA = Rs + disp; }},
|
||||
mem_flags = [], pf_flags = [], inst_flags = []) {{
|
||||
pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
|
||||
pf_inst_flags = inst_flags
|
||||
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code,
|
||||
'warn_once("Prefetching not implemented for MIPS\\n");',
|
||||
pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
|
||||
|
||||
}};
|
||||
|
||||
def format StoreCond(memacc_code, postacc_code,
|
||||
ea_code = {{ EA = Rs + disp; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
postacc_code, exec_template_base = 'StoreCond')
|
||||
}};
|
||||
216
simulators/gem5/src/arch/mips/isa/formats/mt.isa
Normal file
216
simulators/gem5/src/arch/mips/isa/formats/mt.isa
Normal file
@ -0,0 +1,216 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// MT instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for MIPS MT ASE operations.
|
||||
*/
|
||||
class MTOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
bool user_mode;
|
||||
};
|
||||
|
||||
class MTUserModeOp : public MTOp
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MTOp(mnem, _machInst, __opClass)
|
||||
{
|
||||
user_mode = true;
|
||||
}
|
||||
|
||||
//std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
std::stringstream ss;
|
||||
|
||||
if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) {
|
||||
ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
|
||||
} else if (strcmp(mnemonic,"mftgpr") == 0) {
|
||||
ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
|
||||
} else {
|
||||
ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
|
||||
}
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
void getThrRegExValues(%(CPU_exec_context)s *xc,
|
||||
VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
|
||||
TCBindReg &tc_bind, VPEControlReg &vpe_control,
|
||||
MVPConf0Reg &mvp_conf0)
|
||||
{
|
||||
vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
|
||||
tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
|
||||
tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
|
||||
vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
|
||||
mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
|
||||
}
|
||||
|
||||
void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3)
|
||||
{
|
||||
config3 = xc->readMiscReg(MISCREG_CONFIG3);
|
||||
}
|
||||
}};
|
||||
|
||||
def template ThreadRegisterExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
int64_t data M5_VAR_USED;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
VPEConf0Reg vpeConf0;
|
||||
TCBindReg tcBindMT;
|
||||
TCBindReg tcBind;
|
||||
VPEControlReg vpeControl;
|
||||
MVPConf0Reg mvpConf0;
|
||||
|
||||
getThrRegExValues(xc, vpeConf0, tcBindMT,
|
||||
tcBind, vpeControl, mvpConf0);
|
||||
|
||||
if (isCoprocessorEnabled(xc, 0)) {
|
||||
if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) {
|
||||
data = -1;
|
||||
} else if (vpeControl.targTC > mvpConf0.ptc) {
|
||||
data = -1;
|
||||
} else {
|
||||
%(code)s;
|
||||
}
|
||||
} else {
|
||||
fault = new CoprocessorUnusableFault(0);
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
def template MTExecute{{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
|
||||
Config3Reg config3;
|
||||
|
||||
getMTExValues(xc, config3);
|
||||
|
||||
if (isCoprocessorEnabled(xc, 0)) {
|
||||
if (config3.mt == 1) {
|
||||
%(code)s;
|
||||
} else {
|
||||
fault = new ReservedInstructionFault();
|
||||
}
|
||||
} else {
|
||||
fault = new CoprocessorUnusableFault(0);
|
||||
}
|
||||
|
||||
if(fault == NoFault)
|
||||
{
|
||||
%(op_wb)s;
|
||||
}
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format MT_Control(code, *opt_flags) {{
|
||||
inst_flags = ('IsNonSpeculative', )
|
||||
op_type = 'MTOp'
|
||||
|
||||
for x in opt_flags:
|
||||
if x == 'UserMode':
|
||||
op_type = 'MTUserModeOp'
|
||||
else:
|
||||
inst_flags += (x, )
|
||||
|
||||
iop = InstObjParams(name, Name, op_type, code, inst_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = MTExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format MT_MFTR(code, *flags) {{
|
||||
flags += ('IsNonSpeculative', )
|
||||
# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
|
||||
|
||||
code += '''
|
||||
if (MT_H)
|
||||
data = bits(data, 63, 32);
|
||||
Rd = data;
|
||||
'''
|
||||
|
||||
iop = InstObjParams(name, Name, 'MTOp', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = ThreadRegisterExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format MT_MTTR(code, *flags) {{
|
||||
flags += ('IsNonSpeculative', )
|
||||
# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
|
||||
iop = InstObjParams(name, Name, 'MTOp', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = ThreadRegisterExecute.subst(iop)
|
||||
}};
|
||||
139
simulators/gem5/src/arch/mips/isa/formats/noop.isa
Normal file
139
simulators/gem5/src/arch/mips/isa/formats/noop.isa
Normal file
@ -0,0 +1,139 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Nop
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Static instruction class for no-ops. This is a leaf class.
|
||||
*/
|
||||
class Nop : public MipsStaticInst
|
||||
{
|
||||
/// Disassembly of original instruction.
|
||||
const std::string originalDisassembly;
|
||||
|
||||
public:
|
||||
/// Constructor
|
||||
Nop(const std::string _originalDisassembly, MachInst _machInst)
|
||||
: MipsStaticInst("nop", _machInst, No_OpClass),
|
||||
originalDisassembly(_originalDisassembly)
|
||||
{
|
||||
flags[IsNop] = true;
|
||||
}
|
||||
|
||||
~Nop() { }
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Nop::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s %s", "nop", originalDisassembly);
|
||||
}
|
||||
|
||||
/// Helper function for decoding nops. Substitute Nop object
|
||||
/// for original inst passed in as arg (and delete latter).
|
||||
inline
|
||||
MipsStaticInst *
|
||||
makeNop(MipsStaticInst *inst)
|
||||
{
|
||||
std::string nop_str = "(" + inst->disassemble(0) + ")";
|
||||
MipsStaticInst *nop = new Nop(nop_str, inst->machInst);
|
||||
delete inst;
|
||||
return nop;
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
Fault
|
||||
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
|
||||
{
|
||||
return NoFault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Int & FP operate instructions use RD as dest, so check for
|
||||
// RD == 0 to detect nops
|
||||
def template RegNopCheckDecode {{
|
||||
{
|
||||
MipsStaticInst *i = new %(class_name)s(machInst);
|
||||
//if (RD == 0) {
|
||||
//i = makeNop(i);
|
||||
//}
|
||||
return i;
|
||||
}
|
||||
}};
|
||||
|
||||
def template OperateNopCheckDecode {{
|
||||
{
|
||||
MipsStaticInst *i = new %(class_name)s(machInst);
|
||||
//if (RD == 0) {
|
||||
// i = makeNop(i);
|
||||
//}
|
||||
return i;
|
||||
}
|
||||
}};
|
||||
|
||||
// IntImm & Memory instructions use Rt as dest, so check for
|
||||
// Rt == 0 to detect nops
|
||||
def template ImmNopCheckDecode {{
|
||||
{
|
||||
MipsStaticInst *i = new %(class_name)s(machInst);
|
||||
//if (RT == 0) {
|
||||
// i = makeNop(i);
|
||||
// }
|
||||
return i;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
// Like BasicOperate format, but generates NOP if RC/FC == 31
|
||||
def format BasicOperateWithNopCheck(code, *opt_args) {{
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', code,
|
||||
opt_args)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = OperateNopCheckDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format Nop() {{
|
||||
decode_block = 'return new Nop(\"\",machInst);\n'
|
||||
}};
|
||||
|
||||
80
simulators/gem5/src/arch/mips/isa/formats/tlbop.isa
Normal file
80
simulators/gem5/src/arch/mips/isa/formats/tlbop.isa
Normal file
@ -0,0 +1,80 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// TlbOp instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class TlbOp : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
TlbOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string TlbOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of integer instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template TlbOpExecute {{
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//Write the resulting state to the execution context
|
||||
%(op_wb)s;
|
||||
|
||||
//Call into the trap handler with the appropriate fault
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
|
||||
// Primary format for integer operate instructions:
|
||||
def format TlbOp(code, *opt_flags) {{
|
||||
orig_code = code
|
||||
cblk = code
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
exec_output = TlbOpExecute.subst(iop)
|
||||
}};
|
||||
115
simulators/gem5/src/arch/mips/isa/formats/trap.isa
Normal file
115
simulators/gem5/src/arch/mips/isa/formats/trap.isa
Normal file
@ -0,0 +1,115 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
// Jaidev Patwardhan
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Trap instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Base class for integer operations.
|
||||
*/
|
||||
class Trap : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
/// Constructor
|
||||
Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
class TrapImm : public MipsStaticInst
|
||||
{
|
||||
protected:
|
||||
|
||||
int16_t imm;
|
||||
|
||||
/// Constructor
|
||||
TrapImm(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
|
||||
{
|
||||
}
|
||||
|
||||
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
|
||||
|
||||
};
|
||||
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of trap instruction\n";
|
||||
}
|
||||
std::string TrapImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return "Disassembly of trap instruction\n";
|
||||
}
|
||||
}};
|
||||
|
||||
def template TrapExecute {{
|
||||
//Edit This Template When Traps Are Implemented
|
||||
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
|
||||
{
|
||||
//Write the resulting state to the execution context
|
||||
%(op_wb)s;
|
||||
|
||||
//Call into the trap handler with the appropriate fault
|
||||
return No_Fault;
|
||||
}
|
||||
}};
|
||||
def format Trap(code, *flags) {{
|
||||
|
||||
code ='bool cond;\n' + code
|
||||
code += 'if (cond) {\n'
|
||||
code += 'fault = new TrapFault();\n};'
|
||||
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
def format TrapImm(code, *flags) {{
|
||||
|
||||
code ='bool cond;\n' + code
|
||||
code += 'if (cond) {\n'
|
||||
code += 'fault = new TrapFault();\n};'
|
||||
iop = InstObjParams(name, Name, 'MipsStaticInst', code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
278
simulators/gem5/src/arch/mips/isa/formats/unimp.isa
Normal file
278
simulators/gem5/src/arch/mips/isa/formats/unimp.isa
Normal file
@ -0,0 +1,278 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Unimplemented instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Static instruction class for unimplemented instructions that
|
||||
* cause simulator termination. Note that these are recognized
|
||||
* (legal) instructions that the simulator does not support; the
|
||||
* 'Unknown' class is used for unrecognized/illegal instructions.
|
||||
* This is a leaf class.
|
||||
*/
|
||||
class FailUnimplemented : public MipsStaticInst
|
||||
{
|
||||
public:
|
||||
/// Constructor
|
||||
FailUnimplemented(const char *_mnemonic, MachInst _machInst)
|
||||
: MipsStaticInst(_mnemonic, _machInst, No_OpClass)
|
||||
{
|
||||
// don't call execute() (which panics) if we're on a
|
||||
// speculative path
|
||||
flags[IsNonSpeculative] = true;
|
||||
}
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
class CP0Unimplemented : public MipsStaticInst
|
||||
{
|
||||
public:
|
||||
/// Constructor
|
||||
CP0Unimplemented(const char *_mnemonic, MachInst _machInst)
|
||||
: MipsStaticInst(_mnemonic, _machInst, No_OpClass)
|
||||
{
|
||||
// don't call execute() (which panics) if we're on a
|
||||
// speculative path
|
||||
flags[IsNonSpeculative] = true;
|
||||
}
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
class CP1Unimplemented : public MipsStaticInst
|
||||
{
|
||||
public:
|
||||
/// Constructor
|
||||
CP1Unimplemented(const char *_mnemonic, MachInst _machInst)
|
||||
: MipsStaticInst(_mnemonic, _machInst, No_OpClass)
|
||||
{
|
||||
// don't call execute() (which panics) if we're on a
|
||||
// speculative path
|
||||
flags[IsNonSpeculative] = true;
|
||||
}
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
class CP2Unimplemented : public MipsStaticInst
|
||||
{
|
||||
public:
|
||||
/// Constructor
|
||||
CP2Unimplemented(const char *_mnemonic, MachInst _machInst)
|
||||
: MipsStaticInst(_mnemonic, _machInst, No_OpClass)
|
||||
{
|
||||
// don't call execute() (which panics) if we're on a
|
||||
// speculative path
|
||||
flags[IsNonSpeculative] = true;
|
||||
}
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
|
||||
/**
|
||||
* Base class for unimplemented instructions that cause a warning
|
||||
* to be printed (but do not terminate simulation). This
|
||||
* implementation is a little screwy in that it will print a
|
||||
* warning for each instance of a particular unimplemented machine
|
||||
* instruction, not just for each unimplemented opcode. Should
|
||||
* probably make the 'warned' flag a static member of the derived
|
||||
* class.
|
||||
*/
|
||||
class WarnUnimplemented : public MipsStaticInst
|
||||
{
|
||||
private:
|
||||
/// Have we warned on this instruction yet?
|
||||
mutable bool warned;
|
||||
|
||||
public:
|
||||
/// Constructor
|
||||
WarnUnimplemented(const char *_mnemonic, MachInst _machInst)
|
||||
: MipsStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
|
||||
{
|
||||
// don't call execute() (which panics) if we're on a
|
||||
// speculative path
|
||||
flags[IsNonSpeculative] = true;
|
||||
}
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string
|
||||
FailUnimplemented::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||
}
|
||||
|
||||
std::string
|
||||
CP0Unimplemented::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||
}
|
||||
|
||||
std::string
|
||||
CP1Unimplemented::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||
}
|
||||
std::string
|
||||
CP2Unimplemented::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||
}
|
||||
|
||||
std::string
|
||||
WarnUnimplemented::generateDisassembly(Addr pc,
|
||||
const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (unimplemented)", mnemonic);
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
Fault
|
||||
FailUnimplemented::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
panic("attempt to execute unimplemented instruction '%s' "
|
||||
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
|
||||
inst2string(machInst));
|
||||
return NoFault;
|
||||
}
|
||||
|
||||
Fault
|
||||
CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
if (FullSystem) {
|
||||
if (!isCoprocessorEnabled(xc, 0))
|
||||
return new CoprocessorUnusableFault(0);
|
||||
else
|
||||
return new ReservedInstructionFault;
|
||||
} else {
|
||||
panic("attempt to execute unimplemented instruction '%s' "
|
||||
"(inst %#08x, opcode %#x, binary:%s)",
|
||||
mnemonic, machInst, OPCODE, inst2string(machInst));
|
||||
return NoFault;
|
||||
}
|
||||
}
|
||||
|
||||
Fault
|
||||
CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
if (FullSystem) {
|
||||
if (!isCoprocessorEnabled(xc, 1))
|
||||
return new CoprocessorUnusableFault(1);
|
||||
else
|
||||
return new ReservedInstructionFault;
|
||||
} else {
|
||||
panic("attempt to execute unimplemented instruction '%s' "
|
||||
"(inst %#08x, opcode %#x, binary:%s)",
|
||||
mnemonic, machInst, OPCODE, inst2string(machInst));
|
||||
return NoFault;
|
||||
}
|
||||
}
|
||||
|
||||
Fault
|
||||
CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
if (FullSystem) {
|
||||
if (!isCoprocessorEnabled(xc, 2))
|
||||
return new CoprocessorUnusableFault(2);
|
||||
else
|
||||
return new ReservedInstructionFault;
|
||||
} else {
|
||||
panic("attempt to execute unimplemented instruction '%s' "
|
||||
"(inst %#08x, opcode %#x, binary:%s)",
|
||||
mnemonic, machInst, OPCODE, inst2string(machInst));
|
||||
return NoFault;
|
||||
}
|
||||
}
|
||||
|
||||
Fault
|
||||
WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
if (!warned) {
|
||||
warn("\tinstruction '%s' unimplemented\n", mnemonic);
|
||||
warned = true;
|
||||
}
|
||||
|
||||
return NoFault;
|
||||
}
|
||||
}};
|
||||
|
||||
|
||||
def format FailUnimpl() {{
|
||||
iop = InstObjParams(name, 'FailUnimplemented')
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
|
||||
}};
|
||||
def format CP0Unimpl() {{
|
||||
iop = InstObjParams(name, 'CP0Unimplemented')
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
}};
|
||||
def format CP1Unimpl() {{
|
||||
iop = InstObjParams(name, 'CP1Unimplemented')
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
}};
|
||||
def format CP2Unimpl() {{
|
||||
iop = InstObjParams(name, 'CP2Unimplemented')
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
}};
|
||||
def format WarnUnimpl() {{
|
||||
iop = InstObjParams(name, 'WarnUnimplemented')
|
||||
decode_block = BasicDecodeWithMnemonic.subst(iop)
|
||||
}};
|
||||
|
||||
82
simulators/gem5/src/arch/mips/isa/formats/unknown.isa
Normal file
82
simulators/gem5/src/arch/mips/isa/formats/unknown.isa
Normal file
@ -0,0 +1,82 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2006 The Regents of The University of Michigan
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Unknown instructions
|
||||
//
|
||||
|
||||
output header {{
|
||||
/**
|
||||
* Static instruction class for unknown (illegal) instructions.
|
||||
* These cause simulator termination if they are executed in a
|
||||
* non-speculative mode. This is a leaf class.
|
||||
*/
|
||||
class Unknown : public MipsStaticInst
|
||||
{
|
||||
public:
|
||||
/// Constructor
|
||||
Unknown(MachInst _machInst)
|
||||
: MipsStaticInst("unknown", _machInst, No_OpClass)
|
||||
{
|
||||
// don't call execute() (which panics) if we're on a
|
||||
// speculative path
|
||||
flags[IsNonSpeculative] = true;
|
||||
}
|
||||
|
||||
%(BasicExecDeclare)s
|
||||
|
||||
std::string
|
||||
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
||||
};
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
std::string
|
||||
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
|
||||
"unknown", machInst, OPCODE, inst2string(machInst));
|
||||
}
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
Fault
|
||||
Unknown::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
return new ReservedInstructionFault;
|
||||
}
|
||||
}};
|
||||
|
||||
def format Unknown() {{
|
||||
decode_block = 'return new Unknown(machInst);\n'
|
||||
}};
|
||||
|
||||
103
simulators/gem5/src/arch/mips/isa/formats/util.isa
Normal file
103
simulators/gem5/src/arch/mips/isa/formats/util.isa
Normal file
@ -0,0 +1,103 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Steve Reinhardt
|
||||
// Korey Sewell
|
||||
|
||||
let {{
|
||||
def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
postacc_code = '', base_class = 'Memory',
|
||||
decode_template = BasicDecode, exec_template_base = ''):
|
||||
# Make sure flags are in lists (convert to lists if not).
|
||||
mem_flags = makeList(mem_flags)
|
||||
inst_flags = makeList(inst_flags)
|
||||
|
||||
# Some CPU models execute the memory operation as an atomic unit,
|
||||
# while others want to separate them into an effective address
|
||||
# computation and a memory access operation. As a result, we need
|
||||
# to generate three StaticInst objects. Note that the latter two
|
||||
# are nested inside the larger "atomic" one.
|
||||
|
||||
# Generate InstObjParams for each of the three objects. Note that
|
||||
# they differ only in the set of code objects contained (which in
|
||||
# turn affects the object's overall operand list).
|
||||
iop = InstObjParams(name, Name, base_class,
|
||||
{ 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
|
||||
inst_flags)
|
||||
|
||||
if mem_flags:
|
||||
mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
|
||||
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
|
||||
iop.constructor += s
|
||||
|
||||
# select templates
|
||||
|
||||
# The InitiateAcc template is the same for StoreCond templates as the
|
||||
# corresponding Store template..
|
||||
StoreCondInitiateAcc = StoreInitiateAcc
|
||||
|
||||
fullExecTemplate = eval(exec_template_base + 'Execute')
|
||||
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
|
||||
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
|
||||
|
||||
# (header_output, decoder_output, decode_block, exec_output)
|
||||
return (LoadStoreDeclare.subst(iop),
|
||||
LoadStoreConstructor.subst(iop),
|
||||
decode_template.subst(iop),
|
||||
fullExecTemplate.subst(iop)
|
||||
+ EACompExecute.subst(iop)
|
||||
+ initiateAccTemplate.subst(iop)
|
||||
+ completeAccTemplate.subst(iop))
|
||||
}};
|
||||
|
||||
output header {{
|
||||
std::string inst2string(MachInst machInst);
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
|
||||
std::string inst2string(MachInst machInst)
|
||||
{
|
||||
string str = "";
|
||||
uint32_t mask = 0x80000000;
|
||||
|
||||
for(int i=0; i < 32; i++) {
|
||||
if ((machInst & mask) == 0) {
|
||||
str += "0";
|
||||
} else {
|
||||
str += "1";
|
||||
}
|
||||
|
||||
mask = mask >> 1;
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
}};
|
||||
103
simulators/gem5/src/arch/mips/isa/includes.isa
Normal file
103
simulators/gem5/src/arch/mips/isa/includes.isa
Normal file
@ -0,0 +1,103 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Output include file directives.
|
||||
//
|
||||
|
||||
output header {{
|
||||
#include <iomanip>
|
||||
#include <iostream>
|
||||
#include <sstream>
|
||||
|
||||
#include "arch/mips/isa_traits.hh"
|
||||
#include "arch/mips/types.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "mem/packet.hh"
|
||||
}};
|
||||
|
||||
output decoder {{
|
||||
#include <cmath>
|
||||
|
||||
#include "arch/mips/decoder.hh"
|
||||
#include "arch/mips/dsp.hh"
|
||||
#include "arch/mips/dt_constants.hh"
|
||||
#include "arch/mips/faults.hh"
|
||||
#include "arch/mips/isa_traits.hh"
|
||||
#include "arch/mips/mt_constants.hh"
|
||||
#include "arch/mips/pagetable.hh"
|
||||
#include "arch/mips/pra_constants.hh"
|
||||
#include "arch/mips/tlb.hh"
|
||||
#include "arch/mips/utility.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "sim/full_system.hh"
|
||||
#if defined(linux)
|
||||
#include <fenv.h>
|
||||
#endif
|
||||
|
||||
using namespace MipsISA;
|
||||
}};
|
||||
|
||||
output exec {{
|
||||
#include <cmath>
|
||||
|
||||
#include "arch/generic/memhelpers.hh"
|
||||
#include "arch/mips/dsp.hh"
|
||||
#include "arch/mips/dt_constants.hh"
|
||||
#include "arch/mips/faults.hh"
|
||||
#include "arch/mips/isa_traits.hh"
|
||||
#include "arch/mips/mt.hh"
|
||||
#include "arch/mips/mt_constants.hh"
|
||||
#include "arch/mips/pagetable.hh"
|
||||
#include "arch/mips/pra_constants.hh"
|
||||
#include "arch/mips/tlb.hh"
|
||||
#include "arch/mips/utility.hh"
|
||||
#if defined(linux)
|
||||
#include <fenv.h>
|
||||
#endif
|
||||
|
||||
#include "base/condcodes.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/exetrace.hh"
|
||||
#include "debug/MipsPRA.hh"
|
||||
#include "mem/packet.hh"
|
||||
#include "mem/packet_access.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/full_system.hh"
|
||||
#include "sim/sim_events.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
|
||||
using namespace MipsISA;
|
||||
}};
|
||||
|
||||
61
simulators/gem5/src/arch/mips/isa/main.isa
Normal file
61
simulators/gem5/src/arch/mips/isa/main.isa
Normal file
@ -0,0 +1,61 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// MIPS ISA description file.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Include the C++ include directives
|
||||
##include "includes.isa"
|
||||
|
||||
////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Namespace statement. Everything below this line will be in the
|
||||
// MipsISAInst namespace.
|
||||
//
|
||||
|
||||
namespace MipsISA;
|
||||
|
||||
//Include the bitfield definitions
|
||||
##include "bitfields.isa"
|
||||
|
||||
//Include the operand_types and operand definitions
|
||||
##include "operands.isa"
|
||||
|
||||
//Include the base class for mips instructions, and some support code
|
||||
##include "base.isa"
|
||||
|
||||
//Include the definitions for the instruction formats
|
||||
##include "formats/formats.isa"
|
||||
|
||||
//Include the decoder definition
|
||||
##include "decoder.isa"
|
||||
157
simulators/gem5/src/arch/mips/isa/operands.isa
Normal file
157
simulators/gem5/src/arch/mips/isa/operands.isa
Normal file
@ -0,0 +1,157 @@
|
||||
// -*- mode:c++ -*-
|
||||
|
||||
// Copyright (c) 2007 MIPS Technologies, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Authors: Korey Sewell
|
||||
// Jaidev Patwardhan
|
||||
|
||||
def operand_types {{
|
||||
'sb' : 'int8_t',
|
||||
'ub' : 'uint8_t',
|
||||
'sh' : 'int16_t',
|
||||
'uh' : 'uint16_t',
|
||||
'sw' : 'int32_t',
|
||||
'uw' : 'uint32_t',
|
||||
'sd' : 'int64_t',
|
||||
'ud' : 'uint64_t',
|
||||
'sf' : 'float',
|
||||
'df' : 'double'
|
||||
}};
|
||||
|
||||
def operands {{
|
||||
#General Purpose Integer Reg Operands
|
||||
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
|
||||
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
|
||||
'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
|
||||
|
||||
#Immediate Value operand
|
||||
'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
|
||||
|
||||
#Operands used for Link or Syscall Insts
|
||||
'R31': ('IntReg', 'uw','31','IsInteger', 4),
|
||||
'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
|
||||
|
||||
#Special Integer Reg operands
|
||||
'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
|
||||
'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
|
||||
|
||||
#Bitfield-dependent HI/LO Register Access
|
||||
'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
|
||||
'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
|
||||
'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
|
||||
'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
|
||||
|
||||
#DSP Special Purpose Integer Operands
|
||||
'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
|
||||
'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
|
||||
'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
|
||||
'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
|
||||
'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
|
||||
'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
|
||||
'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
|
||||
'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
|
||||
'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
|
||||
'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
|
||||
'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
|
||||
'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
|
||||
'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
|
||||
|
||||
#Floating Point Reg Operands
|
||||
'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
|
||||
'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
|
||||
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
|
||||
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
|
||||
|
||||
#Special Purpose Floating Point Control Reg Operands
|
||||
'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
|
||||
'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
|
||||
'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
|
||||
'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
|
||||
'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
|
||||
|
||||
#Operands For Paired Singles FP Operations
|
||||
'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
|
||||
'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
|
||||
'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
|
||||
'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
|
||||
'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
|
||||
'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
|
||||
'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
|
||||
'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
|
||||
|
||||
#Status Control Reg
|
||||
'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
|
||||
|
||||
#LL Flag
|
||||
'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
|
||||
|
||||
#Thread pointer value for SE mode
|
||||
'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
|
||||
|
||||
# Index Register
|
||||
'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
|
||||
|
||||
|
||||
'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
|
||||
|
||||
#MT Control Regs
|
||||
'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
|
||||
'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
|
||||
'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
|
||||
'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
|
||||
'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
|
||||
'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
|
||||
'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
|
||||
'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
|
||||
|
||||
#CP0 Control Regs
|
||||
'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
|
||||
'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
|
||||
'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
|
||||
'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
|
||||
'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
|
||||
'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
|
||||
'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
|
||||
'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
|
||||
'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
|
||||
'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
|
||||
'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
|
||||
'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
|
||||
'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
|
||||
'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
|
||||
'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
|
||||
'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
|
||||
'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
|
||||
|
||||
#Memory Operand
|
||||
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||
|
||||
#Program Counter Operands
|
||||
'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
|
||||
'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 4),
|
||||
'NNPC': ('PCState', 'uw', 'nnpc', (None, None, 'IsControl'), 4)
|
||||
}};
|
||||
Reference in New Issue
Block a user