Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
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simulators/gem5/src/arch/arm/utility.hh
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187
simulators/gem5/src/arch/arm/utility.hh
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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* Stephen Hines
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*/
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#ifndef __ARCH_ARM_UTILITY_HH__
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#define __ARCH_ARM_UTILITY_HH__
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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namespace ArmISA {
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inline PCState
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buildRetPC(const PCState &curPC, const PCState &callPC)
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{
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PCState retPC = callPC;
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retPC.uEnd();
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return retPC;
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}
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inline bool
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testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
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{
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bool n = (nz & 0x2);
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bool z = (nz & 0x1);
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switch (code)
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{
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case COND_EQ: return z;
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case COND_NE: return !z;
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case COND_CS: return c;
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case COND_CC: return !c;
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case COND_MI: return n;
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case COND_PL: return !n;
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case COND_VS: return v;
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case COND_VC: return !v;
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case COND_HI: return (c && !z);
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case COND_LS: return !(c && !z);
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case COND_GE: return !(n ^ v);
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case COND_LT: return (n ^ v);
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case COND_GT: return !(n ^ v || z);
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case COND_LE: return (n ^ v || z);
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case COND_AL: return true;
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case COND_UC: return true;
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default:
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panic("Unhandled predicate condition: %d\n", code);
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}
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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inline void startupCPU(ThreadContext *tc, int cpuId)
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{
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tc->activate(0);
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}
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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static inline void
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copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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{
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panic("Copy Misc. Regs Not Implemented Yet\n");
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}
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void initCPU(ThreadContext *tc, int cpuId);
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static inline bool
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inUserMode(CPSR cpsr)
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{
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return cpsr.mode == MODE_USER;
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}
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static inline bool
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inUserMode(ThreadContext *tc)
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{
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return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
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}
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static inline bool
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inPrivilegedMode(CPSR cpsr)
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{
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return !inUserMode(cpsr);
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}
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static inline bool
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inPrivilegedMode(ThreadContext *tc)
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{
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return !inUserMode(tc);
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}
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static inline bool
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vfpEnabled(CPACR cpacr, CPSR cpsr)
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{
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return cpacr.cp10 == 0x3 ||
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(cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
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}
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static inline bool
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vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
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{
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if ((cpacr.cp11 == 0x3) ||
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((cpacr.cp11 == 0x1) && inPrivilegedMode(cpsr)))
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return fpexc.en && vfpEnabled(cpacr, cpsr);
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else
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return fpexc.en && vfpEnabled(cpacr, cpsr) &&
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(cpacr.cp11 == cpacr.cp10);
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}
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static inline bool
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neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
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{
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return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
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}
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uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
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void skipFunction(ThreadContext *tc);
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inline void
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advancePC(PCState &pc, const StaticInstPtr inst)
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{
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inst->advancePC(pc);
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}
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Addr truncPage(Addr addr);
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Addr roundPage(Addr addr);
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inline uint64_t
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getExecutingAsid(ThreadContext *tc)
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{
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return tc->readMiscReg(MISCREG_CONTEXTIDR);
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}
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}
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#endif
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