Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
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simulators/gem5/src/arch/alpha/ipr.hh
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simulators/gem5/src/arch/alpha/ipr.hh
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Gabe Black
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*/
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#ifndef __ARCH_ALPHA_IPR_HH__
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#define __ARCH_ALPHA_IPR_HH__
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namespace AlphaISA {
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////////////////////////////////////////////////////////////////////////
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//
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// Internal Processor Reigsters
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//
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enum md_ipr_names {
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RAW_IPR_ISR = 0x100, // interrupt summary
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RAW_IPR_ITB_TAG = 0x101, // ITLB tag
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RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry
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RAW_IPR_ITB_ASN = 0x103, // ITLB address space
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RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp
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RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all
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RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process
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RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select
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RAW_IPR_SIRR = 0x108, // software interrupt request
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RAW_IPR_ASTRR = 0x109, // asynchronous system trap request
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RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable
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RAW_IPR_EXC_ADDR = 0x10b, // exception address
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RAW_IPR_EXC_SUM = 0x10c, // exception summary
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RAW_IPR_EXC_MASK = 0x10d, // exception mask
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RAW_IPR_PAL_BASE = 0x10e, // PAL base address
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RAW_IPR_ICM = 0x10f, // instruction current mode
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RAW_IPR_IPLR = 0x110, // interrupt priority level
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RAW_IPR_INTID = 0x111, // interrupt ID
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RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr
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RAW_IPR_IVPTBR = 0x113, // virtual page table base
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RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear
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RAW_IPR_SL_XMIT = 0x116, // serial line transmit
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RAW_IPR_SL_RCV = 0x117, // serial line receive
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RAW_IPR_ICSR = 0x118, // instruction control and status
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RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
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RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status
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RAW_IPR_PMCTR = 0x11c, // performance counter
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// PAL temporary registers...
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// register meanings gleaned from osfpal.s source code
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RAW_IPR_PALtemp0 = 0x140, // local scratch
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RAW_IPR_PALtemp1 = 0x141, // local scratch
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RAW_IPR_PALtemp2 = 0x142, // entUna
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RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
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RAW_IPR_PALtemp4 = 0x144, // memory management temp
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RAW_IPR_PALtemp5 = 0x145, // memory management temp
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RAW_IPR_PALtemp6 = 0x146, // memory management temp
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RAW_IPR_PALtemp7 = 0x147, // entIF
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RAW_IPR_PALtemp8 = 0x148, // intmask
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RAW_IPR_PALtemp9 = 0x149, // entSys
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RAW_IPR_PALtemp10 = 0x14a, // ??
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RAW_IPR_PALtemp11 = 0x14b, // entInt
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RAW_IPR_PALtemp12 = 0x14c, // entArith
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RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
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RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
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RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
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RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
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RAW_IPR_PALtemp17 = 0x151, // sysval
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RAW_IPR_PALtemp18 = 0x152, // usp
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RAW_IPR_PALtemp19 = 0x153, // ksp
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RAW_IPR_PALtemp20 = 0x154, // PTBR
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RAW_IPR_PALtemp21 = 0x155, // entMM
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RAW_IPR_PALtemp22 = 0x156, // kgp
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RAW_IPR_PALtemp23 = 0x157, // PCBB
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RAW_IPR_DTB_ASN = 0x200, // DTLB address space number
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RAW_IPR_DTB_CM = 0x201, // DTLB current mode
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RAW_IPR_DTB_TAG = 0x202, // DTLB tag
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RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry
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RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary
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RAW_IPR_MM_STAT = 0x205, // data MMU fault status
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RAW_IPR_VA = 0x206, // fault virtual address
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RAW_IPR_VA_FORM = 0x207, // formatted virtual address
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RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base
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RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process
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RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all
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RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single
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RAW_IPR_ALT_MODE = 0x20c, // alternate mode
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RAW_IPR_CC = 0x20d, // cycle counter
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RAW_IPR_CC_CTL = 0x20e, // cycle counter control
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RAW_IPR_MCSR = 0x20f, // MTU control
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RAW_IPR_DC_FLUSH = 0x210,
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RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status
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RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control
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RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag
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RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary
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RAW_IPR_DC_MODE = 0x216, // Dcache mode
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RAW_IPR_MAF_MODE = 0x217, // miss address file mode
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MaxInternalProcRegs // number of IPRs
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};
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enum MiscRegIpr
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{
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//Write only
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MinWriteOnlyIpr,
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IPR_HWINT_CLR = MinWriteOnlyIpr,
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IPR_SL_XMIT,
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IPR_DC_FLUSH,
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IPR_IC_FLUSH,
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IPR_ALT_MODE,
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IPR_DTB_IA,
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IPR_DTB_IAP,
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IPR_ITB_IA,
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MaxWriteOnlyIpr,
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IPR_ITB_IAP = MaxWriteOnlyIpr,
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//Read only
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MinReadOnlyIpr,
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IPR_INTID = MinReadOnlyIpr,
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IPR_SL_RCV,
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IPR_MM_STAT,
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IPR_ITB_PTE_TEMP,
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MaxReadOnlyIpr,
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IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
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IPR_ISR,
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IPR_ITB_TAG,
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IPR_ITB_PTE,
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IPR_ITB_ASN,
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IPR_ITB_IS,
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IPR_SIRR,
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IPR_ASTRR,
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IPR_ASTER,
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IPR_EXC_ADDR,
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IPR_EXC_SUM,
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IPR_EXC_MASK,
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IPR_PAL_BASE,
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IPR_ICM,
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IPR_IPLR,
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IPR_IFAULT_VA_FORM,
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IPR_IVPTBR,
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IPR_ICSR,
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IPR_IC_PERR_STAT,
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IPR_PMCTR,
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// PAL temporary registers...
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// register meanings gleaned from osfpal.s source code
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IPR_PALtemp0,
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IPR_PALtemp1,
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IPR_PALtemp2,
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IPR_PALtemp3,
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IPR_PALtemp4,
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IPR_PALtemp5,
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IPR_PALtemp6,
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IPR_PALtemp7,
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IPR_PALtemp8,
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IPR_PALtemp9,
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IPR_PALtemp10,
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IPR_PALtemp11,
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IPR_PALtemp12,
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IPR_PALtemp13,
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IPR_PALtemp14,
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IPR_PALtemp15,
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IPR_PALtemp16,
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IPR_PALtemp17,
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IPR_PALtemp18,
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IPR_PALtemp19,
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IPR_PALtemp20,
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IPR_PALtemp21,
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IPR_PALtemp22,
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IPR_PALtemp23,
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IPR_DTB_ASN,
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IPR_DTB_CM,
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IPR_DTB_TAG,
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IPR_DTB_PTE,
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IPR_VA,
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IPR_VA_FORM,
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IPR_MVPTBR,
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IPR_DTB_IS,
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IPR_CC,
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IPR_CC_CTL,
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IPR_MCSR,
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IPR_DC_PERR_STAT,
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IPR_DC_TEST_CTL,
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IPR_DC_TEST_TAG,
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IPR_DC_TEST_TAG_TEMP,
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IPR_DC_MODE,
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IPR_MAF_MODE,
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NumInternalProcRegs // number of IPR registers
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};
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inline bool
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IprIsWritable(int index)
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{
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return index < MinReadOnlyIpr || index > MaxReadOnlyIpr;
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}
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inline bool
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IprIsReadable(int index)
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{
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return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr;
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}
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extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
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extern int IprToMiscRegIndex[MaxInternalProcRegs];
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void initializeIprTable();
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_IPR_HH__
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