Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/src/arch/SConscript

@@ -0,0 +1,139 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import sys
+import os
+
+Import('*')
+
+#################################################################
+#
+# ISA "switch header" generation.
+#
+# Auto-generate arch headers that include the right ISA-specific
+# header based on the setting of THE_ISA preprocessor variable.
+#
+#################################################################
+
+# List of headers to generate
+isa_switch_hdrs = Split('''
+        decoder.hh
+        interrupts.hh
+        isa.hh
+        isa_traits.hh
+        kernel_stats.hh
+        locked_mem.hh
+        microcode_rom.hh
+        mmapped_ipr.hh
+        mt.hh
+        process.hh
+        registers.hh
+        remote_gdb.hh
+        stacktrace.hh
+        tlb.hh
+        types.hh
+        utility.hh
+        vtophys.hh
+        ''')
+
+# Set up this directory to support switching headers
+make_switching_dir('arch', isa_switch_hdrs, env)
+
+#################################################################
+#
+# Include architecture-specific files.
+#
+#################################################################
+
+#
+# Build a SCons scanner for ISA files
+#
+import SCons.Scanner
+
+isa_scanner = SCons.Scanner.Classic("ISAScan",
+                                    [".isa", ".ISA"],
+                                    "SRCDIR",
+                                    r'^\s*##include\s+"([\w/.-]*)"')
+
+env.Append(SCANNERS = isa_scanner)
+
+#
+# Now create a Builder object that uses isa_parser.py to generate C++
+# output from the ISA description (*.isa) files.
+#
+
+isa_parser = File('isa_parser.py')
+
+# The emitter patches up the sources & targets to include the
+# autogenerated files as targets and isa parser itself as a source.
+def isa_desc_emitter(target, source, env):
+    cpu_models = list(env['CPU_MODELS'])
+    cpu_models.append('CheckerCPU')
+
+    # Several files are generated from the ISA description.
+    # We always get the basic decoder and header file.
+    target = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ]
+    # We also get an execute file for each selected CPU model.
+    target += [CpuModel.dict[cpu].filename for cpu in cpu_models]
+
+    # List the isa parser as a source.
+    source += [ isa_parser ]
+    # Add in the CPU models.
+    source += [ Value(m) for m in cpu_models ]
+
+    return [os.path.join("generated", t) for t in target], source
+
+ARCH_DIR = Dir('.')
+
+# import ply here because SCons screws with sys.path when performing actions.
+import ply
+
+def isa_desc_action_func(target, source, env):
+    # Add the current directory to the system path so we can import files
+    sys.path[0:0] = [ ARCH_DIR.srcnode().abspath ]
+    import isa_parser
+
+    # Skip over the ISA description itself and the parser to the CPU models.
+    models = [ s.get_contents() for s in source[2:] ]
+    cpu_models = [CpuModel.dict[cpu] for cpu in models]
+    parser = isa_parser.ISAParser(target[0].dir.abspath, cpu_models)
+    parser.parse_isa_desc(source[0].abspath)
+isa_desc_action = MakeAction(isa_desc_action_func, Transform("ISA DESC", 1))
+
+# Also include the CheckerCPU as one of the models if it is being
+# enabled via command line.
+isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
+
+env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
+
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
+CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])