Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/configs/ruby/Network_test.py

@@ -0,0 +1,138 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the cache latency is only used by the sequencer on fast path hits
+#
+class Cache(RubyCache):
+    latency = 3
+
+def define_options(parser):
+    return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+    
+    if buildEnv['PROTOCOL'] != 'Network_test':
+        panic("This script requires the Network_test protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The Garnet tester protocol does not support fs nor dma
+    #
+    assert(piobus == None)
+    assert(dma_ports == [])
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    dir_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    cntrl_count = 0
+
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        # Only one cache exists for this protocol, so by default use the L1D
+        # config parameters.
+        #
+        cache = Cache(size = options.l1d_size,
+                      assoc = options.l1d_assoc)
+
+        #
+        # Only one unified L1 cache exists.  Can cache instructions and data.
+        #
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      cacheMemory = cache,
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(icache = cache,
+                                dcache = cache,
+                                using_network_tester = True,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+        cntrl_count += 1
+
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory(version = i,
+                                                             size = dir_size),
+                                         memBuffer = mem_cntrl,
+                                         ruby_system = ruby_system)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)