Adding gem5 source to svn.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/configs/ruby/MESI_CMP_directory.py

@@ -0,0 +1,188 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+    latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+    latency = 15
+
+def define_options(parser):
+    return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+    
+    if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
+        panic("This script requires the MESI_CMP_directory protocol to be built.")
+
+    cpu_sequencers = []
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    l2_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    dma_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+    l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
+    
+    cntrl_count = 0
+    
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l1i_cache = L1Cache(size = options.l1i_size,
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
+        l1d_cache = L1Cache(size = options.l1d_size,
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
+
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L1IcacheMemory = l1i_cache,
+                                      L1DcacheMemory = l1d_cache,
+                                      l2_select_num_bits = l2_bits,
+                                      send_evictions = (
+                                          options.cpu_type == "detailed"),
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
+                                dcache = l1d_cache,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+        
+        cntrl_count += 1
+
+    l2_index_start = block_size_bits + l2_bits
+
+    for i in xrange(options.num_l2caches):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l2_cache = L2Cache(size = options.l2_size,
+                           assoc = options.l2_assoc,
+                           start_index_bit = l2_index_start)
+
+        l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L2cacheMemory = l2_cache,
+                                      ruby_system = ruby_system)
+        
+        exec("system.l2_cntrl%d = l2_cntrl" % i)
+        l2_cntrl_nodes.append(l2_cntrl)
+        
+        cntrl_count += 1
+        
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory(version = i,
+                                                             size = dir_size,
+                                                             use_map =
+                                                           options.use_map),
+                                         memBuffer = mem_cntrl,
+                                         ruby_system = ruby_system)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    for i, dma_port in enumerate(dma_ports):
+        #
+        # Create the Ruby objects associated with the dma controller
+        #
+        dma_seq = DMASequencer(version = i,
+                               ruby_system = ruby_system)
+        
+        dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
+                                   dma_sequencer = dma_seq,
+                                   ruby_system = ruby_system)
+
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
+        exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+        dma_cntrl_nodes.append(dma_cntrl)
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + \
+                 l2_cntrl_nodes + \
+                 dir_cntrl_nodes + \
+                 dma_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)

simulators/gem5/configs/ruby/MI_example.py

@@ -0,0 +1,158 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+
+#
+# Note: the cache latency is only used by the sequencer on fast path hits
+#
+class Cache(RubyCache):
+    latency = 3
+
+def define_options(parser):
+    return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+    
+    if buildEnv['PROTOCOL'] != 'MI_example':
+        panic("This script requires the MI_example protocol to be built.")
+
+    cpu_sequencers = []
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    dma_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+    block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
+    
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        # Only one cache exists for this protocol, so by default use the L1D
+        # config parameters.
+        #
+        cache = Cache(size = options.l1d_size,
+                      assoc = options.l1d_assoc,
+                      start_index_bit = block_size_bits)
+
+        #
+        # Only one unified L1 cache exists.  Can cache instructions and data.
+        #
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      cacheMemory = cache,
+                                      send_evictions = (
+                                          options.cpu_type == "detailed"),
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(version = i,
+                                icache = cache,
+                                dcache = cache,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+        cntrl_count += 1
+
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory( \
+                                                    version = i,
+                                                    size = dir_size,
+                                                    use_map = options.use_map,
+                                                    map_levels = \
+                                                      options.map_levels),
+                                         memBuffer = mem_cntrl,
+                                         ruby_system = ruby_system)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    for i, dma_port in enumerate(dma_ports):
+        #
+        # Create the Ruby objects associated with the dma controller
+        #
+        dma_seq = DMASequencer(version = i,
+                               ruby_system = ruby_system)
+        
+        dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
+                                   dma_sequencer = dma_seq,
+                                   ruby_system = ruby_system)
+
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
+        exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+        dma_cntrl_nodes.append(dma_cntrl)
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)

simulators/gem5/configs/ruby/MOESI_CMP_directory.py

@@ -0,0 +1,185 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+    latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+    latency = 15
+
+def define_options(parser):
+    return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+
+    if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
+        panic("This script requires the MOESI_CMP_directory protocol to be built.")
+
+    cpu_sequencers = []
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    l2_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    dma_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+    l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
+    
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l1i_cache = L1Cache(size = options.l1i_size,
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
+        l1d_cache = L1Cache(size = options.l1d_size,
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
+
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L1IcacheMemory = l1i_cache,
+                                      L1DcacheMemory = l1d_cache,
+                                      l2_select_num_bits = l2_bits,
+                                      send_evictions = (
+                                          options.cpu_type == "detailed"),
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
+                                dcache = l1d_cache,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+        cntrl_count += 1
+
+    l2_index_start = block_size_bits + l2_bits
+
+    for i in xrange(options.num_l2caches):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l2_cache = L2Cache(size = options.l2_size,
+                           assoc = options.l2_assoc,
+                           start_index_bit = l2_index_start)
+
+        l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L2cacheMemory = l2_cache,
+                                      ruby_system = ruby_system)
+        
+        exec("system.l2_cntrl%d = l2_cntrl" % i)
+        l2_cntrl_nodes.append(l2_cntrl)
+
+        cntrl_count += 1
+        
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory(version = i,
+                                                             size = dir_size),
+                                         memBuffer = mem_cntrl,
+                                         ruby_system = ruby_system)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    for i, dma_port in enumerate(dma_ports):
+        #
+        # Create the Ruby objects associated with the dma controller
+        #
+        dma_seq = DMASequencer(version = i,
+                               ruby_system = ruby_system)
+        
+        dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
+                                   dma_sequencer = dma_seq,
+                                   ruby_system = ruby_system)
+
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
+        exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+        dma_cntrl_nodes.append(dma_cntrl)
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + \
+                 l2_cntrl_nodes + \
+                 dir_cntrl_nodes + \
+                 dma_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)

simulators/gem5/configs/ruby/MOESI_CMP_token.py

@@ -0,0 +1,209 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+    latency = 2
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+    latency = 10
+
+def define_options(parser):
+    parser.add_option("--l1-retries", type="int", default=1,
+                      help="Token_CMP: # of l1 retries before going persistent")
+    parser.add_option("--timeout-latency", type="int", default=300,
+                      help="Token_CMP: cycles until issuing again");
+    parser.add_option("--disable-dyn-timeouts", action="store_true",
+          help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
+    parser.add_option("--allow-atomic-migration", action="store_true",
+          help="allow migratory sharing for atomic only accessed blocks")
+    
+def create_system(options, system, piobus, dma_ports, ruby_system):
+    
+    if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
+        panic("This script requires the MOESI_CMP_token protocol to be built.")
+
+    #
+    # number of tokens that the owner passes to requests so that shared blocks can
+    # respond to read requests
+    #
+    n_tokens = options.num_cpus + 1
+
+    cpu_sequencers = []
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    l2_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    dma_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+    l2_bits = int(math.log(options.num_l2caches, 2))
+    block_size_bits = int(math.log(options.cacheline_size, 2))
+    
+    cntrl_count = 0
+
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l1i_cache = L1Cache(size = options.l1i_size,
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits)
+        l1d_cache = L1Cache(size = options.l1d_size,
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
+
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L1IcacheMemory = l1i_cache,
+                                      L1DcacheMemory = l1d_cache,
+                                      l2_select_num_bits = l2_bits,
+                                      N_tokens = n_tokens,
+                                      retry_threshold = \
+                                        options.l1_retries,
+                                      fixed_timeout_latency = \
+                                        options.timeout_latency,
+                                      dynamic_timeout_enabled = \
+                                        not options.disable_dyn_timeouts,
+                                      no_mig_atomic = not \
+                                        options.allow_atomic_migration,
+                                      send_evictions = (
+                                          options.cpu_type == "detailed"),
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
+                                dcache = l1d_cache,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+        cntrl_count += 1
+
+    l2_index_start = block_size_bits + l2_bits
+
+    for i in xrange(options.num_l2caches):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l2_cache = L2Cache(size = options.l2_size,
+                           assoc = options.l2_assoc,
+                           start_index_bit = l2_index_start)
+
+        l2_cntrl = L2Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L2cacheMemory = l2_cache,
+                                      N_tokens = n_tokens,
+                                      ruby_system = ruby_system)
+        
+        exec("system.l2_cntrl%d = l2_cntrl" % i)
+        l2_cntrl_nodes.append(l2_cntrl)
+
+        cntrl_count += 1
+        
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory(version = i,
+                                                             size = dir_size),
+                                         memBuffer = mem_cntrl,
+                                         l2_select_num_bits = l2_bits,
+                                         ruby_system = ruby_system)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    for i, dma_port in enumerate(dma_ports):
+        #
+        # Create the Ruby objects associated with the dma controller
+        #
+        dma_seq = DMASequencer(version = i,
+                               ruby_system = ruby_system)
+        
+        dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
+                                   dma_sequencer = dma_seq,
+                                   ruby_system = ruby_system)
+
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
+        exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+        dma_cntrl_nodes.append(dma_cntrl)
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + \
+                 l2_cntrl_nodes + \
+                 dir_cntrl_nodes + \
+                 dma_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)

simulators/gem5/configs/ruby/MOESI_hammer.py

@@ -0,0 +1,222 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+    latency = 2
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+    latency = 10
+
+#
+# Probe filter is a cache, latency is not used
+#
+class ProbeFilter(RubyCache):
+    latency = 1
+
+def define_options(parser):
+    parser.add_option("--allow-atomic-migration", action="store_true",
+          help="allow migratory sharing for atomic only accessed blocks")
+    parser.add_option("--pf-on", action="store_true",
+          help="Hammer: enable Probe Filter")
+    parser.add_option("--dir-on", action="store_true",
+          help="Hammer: enable Full-bit Directory")
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+
+    if buildEnv['PROTOCOL'] != 'MOESI_hammer':
+        panic("This script requires the MOESI_hammer protocol to be built.")
+
+    cpu_sequencers = []
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    dir_cntrl_nodes = []
+    dma_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+    block_size_bits = int(math.log(options.cacheline_size, 2))
+
+    cntrl_count = 0
+    
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        #
+        l1i_cache = L1Cache(size = options.l1i_size,
+                            assoc = options.l1i_assoc,
+                            start_index_bit = block_size_bits,
+                            is_icache = True)
+        l1d_cache = L1Cache(size = options.l1d_size,
+                            assoc = options.l1d_assoc,
+                            start_index_bit = block_size_bits)
+        l2_cache = L2Cache(size = options.l2_size,
+                           assoc = options.l2_assoc,
+                           start_index_bit = block_size_bits)
+
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      L1IcacheMemory = l1i_cache,
+                                      L1DcacheMemory = l1d_cache,
+                                      L2cacheMemory = l2_cache,
+                                      no_mig_atomic = not \
+                                        options.allow_atomic_migration,
+                                      send_evictions = (
+                                          options.cpu_type == "detailed"),
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(version = i,
+                                icache = l1i_cache,
+                                dcache = l1d_cache,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        if options.recycle_latency:
+            l1_cntrl.recycle_latency = options.recycle_latency
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+        cntrl_count += 1
+
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    #
+    # determine size and index bits for probe filter
+    # By default, the probe filter size is configured to be twice the
+    # size of the L2 cache.
+    #
+    pf_size = MemorySize(options.l2_size)
+    pf_size.value = pf_size.value * 2
+    dir_bits = int(math.log(options.num_dirs, 2))
+    pf_bits = int(math.log(pf_size.value, 2))
+    if options.numa_high_bit:
+        if options.numa_high_bit > 0:
+            # if numa high bit explicitly set, make sure it does not overlap
+            # with the probe filter index
+            assert(options.numa_high_bit - dir_bits > pf_bits)
+
+        # set the probe filter start bit to just above the block offset
+        pf_start_bit = 6
+    else:
+        if dir_bits > 0:
+            pf_start_bit = dir_bits + 5
+        else:
+            pf_start_bit = 6
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        pf = ProbeFilter(size = pf_size, assoc = 4,
+                         start_index_bit = pf_start_bit)
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory( \
+                                                    version = i,
+                                                    size = dir_size,
+                                                    use_map = options.use_map,
+                                                    map_levels = \
+                                                    options.map_levels,
+                                                    numa_high_bit = \
+                                                      options.numa_high_bit),
+                                         probeFilter = pf,
+                                         memBuffer = mem_cntrl,
+                                         probe_filter_enabled = options.pf_on,
+                                         full_bit_dir_enabled = options.dir_on,
+                                         ruby_system = ruby_system)
+
+        if options.recycle_latency:
+            dir_cntrl.recycle_latency = options.recycle_latency
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    for i, dma_port in enumerate(dma_ports):
+        #
+        # Create the Ruby objects associated with the dma controller
+        #
+        dma_seq = DMASequencer(version = i,
+                               ruby_system = ruby_system)
+        
+        dma_cntrl = DMA_Controller(version = i,
+                                   cntrl_id = cntrl_count,
+                                   dma_sequencer = dma_seq,
+                                   ruby_system = ruby_system)
+
+        exec("system.dma_cntrl%d = dma_cntrl" % i)
+        exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+        dma_cntrl_nodes.append(dma_cntrl)
+
+        if options.recycle_latency:
+            dma_cntrl.recycle_latency = options.recycle_latency
+
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)

simulators/gem5/configs/ruby/Network_test.py

@@ -0,0 +1,138 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the cache latency is only used by the sequencer on fast path hits
+#
+class Cache(RubyCache):
+    latency = 3
+
+def define_options(parser):
+    return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+    
+    if buildEnv['PROTOCOL'] != 'Network_test':
+        panic("This script requires the Network_test protocol to be built.")
+
+    cpu_sequencers = []
+
+    #
+    # The Garnet tester protocol does not support fs nor dma
+    #
+    assert(piobus == None)
+    assert(dma_ports == [])
+    
+    #
+    # The ruby network creation expects the list of nodes in the system to be
+    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
+    # listed before the directory nodes and directory nodes before dma nodes, etc.
+    #
+    l1_cntrl_nodes = []
+    dir_cntrl_nodes = []
+
+    #
+    # Must create the individual controllers before the network to ensure the
+    # controller constructors are called before the network constructor
+    #
+
+    cntrl_count = 0
+
+    for i in xrange(options.num_cpus):
+        #
+        # First create the Ruby objects associated with this cpu
+        # Only one cache exists for this protocol, so by default use the L1D
+        # config parameters.
+        #
+        cache = Cache(size = options.l1d_size,
+                      assoc = options.l1d_assoc)
+
+        #
+        # Only one unified L1 cache exists.  Can cache instructions and data.
+        #
+        l1_cntrl = L1Cache_Controller(version = i,
+                                      cntrl_id = cntrl_count,
+                                      cacheMemory = cache,
+                                      ruby_system = ruby_system)
+
+        cpu_seq = RubySequencer(icache = cache,
+                                dcache = cache,
+                                using_network_tester = True,
+                                ruby_system = ruby_system)
+
+        l1_cntrl.sequencer = cpu_seq
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.slave
+
+        exec("system.l1_cntrl%d = l1_cntrl" % i)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+        cntrl_count += 1
+
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    mem_module_size = phys_mem_size / options.num_dirs
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
+
+        mem_cntrl = RubyMemoryControl(version = i)
+
+        dir_size = MemorySize('0B')
+        dir_size.value = mem_module_size
+
+        dir_cntrl = Directory_Controller(version = i,
+                                         cntrl_id = cntrl_count,
+                                         directory = \
+                                         RubyDirectoryMemory(version = i,
+                                                             size = dir_size),
+                                         memBuffer = mem_cntrl,
+                                         ruby_system = ruby_system)
+
+        exec("system.dir_cntrl%d = dir_cntrl" % i)
+        dir_cntrl_nodes.append(dir_cntrl)
+
+        cntrl_count += 1
+
+    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
+
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)

simulators/gem5/configs/ruby/Ruby.py

@@ -0,0 +1,189 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+
+def define_options(parser):
+    # By default, ruby uses the simple timing cpu
+    parser.set_defaults(cpu_type="timing")
+
+    # ruby network options
+    parser.add_option("--topology", type="string", default="Crossbar",
+                 help="check src/mem/ruby/network/topologies for complete set")
+    parser.add_option("--mesh-rows", type="int", default=1,
+                      help="the number of rows in the mesh topology")
+    parser.add_option("--garnet-network", type="string", default=None,
+                      help="'fixed'|'flexible'")
+    parser.add_option("--network-fault-model", action="store_true", default=False,
+                      help="enable network fault model: see src/mem/ruby/network/fault_model/")
+
+    # ruby mapping options
+    parser.add_option("--numa-high-bit", type="int", default=0,
+                      help="high order address bit to use for numa mapping. " \
+                           "0 = highest bit, not specified = lowest bit")
+
+    # ruby sparse memory options
+    parser.add_option("--use-map", action="store_true", default=False)
+    parser.add_option("--map-levels", type="int", default=4)
+
+    parser.add_option("--recycle-latency", type="int", default=10,
+                      help="Recycle latency for ruby controller input buffers")
+
+    parser.add_option("--random_seed", type="int", default=1234,
+                      help="Used for seeding the random number generator")
+
+    parser.add_option("--ruby_stats", type="string", default="ruby.stats")
+
+    protocol = buildEnv['PROTOCOL']
+    exec "import %s" % protocol
+    eval("%s.define_options(parser)" % protocol)
+
+def create_system(options, system, piobus = None, dma_ports = []):
+
+    system.ruby = RubySystem(clock = options.clock,
+                             stats_filename = options.ruby_stats,
+                             no_mem_vec = options.use_map)
+    ruby = system.ruby
+
+    protocol = buildEnv['PROTOCOL']
+    exec "import %s" % protocol
+    try:
+        (cpu_sequencers, dir_cntrls, all_cntrls) = \
+             eval("%s.create_system(options, system, piobus, dma_ports, ruby)"
+                  % protocol)
+    except:
+        print "Error: could not create sytem for ruby protocol %s" % protocol
+        raise
+
+    # Create a port proxy for connecting the system port. This is
+    # independent of the protocol and kept in the protocol-agnostic
+    # part (i.e. here).
+    sys_port_proxy = RubyPortProxy(ruby_system = ruby)
+    # Give the system port proxy a SimObject parent without creating a
+    # full-fledged controller
+    system.sys_port_proxy = sys_port_proxy
+
+    # Connect the system port for loading of binaries etc
+    system.system_port = system.sys_port_proxy.slave
+
+
+    #
+    # Set the network classes based on the command line options
+    #
+    if options.garnet_network == "fixed":
+        class NetworkClass(GarnetNetwork_d): pass
+        class IntLinkClass(GarnetIntLink_d): pass
+        class ExtLinkClass(GarnetExtLink_d): pass
+        class RouterClass(GarnetRouter_d): pass
+    elif options.garnet_network == "flexible":
+        class NetworkClass(GarnetNetwork): pass
+        class IntLinkClass(GarnetIntLink): pass
+        class ExtLinkClass(GarnetExtLink): pass
+        class RouterClass(GarnetRouter): pass
+    else:
+        class NetworkClass(SimpleNetwork): pass
+        class IntLinkClass(SimpleIntLink): pass
+        class ExtLinkClass(SimpleExtLink): pass
+        class RouterClass(BasicRouter): pass
+    
+    #
+    # Important: the topology must be created before the network and after the
+    # controllers.
+    #
+    exec "import %s" % options.topology
+    try:
+        net_topology = eval("%s.makeTopology(all_cntrls, options, \
+                                             IntLinkClass, ExtLinkClass, \
+                                             RouterClass)" \
+                            % options.topology)
+    except:
+        print "Error: could not create topology %s" % options.topology
+        raise
+
+    if options.network_fault_model:
+        assert(options.garnet_network == "fixed")
+        fault_model = FaultModel()
+        network = NetworkClass(ruby_system = ruby, topology = net_topology,\
+                               enable_fault_model=True, fault_model = fault_model)
+    else:
+        network = NetworkClass(ruby_system = ruby, topology = net_topology)
+
+    #
+    # Loop through the directory controlers.
+    # Determine the total memory size of the ruby system and verify it is equal
+    # to physmem.  However, if Ruby memory is using sparse memory in SE 
+    # mode, then the system should not back-up the memory state with
+    # the Memory Vector and thus the memory size bytes should stay at 0.
+    # Also set the numa bits to the appropriate values.
+    #
+    total_mem_size = MemorySize('0B')
+
+    dir_bits = int(math.log(options.num_dirs, 2))
+
+    if options.numa_high_bit:
+        numa_bit = options.numa_high_bit
+    else:
+        # if not specified, use the lowest bits above the block offest
+        if dir_bits > 0:
+            # add 5 because bits 0-5 are the block offset
+            numa_bit = dir_bits + 5
+        else:
+            numa_bit = 6
+        
+    for dir_cntrl in dir_cntrls:
+        total_mem_size.value += dir_cntrl.directory.size.value
+        dir_cntrl.directory.numa_high_bit = numa_bit
+        
+    phys_mem_size = 0
+    for mem in system.memories.unproxy(system):
+        phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+    assert(total_mem_size.value == phys_mem_size)
+
+    ruby_profiler = RubyProfiler(ruby_system = ruby,
+                                 num_of_sequencers = len(cpu_sequencers))
+    ruby.network = network
+    ruby.profiler = ruby_profiler
+    ruby.mem_size = total_mem_size
+    ruby._cpu_ruby_ports = cpu_sequencers
+    ruby.random_seed    = options.random_seed