Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
12
simulators/gem5/configs/boot/ammp.rcS
Normal file
12
simulators/gem5/configs/boot/ammp.rcS
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@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/ammp00/
|
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|
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/sbin/m5 checkpoint 0 0
|
||||
/sbin/m5 checkpoint 100000000 200000000
|
||||
|
||||
/sbin/m5 loadsymbol
|
||||
|
||||
/sbin/m5 resetstats
|
||||
./ammp < input/mdred.in
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||||
/sbin/m5 exit
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||||
257
simulators/gem5/configs/boot/ammp.symbol
Normal file
257
simulators/gem5/configs/boot/ammp.symbol
Normal file
@ -0,0 +1,257 @@
|
||||
000000012001da40 T AMMPmonitor
|
||||
000000012001dfc0 T AMMPmonitor_mute
|
||||
0000000120034338 D _DYNAMIC
|
||||
00000001200346c8 D _GLOBAL_OFFSET_TABLE_
|
||||
0000000120034d60 G _IO_stdin_used
|
||||
0000000120034500 T _PROCEDURE_LINKAGE_TABLE_
|
||||
00000001200344e0 d __CTOR_END__
|
||||
00000001200344d8 d __CTOR_LIST__
|
||||
00000001200344f0 d __DTOR_END__
|
||||
00000001200344e8 d __DTOR_LIST__
|
||||
0000000120034334 r __FRAME_END__
|
||||
00000001200344f8 d __JCR_END__
|
||||
00000001200344f8 d __JCR_LIST__
|
||||
0000000120034da0 A __bss_start
|
||||
00000001200328c8 D __data_start
|
||||
0000000120020c40 t __do_global_ctors_aux
|
||||
0000000120001090 t __do_global_dtors_aux
|
||||
0000000120034d68 G __dso_handle
|
||||
00000001200328c8 A __fini_array_end
|
||||
00000001200328c8 A __fini_array_start
|
||||
00000001200328c8 A __init_array_end
|
||||
00000001200328c8 A __init_array_start
|
||||
0000000120020ba0 T __libc_csu_fini
|
||||
0000000120020af0 T __libc_csu_init
|
||||
0000000120001050 W __start
|
||||
0000000120034da0 A _edata
|
||||
0000000120035418 A _end
|
||||
0000000120020ca0 T _fini
|
||||
0000000120000fe8 T _init
|
||||
0000000120001050 T _start
|
||||
000000012000d220 T a_angle
|
||||
000000012000b3d0 T a_bond
|
||||
000000012000e1b0 T a_c_angle
|
||||
0000000120009cd0 T a_d_zero
|
||||
0000000120009c90 T a_f_zero
|
||||
0000000120009f70 T a_ftodx
|
||||
000000012000a000 T a_ftogx
|
||||
000000012000a090 T a_ftovx
|
||||
0000000120009d20 T a_g_zero
|
||||
0000000120010950 T a_hybrid
|
||||
000000012000a7c0 T a_inactive_f_zero
|
||||
0000000120009e50 T a_inc_d
|
||||
0000000120009dc0 T a_inc_f
|
||||
0000000120009ee0 T a_inc_v
|
||||
000000012000a370 T a_l2_d
|
||||
000000012000a220 T a_l2_f
|
||||
000000012000a290 T a_l2_g
|
||||
000000012000a300 T a_l2_v
|
||||
0000000120008bf0 T a_m_serial
|
||||
000000012000a1a0 T a_max_d
|
||||
000000012000a120 T a_max_f
|
||||
000000012000d570 T a_mmangle
|
||||
000000012000b620 T a_mmbond
|
||||
0000000120009c30 T a_next
|
||||
0000000120005350 T a_noel
|
||||
0000000120004700 T a_nonbon
|
||||
0000000120009bc0 T a_number
|
||||
00000001200096b0 T a_pr_beta
|
||||
000000012000a660 T a_readvelocity
|
||||
0000000120020750 T a_restrain
|
||||
000000012001eda0 T a_tether
|
||||
000000012001a2e0 T a_torsion
|
||||
0000000120009d70 T a_v_zero
|
||||
0000000120003c90 T aaerror
|
||||
0000000120009a60 T activate
|
||||
000000012001fef0 T alltether
|
||||
0000000120004370 T analyze
|
||||
000000012000c0d0 T angle
|
||||
0000000120034df8 S angle_first
|
||||
0000000120034e00 S angle_last
|
||||
0000000120034dd0 s ap.2
|
||||
0000000120034de0 s ap.4
|
||||
0000000120008970 T atom
|
||||
0000000120034dc8 s atomNUMBER
|
||||
0000000120034dcc s atomUPDATE
|
||||
000000012000a8b0 T bond
|
||||
0000000120034de8 S bond_first
|
||||
0000000120034df0 S bond_last
|
||||
000000012000bf20 T bond_length
|
||||
000000012001f240 T bstrot
|
||||
0000000120034ea0 b buff.0
|
||||
000000012001ad40 T cngdel
|
||||
0000000120034da0 s completed.1
|
||||
00000001200200c0 T cpyvec
|
||||
00000001200328c8 W data_start
|
||||
0000000120034d98 g dielecold.0
|
||||
000000012000efe0 T dump_angles
|
||||
0000000120008d00 T dump_atoms
|
||||
000000012000be40 T dump_bonds
|
||||
000000012000a3e0 T dump_excludes
|
||||
000000012000a6c0 T dump_force
|
||||
0000000120011a50 T dump_hybrids
|
||||
0000000120005c20 T dump_noels
|
||||
0000000120008f40 T dump_pdb
|
||||
0000000120020a10 T dump_restrains
|
||||
000000012001ffe0 T dump_tethers
|
||||
0000000120017b30 T dump_tgroup
|
||||
000000012001a170 T dump_torsions
|
||||
000000012001b7a0 T dump_variable
|
||||
000000012000a590 T dump_velocity
|
||||
0000000120034d7c g echo.0
|
||||
0000000120001760 T eval
|
||||
000000012000c580 T f_angle
|
||||
000000012000ac60 T f_bond
|
||||
0000000120001230 T f_box
|
||||
000000012000dc50 T f_c_angle
|
||||
000000012000ea10 T f_ho_angle
|
||||
000000012000bab0 T f_ho_bond
|
||||
0000000120011020 T f_ho_hybrid
|
||||
0000000120005840 T f_ho_noel
|
||||
000000012001fca0 T f_ho_tether
|
||||
00000001200102b0 T f_hybrid
|
||||
000000012000cd10 T f_mmangle
|
||||
000000012000b0e0 T f_mmbond
|
||||
0000000120005060 T f_noel
|
||||
00000001200155d0 T f_nonbon
|
||||
0000000120020500 T f_restrain
|
||||
000000012001ebd0 T f_tether
|
||||
0000000120019850 T f_torsion
|
||||
000000012000fbd0 T f_trace
|
||||
0000000120034db8 S first
|
||||
0000000120035058 B forces
|
||||
0000000120001130 t frame_dummy
|
||||
0000000120014b20 T fv_update_nonbon
|
||||
0000000120034e58 s fx.0
|
||||
0000000120034e60 s fy.1
|
||||
0000000120034e68 s fz.2
|
||||
000000012000ef40 T get_angle
|
||||
000000012000bda0 T get_bond
|
||||
000000012000c050 T get_bond_pointer
|
||||
000000012001b6e0 T get_f_variable
|
||||
00000001200119b0 T get_hybrid
|
||||
000000012001b740 T get_i_variable
|
||||
0000000120005b80 T get_noel
|
||||
0000000120020970 T get_restrain
|
||||
000000012001a9f0 T get_torsion
|
||||
00000001200184a0 T get_torsion_value
|
||||
000000012001ca50 T getatomdata
|
||||
000000012000f130 T gsdg
|
||||
000000012000e5a0 T gsdg_angle
|
||||
000000012000bfc0 T gsdg_bond
|
||||
000000012000f810 T gsdg_dgeom
|
||||
0000000120011790 T gsdg_hybrid
|
||||
000000012000f6c0 T gsdg_line_search
|
||||
0000000120005d30 T gsdg_noel
|
||||
000000012001a850 T gsdg_torsion
|
||||
0000000120034d84 g highest.0
|
||||
0000000120007490 T hpac
|
||||
000000012000fe30 T hybrid
|
||||
0000000120034e08 S hybrid_first
|
||||
0000000120034e10 S hybrid_last
|
||||
0000000120034e70 S in_mom_list
|
||||
0000000120009920 T inactivate
|
||||
00000001200097a0 T inactivate_non_zero
|
||||
0000000120034d80 g inloop.1
|
||||
0000000120034e74 s ip.1
|
||||
0000000120034e78 s jp.2
|
||||
0000000120034e7c s kp.3
|
||||
0000000120034dc0 S last
|
||||
0000000120034dd8 s lastmatched.3
|
||||
000000012001b0d0 T linmin
|
||||
0000000120003f80 T loadloop
|
||||
0000000120034e28 s local.3
|
||||
0000000120034d88 g lowest.1
|
||||
0000000120034e20 s lsize.2
|
||||
0000000120001180 T main
|
||||
0000000120017c10 T match_tgroup
|
||||
000000012001b450 T match_variable
|
||||
000000012001b860 T math
|
||||
000000012001cd40 T math_findlabel
|
||||
000000012001ccb0 T math_match_atom
|
||||
0000000120020100 T matmul
|
||||
0000000120012b90 T mm_fv_update_nonbon
|
||||
000000012001cef0 T mom
|
||||
000000012001d3f0 T mom_add
|
||||
000000012001d900 T mom_jab
|
||||
00000001200350f8 B mom_list
|
||||
000000012001d890 T mom_param
|
||||
000000012001d600 T mom_solve
|
||||
0000000120004c70 T noel
|
||||
0000000120034da8 S noel_first
|
||||
0000000120034db0 S noel_last
|
||||
0000000120034d78 G nused
|
||||
0000000120034e18 s oldatomnumber.0
|
||||
0000000120034d90 g oldcutoff.4
|
||||
0000000120034d70 g p.0
|
||||
0000000120006430 T pac
|
||||
0000000120006dd0 T pacpac
|
||||
00000001200350a8 B potentials
|
||||
0000000120007ac0 T ppac
|
||||
0000000120008180 T ptpac
|
||||
000000012001e840 T rand3
|
||||
000000012001e480 T randf
|
||||
000000012001e760 T randg
|
||||
0000000120001550 T read_eval_do
|
||||
00000001200201c0 T restrain
|
||||
0000000120034e90 S restrain_first
|
||||
0000000120034e98 S restrain_last
|
||||
000000012001b4e0 T set_f_variable
|
||||
000000012001b5e0 T set_i_variable
|
||||
0000000120018730 T set_torsion
|
||||
000000012001e2a0 T significance
|
||||
0000000120034e1c s since.1
|
||||
000000012001aa90 T steep
|
||||
0000000120018f50 T tailor_exclude
|
||||
0000000120018d30 T tailor_include
|
||||
0000000120019110 T tailor_qab
|
||||
000000012001e940 T tether
|
||||
0000000120034e80 S tether_first
|
||||
0000000120034e88 S tether_last
|
||||
00000001200171f0 T tg_apply
|
||||
0000000120017490 T tg_d_apply
|
||||
0000000120016fd0 T tg_do_search
|
||||
0000000120034e30 S tg_first
|
||||
0000000120017a20 T tg_gen_con
|
||||
0000000120016b90 T tg_init
|
||||
0000000120017700 T tg_nonbon
|
||||
0000000120016220 T tgroup
|
||||
0000000120004220 T tisint
|
||||
0000000120003cd0 T tisvariable
|
||||
00000001200189e0 T tmap
|
||||
0000000120017ec0 T tmin
|
||||
0000000120019190 T torsion
|
||||
0000000120034e38 S torsion_first
|
||||
0000000120034e40 S torsion_last
|
||||
0000000120006840 T tpac
|
||||
0000000120016800 T tsearch
|
||||
0000000120017c80 T tset
|
||||
0000000120018200 T tset_bond_build
|
||||
0000000120012100 T u_f_nonbon
|
||||
0000000120011b60 T u_v_nonbon
|
||||
0000000120012770 T uselist
|
||||
000000012000c310 T v_angle
|
||||
000000012000aac0 T v_bond
|
||||
0000000120001540 T v_box
|
||||
000000012000d930 T v_c_angle
|
||||
000000012000e750 T v_ho_angle
|
||||
000000012000b8a0 T v_ho_bond
|
||||
0000000120010ce0 T v_ho_hybrid
|
||||
00000001200055e0 T v_ho_noel
|
||||
000000012001faf0 T v_ho_tether
|
||||
000000012000fff0 T v_hybrid
|
||||
0000000120005dc0 T v_maxwell
|
||||
000000012000ca20 T v_mmangle
|
||||
000000012000aef0 T v_mmbond
|
||||
0000000120004e60 T v_noel
|
||||
0000000120015a80 T v_nonbon
|
||||
0000000120005fd0 T v_rescale
|
||||
0000000120020360 T v_restrain
|
||||
000000012001eab0 T v_tether
|
||||
00000001200193e0 T v_torsion
|
||||
000000012000f990 T v_trace
|
||||
000000012001c6f0 T validatom
|
||||
0000000120034e48 S variableFIRST
|
||||
0000000120034e50 S variableLAST
|
||||
00000001200061a0 T verlet
|
||||
0000000120015ec0 T zone_nonbon
|
||||
7
simulators/gem5/configs/boot/art.rcS
Normal file
7
simulators/gem5/configs/boot/art.rcS
Normal file
@ -0,0 +1,7 @@
|
||||
#!/bin/sh
|
||||
|
||||
#/benchmarks/spec/art00/art -scanfile c756hel.in -trainfile1 a10.img -stride 2 -startx 134 -starty 220 -endx 184 -endy 240 -objects 3
|
||||
cd /benchmarks/spec/art00/
|
||||
/sbin/m5 resetstats
|
||||
/benchmarks/spec/art00/art -scanfile c756hel.in -trainfile1 a10.img -stride 5 -startx 134 -starty 220 -endx 184 -endy 240 -objects 1
|
||||
/sbin/m5 exit
|
||||
38
simulators/gem5/configs/boot/bbench-gb.rcS
Normal file
38
simulators/gem5/configs/boot/bbench-gb.rcS
Normal file
@ -0,0 +1,38 @@
|
||||
#!/system/bin/sh
|
||||
|
||||
#Author: Anthony Gutierrez
|
||||
# run script for bbench on gingerbread
|
||||
|
||||
stop_m5() {
|
||||
/sbin/m5 exit
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
wait_bb_finishfifo() {
|
||||
echo "<html><head>FINISH</head><body><h1>FINISH</h1></body></html>" > /data/bbench/finish_fifo.html
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
mkfifo_bbench() {
|
||||
mkfifo /data/bbench/finish_fifo.html
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
run_bbench_test() {
|
||||
mkfifo_bbench
|
||||
am start -n com.android.browser/.BrowserActivity
|
||||
wait_bb_finishfifo
|
||||
|
||||
rm /data/bbench/finish_fifo.html
|
||||
stop_m5
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
sleep 10
|
||||
/sbin/m5 dumpstats
|
||||
/sbin/m5 resetstats
|
||||
run_bbench_test
|
||||
38
simulators/gem5/configs/boot/bbench-ics.rcS
Normal file
38
simulators/gem5/configs/boot/bbench-ics.rcS
Normal file
@ -0,0 +1,38 @@
|
||||
#!/system/bin/sh
|
||||
|
||||
#Author: Anthony Gutierrez
|
||||
# run script for bbench on ics
|
||||
|
||||
stop_m5() {
|
||||
/sbin/m5 exit
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
wait_bb_finishfifo() {
|
||||
echo "<html><head>FINISH</head><body><h1>FINISH</h1></body></html>" > /data/bbench/finish_fifo.html
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
mkfifo_bbench() {
|
||||
/sbin/busybox mkfifo /data/bbench/finish_fifo.html
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
run_bbench_test() {
|
||||
mkfifo_bbench
|
||||
am start -a android.intent.action.VIEW -d file:///data/bbench/index.html -t application/x-webarchive-xml
|
||||
wait_bb_finishfifo
|
||||
|
||||
rm /data/bbench/finish_fifo.html
|
||||
stop_m5
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
sleep 10
|
||||
/sbin/m5 dumpstats
|
||||
/sbin/m5 resetstats
|
||||
run_bbench_test
|
||||
43
simulators/gem5/configs/boot/bbench.rcS
Normal file
43
simulators/gem5/configs/boot/bbench.rcS
Normal file
@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#Author: Anthony Gutierrez
|
||||
|
||||
stop_m5() {
|
||||
echo "FINISHED";
|
||||
/sbin/m5 exit
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
wait_bb_finishfifo() {
|
||||
echo "<html><head>FINISH</head><body><h1>FINISH</h1></body></html>" > /data/bbench/finish_fifo.html
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
mkfifo_bbench() {
|
||||
mkfifo /data/bbench/finish_fifo.html
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
run_bbench_test() {
|
||||
echo "STARTING BBENCH"
|
||||
|
||||
mkfifo_bbench
|
||||
|
||||
am start -n com.android.browser/.BrowserActivity
|
||||
wait_bb_finishfifo
|
||||
|
||||
echo "END OF BBENCH RUN"
|
||||
|
||||
rm /data/bbench/finish_fifo.html
|
||||
stop_m5
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
sleep 10
|
||||
/sbin/m5 dumpstats
|
||||
/sbin/m5 resetstats
|
||||
run_bbench_test
|
||||
3
simulators/gem5/configs/boot/bn-app.rcS
Normal file
3
simulators/gem5/configs/boot/bn-app.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
cd /benchmarks/bn
|
||||
./bottleneck-app
|
||||
m5 exit
|
||||
13
simulators/gem5/configs/boot/bonnie.rcS
Normal file
13
simulators/gem5/configs/boot/bonnie.rcS
Normal file
@ -0,0 +1,13 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "Mounting empty disk..."
|
||||
mkdir /tmp-space
|
||||
/bin/mount /dev/hdb1 /tmp-space
|
||||
chmod a+rwx /tmp-space
|
||||
echo "done."
|
||||
|
||||
/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /tmp-space
|
||||
m5 exit
|
||||
309
simulators/gem5/configs/boot/bonnie.symbol
Normal file
309
simulators/gem5/configs/boot/bonnie.symbol
Normal file
@ -0,0 +1,309 @@
|
||||
0000000120025cb0 V DW.ref._ZTISt9bad_alloc
|
||||
0000000120025c98 V DW.ref.__gxx_personality_v0
|
||||
0000000120025018 D _DYNAMIC
|
||||
00000001200255a0 D _GLOBAL_OFFSET_TABLE_
|
||||
0000000120025c80 G _IO_stdin_used
|
||||
00000001200251e0 T _PROCEDURE_LINKAGE_TABLE_
|
||||
000000012000e8a0 T _Unwind_Backtrace
|
||||
000000012000e860 T _Unwind_DeleteException
|
||||
000000012000c290 T _Unwind_FindEnclosingFunction
|
||||
0000000120010df0 T _Unwind_Find_FDE
|
||||
0000000120010850 t _Unwind_Find_registered_FDE
|
||||
000000012000e470 T _Unwind_ForcedUnwind
|
||||
000000012000e340 t _Unwind_ForcedUnwind_Phase2
|
||||
000000012000c260 T _Unwind_GetCFA
|
||||
000000012000c2d0 T _Unwind_GetDataRelBase
|
||||
000000012000e9d0 T _Unwind_GetGR
|
||||
000000012000e9f0 T _Unwind_GetIP
|
||||
000000012000c270 T _Unwind_GetLanguageSpecificData
|
||||
000000012000c280 T _Unwind_GetRegionStart
|
||||
000000012000c2e0 T _Unwind_GetTextRelBase
|
||||
0000000120010ac0 t _Unwind_IteratePhdrCallback
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
000000012000ab30 T _ZNKSt9exception4whatEv
|
||||
000000012000b00c T _ZNKSt9type_info10__do_catchEPKS_PPvj
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||||
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||||
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||||
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||||
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|
||||
000000012000af74 T _ZNSt10bad_typeidD1Ev
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||||
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|
||||
000000012000aadc T _ZNSt13bad_exceptionD0Ev
|
||||
000000012000aaa8 T _ZNSt13bad_exceptionD1Ev
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
000000012000aa40 T _ZNSt9exceptionD0Ev
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||||
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||||
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||||
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||||
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||||
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||||
000000012000a39c T _ZSt10unexpectedv
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
00000001200125b0 V _ZTVSt9bad_alloc
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||||
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||||
0000000120012758 V _ZTVSt9type_info
|
||||
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|
||||
0000000120025cc8 g _ZZ18__gthread_active_pvE20__gthread_active_ptr
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||||
0000000120025cc4 g _ZZ21get_globals_init_oncevE4once
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||||
0000000120009518 T _ZdlPv
|
||||
000000012000a648 T _Znam
|
||||
000000012000a580 T _Znwm
|
||||
00000001200251c0 d __CTOR_END__
|
||||
00000001200251b8 d __CTOR_LIST__
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||||
00000001200251d0 d __DTOR_END__
|
||||
00000001200251c8 d __DTOR_LIST__
|
||||
0000000120024f30 r __FRAME_END__
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||||
00000001200251d8 d __JCR_END__
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||||
00000001200251d8 d __JCR_LIST__
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||||
0000000120025ce8 A __bss_start
|
||||
000000012000a694 T __cxa_allocate_exception
|
||||
000000012000a884 T __cxa_begin_catch
|
||||
000000012000a19c T __cxa_call_unexpected
|
||||
000000012000a930 T __cxa_end_catch
|
||||
000000012000a7b4 T __cxa_free_exception
|
||||
000000012000ac84 T __cxa_get_globals
|
||||
000000012000ac3c T __cxa_get_globals_fast
|
||||
000000012000a4f8 T __cxa_rethrow
|
||||
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|
||||
0000000120024000 D __data_start
|
||||
000000012000fa50 T __deregister_frame
|
||||
000000012000fa20 T __deregister_frame_info
|
||||
000000012000f8c0 T __deregister_frame_info_bases
|
||||
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||||
0000000120002160 t __do_global_dtors_aux
|
||||
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|
||||
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|
||||
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|
||||
0000000120024000 A __fini_array_start
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000000120025ce8 A _edata
|
||||
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|
||||
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|
||||
00000001200020b0 T _init
|
||||
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|
||||
0000000120010250 t add_fdes
|
||||
0000000120025cea s already_printed_error
|
||||
00000001200094b0 T arm
|
||||
0000000120010a30 t base_from_cb_data
|
||||
000000012000fab0 t base_from_object
|
||||
000000012000bf50 t base_of_encoded_value
|
||||
00000001200094f8 T checkpoint
|
||||
00000001200100e0 t classify_object_over_fdes
|
||||
0000000120025ce8 s completed.1
|
||||
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|
||||
0000000120024000 W data_start
|
||||
0000000120009508 T debugbreak
|
||||
00000001200094e8 T dump_stats
|
||||
00000001200094f0 T dumpreset_stats
|
||||
0000000120035d40 b dwarf_reg_size_table
|
||||
0000000120025d30 b emergency_buffer
|
||||
0000000120024008 d emergency_mutex
|
||||
0000000120025cf0 s emergency_used
|
||||
000000012000caa0 t execute_cfa_program
|
||||
000000012000c520 t execute_stack_op
|
||||
0000000120025ce9 s exitNow
|
||||
000000012000c2f0 t extract_cie_info
|
||||
000000012000fd20 t fde_mixed_encoding_compare
|
||||
000000012000fc60 t fde_single_encoding_compare
|
||||
00000001200111d0 t fde_split
|
||||
000000012000fc30 t fde_unencoded_compare
|
||||
0000000120002200 t frame_dummy
|
||||
000000012000fe00 t frame_heapsort
|
||||
000000012000fb40 t get_cie_encoding
|
||||
0000000120025cf8 s globals_key
|
||||
0000000120035d30 b globals_static
|
||||
000000012000ea10 t init_dwarf_reg_size_table
|
||||
0000000120010e90 t init_object
|
||||
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|
||||
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|
||||
00000001200094c8 T ivle
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0000000120025c90 g p.0
|
||||
00000001200094b8 T quiesce
|
||||
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|
||||
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|
||||
000000012000c060 t read_sleb128
|
||||
000000012000f3f0 t read_sleb128
|
||||
000000012000c020 t read_uleb128
|
||||
000000012000f3b0 t read_uleb128
|
||||
0000000120009500 T readfile
|
||||
00000001200094e0 T reset_stats
|
||||
0000000120010560 t search_object
|
||||
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|
||||
000000012000bed0 t size_of_encoded_value
|
||||
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|
||||
0000000120009510 T switchcpu
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
000000012000d390 t uw_update_context_1
|
||||
6
simulators/gem5/configs/boot/bzip.rcS
Normal file
6
simulators/gem5/configs/boot/bzip.rcS
Normal file
@ -0,0 +1,6 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/bzip200/
|
||||
/sbin/m5 resetstats
|
||||
/benchmarks/spec/bzip200/bzip2 lgred.graphic 1
|
||||
/sbin/m5 exit
|
||||
3454
simulators/gem5/configs/boot/cc1.symbol
Normal file
3454
simulators/gem5/configs/boot/cc1.symbol
Normal file
File diff suppressed because it is too large
Load Diff
8
simulators/gem5/configs/boot/devtime.rcS
Normal file
8
simulators/gem5/configs/boot/devtime.rcS
Normal file
@ -0,0 +1,8 @@
|
||||
insmod /modules/devtime.ko dataAddr=0x9000008 count=100
|
||||
rmmod devtime
|
||||
insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100
|
||||
rmmod devtime
|
||||
insmod /modules/devtime.ko memTest=1 count=100
|
||||
rmmod devtime
|
||||
m5 exit
|
||||
|
||||
12
simulators/gem5/configs/boot/equake.rcS
Normal file
12
simulators/gem5/configs/boot/equake.rcS
Normal file
@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/equake00/
|
||||
|
||||
/sbin/m5 checkpoint 0 0
|
||||
/sbin/m5 checkpoint 100000000 200000000
|
||||
|
||||
/sbin/m5 loadsymbol
|
||||
|
||||
/sbin/m5 resetstats
|
||||
/benchmarks/spec/equake00/equake < lgred.in
|
||||
/sbin/m5 exit
|
||||
94
simulators/gem5/configs/boot/equake.symbol
Normal file
94
simulators/gem5/configs/boot/equake.symbol
Normal file
@ -0,0 +1,94 @@
|
||||
000000012001a868 S ARCHcholeskylen
|
||||
000000012001a878 S ARCHcoord
|
||||
000000012001a930 S ARCHcorners
|
||||
000000012001a938 S ARCHduration
|
||||
000000012001a940 S ARCHelems
|
||||
000000012001a8b0 S ARCHglobalelem
|
||||
000000012001a8d0 S ARCHglobalelems
|
||||
000000012001a8e8 S ARCHglobalnode
|
||||
000000012001a8a8 S ARCHglobalnodes
|
||||
000000012001a8d8 S ARCHmatrixcol
|
||||
000000012001a898 S ARCHmatrixindex
|
||||
000000012001a924 S ARCHmatrixlen
|
||||
000000012001a8ac S ARCHmesh_dim
|
||||
000000012001a8f8 S ARCHmine
|
||||
000000012001a90c S ARCHnodes
|
||||
000000012001a908 S ARCHpriv
|
||||
000000012001a920 S ARCHsubdomains
|
||||
000000012001a8b8 S ARCHvertex
|
||||
000000012001a900 S C
|
||||
000000012001a918 S C23
|
||||
000000012001a9a8 B Damp
|
||||
000000012001a9c8 B Exc
|
||||
000000012001a8a0 S K
|
||||
000000012001a928 S M
|
||||
000000012001a888 S M23
|
||||
000000012001a950 B Src
|
||||
000000012001a890 S V23
|
||||
000000012001a388 D _DYNAMIC
|
||||
000000012001a5f8 D _GLOBAL_OFFSET_TABLE_
|
||||
000000012001a848 G _IO_stdin_used
|
||||
000000012001a550 T _PROCEDURE_LINKAGE_TABLE_
|
||||
000000012001a530 d __CTOR_END__
|
||||
000000012001a528 d __CTOR_LIST__
|
||||
000000012001a540 d __DTOR_END__
|
||||
000000012001a538 d __DTOR_LIST__
|
||||
000000012001a384 r __FRAME_END__
|
||||
000000012001a548 d __JCR_END__
|
||||
000000012001a548 d __JCR_LIST__
|
||||
000000012001a860 A __bss_start
|
||||
000000012001a000 D __data_start
|
||||
0000000120008c50 t __do_global_ctors_aux
|
||||
00000001200008d0 t __do_global_dtors_aux
|
||||
000000012001a850 G __dso_handle
|
||||
000000012001a000 A __fini_array_end
|
||||
000000012001a000 A __fini_array_start
|
||||
000000012001a000 A __init_array_end
|
||||
000000012001a000 A __init_array_start
|
||||
0000000120008bb0 T __libc_csu_fini
|
||||
0000000120008b00 T __libc_csu_init
|
||||
0000000120000890 W __start
|
||||
000000012001a860 A _edata
|
||||
000000012001a9e0 A _end
|
||||
0000000120008cb0 T _fini
|
||||
0000000120000828 T _init
|
||||
0000000120000890 T _start
|
||||
00000001200049c4 T abe_matrix
|
||||
00000001200056b8 T arch_bail
|
||||
00000001200056e4 T arch_info
|
||||
0000000120006584 T arch_init
|
||||
00000001200057e0 T arch_parsecommandline
|
||||
0000000120005bf4 T arch_readdouble
|
||||
0000000120005ad0 T arch_readelemvector
|
||||
00000001200059ac T arch_readnodevector
|
||||
0000000120004530 T area_triangle
|
||||
00000001200051e8 T centroid
|
||||
000000012001a860 s completed.1
|
||||
000000012001a000 W data_start
|
||||
000000012001a948 S disp
|
||||
00000001200050bc T distance
|
||||
0000000120003c70 T element_matrices
|
||||
0000000120000970 t frame_dummy
|
||||
00000001200036f8 T get_Enu
|
||||
0000000120003820 T inv_J
|
||||
00000001200009c0 T main
|
||||
0000000120007a88 T mem_init
|
||||
00000001200054b8 T mv12x12
|
||||
000000012001a8c0 S nodekind
|
||||
000000012001a910 S nodekindf
|
||||
000000012001a8f0 S options
|
||||
000000012001a858 g p.0
|
||||
000000012001a8c8 S packfile
|
||||
0000000120004bc4 T phi0
|
||||
0000000120004cc4 T phi1
|
||||
0000000120004d98 T phi2
|
||||
00000001200052e8 T point2fault
|
||||
000000012001a870 S progname
|
||||
0000000120005cd8 T readpackfile
|
||||
000000012000360c T shape_ders
|
||||
0000000120004e84 T slip
|
||||
0000000120006604 T smvp
|
||||
00000001200070f8 T smvp_opt
|
||||
000000012001a880 S source_elms
|
||||
000000012001a8e0 S vel
|
||||
000000012000561c T vv12x12
|
||||
12
simulators/gem5/configs/boot/gcc.rcS
Normal file
12
simulators/gem5/configs/boot/gcc.rcS
Normal file
@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/gcc00/
|
||||
|
||||
/sbin/m5 checkpoint 0 0
|
||||
/sbin/m5 checkpoint 100000000 200000000
|
||||
|
||||
/sbin/m5 loadsymbol
|
||||
|
||||
/sbin/m5 resetstats
|
||||
./cc1 mdred.rtlanal.i
|
||||
/sbin/m5 exit
|
||||
12
simulators/gem5/configs/boot/gzip.rcS
Normal file
12
simulators/gem5/configs/boot/gzip.rcS
Normal file
@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/gzip00/
|
||||
|
||||
/sbin/m5 checkpoint 0 0
|
||||
/sbin/m5 checkpoint 100000000 200000000
|
||||
|
||||
/sbin/m5 loadsymbol
|
||||
|
||||
/sbin/m5 resetstats
|
||||
./gzip lgred.log 1
|
||||
/sbin/m5 exit
|
||||
268
simulators/gem5/configs/boot/gzip.symbol
Normal file
268
simulators/gem5/configs/boot/gzip.symbol
Normal file
@ -0,0 +1,268 @@
|
||||
0000000120022c08 D _DYNAMIC
|
||||
0000000120022fd0 D _GLOBAL_OFFSET_TABLE_
|
||||
0000000120023498 G _IO_stdin_used
|
||||
0000000120022dc0 T _PROCEDURE_LINKAGE_TABLE_
|
||||
0000000120022da0 d __CTOR_END__
|
||||
0000000120022d98 d __CTOR_LIST__
|
||||
0000000120022db0 d __DTOR_END__
|
||||
0000000120022da8 d __DTOR_LIST__
|
||||
0000000120022c04 r __FRAME_END__
|
||||
0000000120022db8 d __JCR_END__
|
||||
0000000120022db8 d __JCR_LIST__
|
||||
00000001200234f8 A __bss_start
|
||||
0000000120021030 D __data_start
|
||||
000000012000fbc0 t __do_global_ctors_aux
|
||||
00000001200012a0 t __do_global_dtors_aux
|
||||
00000001200234a0 G __dso_handle
|
||||
0000000120021030 A __fini_array_end
|
||||
0000000120021030 A __fini_array_start
|
||||
0000000120021030 A __init_array_end
|
||||
0000000120021030 A __init_array_start
|
||||
000000012000fb20 T __libc_csu_fini
|
||||
000000012000fa70 T __libc_csu_init
|
||||
0000000120001260 W __start
|
||||
00000001200234f8 A _edata
|
||||
0000000120073b10 A _end
|
||||
000000012000fc20 T _fini
|
||||
00000001200011f8 T _init
|
||||
0000000120001260 T _start
|
||||
0000000120004cf0 T abort_gzip
|
||||
000000012000de80 T add_envopt
|
||||
0000000120023550 S args
|
||||
0000000120023520 S ascii
|
||||
000000012002551c b base_dist
|
||||
00000001200254a8 b base_length
|
||||
0000000120023698 S bb
|
||||
00000001200234fc s bi_buf
|
||||
0000000120001ad0 T bi_init
|
||||
0000000120001b20 T bi_reverse
|
||||
0000000120023500 s bi_valid
|
||||
00000001200015d0 T bi_windup
|
||||
00000001200235b8 s bitbuf
|
||||
00000001200235e0 s bitbuf
|
||||
00000001200235c0 s bitcount
|
||||
0000000120023690 S bk
|
||||
0000000120024654 b bl_count
|
||||
0000000120021830 d bl_desc
|
||||
0000000120021858 d bl_order
|
||||
00000001200245b8 b bl_tree
|
||||
00000001200234ec G block_mode
|
||||
0000000120023610 S block_start
|
||||
00000001200235b4 s blocksize
|
||||
0000000120021540 d border
|
||||
0000000120009620 t build_tree
|
||||
0000000120023650 S bytes_in
|
||||
0000000120023668 S bytes_out
|
||||
0000000120004740 t check_ofname
|
||||
000000012000d5c0 T check_zipfile
|
||||
000000012000e540 T clear_bufs
|
||||
00000001200234f8 s completed.1
|
||||
0000000120023518 s compr_level
|
||||
00000001200092e0 t compress_block
|
||||
00000001200235a0 s compressed_len
|
||||
0000000120021030 d configuration_table
|
||||
000000012000e280 T copy
|
||||
00000001200017d0 T copy_block
|
||||
0000000120004ae0 t copy_stat
|
||||
0000000120021644 d cpdext
|
||||
0000000120021608 d cpdist
|
||||
000000012002158c d cplens
|
||||
00000001200215ca d cplext
|
||||
00000001200235f8 s crc
|
||||
00000001200234f0 g crc.0
|
||||
0000000120021870 D crc_32_tab
|
||||
0000000120002b90 t create_outfile
|
||||
0000000120008450 T ct_init
|
||||
0000000120008f60 T ct_tally
|
||||
000000012002ea20 B d_buf
|
||||
0000000120021808 d d_desc
|
||||
0000000120021030 W data_start
|
||||
00000001200234e8 G dbglvl
|
||||
00000001200234e4 G dbits
|
||||
0000000120008440 T debug_time
|
||||
000000012000a5e0 t decode
|
||||
000000012000ad50 t decode_c
|
||||
000000012000ab90 t decode_start
|
||||
0000000120023528 S decompress
|
||||
00000001200236c0 S decrypt
|
||||
0000000120002250 T deflate
|
||||
0000000120002770 t deflate_fast
|
||||
0000000120024f68 b depth
|
||||
000000012000ee70 T display_ratio
|
||||
00000001200252a5 b dist_code
|
||||
0000000120004c60 t do_exit
|
||||
0000000120003f00 t do_list
|
||||
0000000120023540 S do_lzw
|
||||
00000001200235c8 s done
|
||||
0000000120023fcc b dyn_dtree
|
||||
00000001200236d8 b dyn_ltree
|
||||
0000000120023678 S env
|
||||
000000012002350c s eofile
|
||||
000000012000e1c0 T error
|
||||
0000000120023548 S exit_code
|
||||
00000001200235f4 S ext_header
|
||||
0000000120021794 d extra_blbits
|
||||
000000012002171c d extra_dbits
|
||||
00000001200216a8 d extra_lbits
|
||||
00000001200236b8 S file_method
|
||||
000000012000f9c0 T file_read
|
||||
00000001200236b0 S file_type
|
||||
000000012000e580 T fill_inbuf
|
||||
0000000120002030 t fill_window
|
||||
00000001200234d8 g first_time.2
|
||||
000000012002358d s flag_bit
|
||||
0000000120025594 b flag_buf
|
||||
000000012002358c s flags
|
||||
0000000120008ba0 T flush_block
|
||||
000000012000e730 T flush_outbuf
|
||||
000000012000e860 T flush_window
|
||||
000000012002352c S force
|
||||
0000000120023640 S foreground
|
||||
0000000120001340 t frame_dummy
|
||||
000000012000a1a0 t gen_bitlen
|
||||
0000000120008a80 t gen_codes
|
||||
0000000120002dd0 t get_istat
|
||||
00000001200032c0 T get_method
|
||||
0000000120004d50 t get_suffix
|
||||
0000000120023618 S good_match
|
||||
000000012000ebf0 T gzipbasename
|
||||
00000001200236d0 S header_bytes
|
||||
0000000120024674 b heap
|
||||
0000000120023578 s heap_len
|
||||
000000012002357c s heap_max
|
||||
00000001200214b8 d help_msg.5
|
||||
0000000120004ee0 T huft_build
|
||||
0000000120005670 T huft_free
|
||||
00000001200236a0 S hufts
|
||||
00000001200235b0 s i.0
|
||||
0000000120023688 S ifd
|
||||
0000000120023658 S ifile_size
|
||||
000000012005eea8 B ifname
|
||||
000000012002356c s in_exit.4
|
||||
00000001200269e0 B inbuf
|
||||
0000000120006e00 T inflate
|
||||
0000000120006bf0 T inflate_block
|
||||
00000001200056d0 T inflate_codes
|
||||
00000001200062b0 T inflate_dynamic
|
||||
00000001200060f0 T inflate_fixed
|
||||
0000000120005e10 T inflate_stored
|
||||
0000000120008960 t init_block
|
||||
0000000120023684 S inptr
|
||||
00000001200235a8 s input_len
|
||||
0000000120023508 s ins_h
|
||||
0000000120023644 S insize
|
||||
000000012003ea20 B istat
|
||||
00000001200235c4 s j
|
||||
00000001200236c8 S key
|
||||
00000001200213f8 d known_suffixes.0
|
||||
00000001200217e0 d l_desc
|
||||
0000000120023584 s last_dist
|
||||
0000000120023588 s last_flags
|
||||
0000000120023580 s last_lit
|
||||
000000012002364c S last_member
|
||||
00000001200234e0 G lbits
|
||||
0000000120026910 b leaves
|
||||
00000001200251a5 b length_code
|
||||
00000001200234c8 G level
|
||||
0000000120021080 d license_msg
|
||||
0000000120023534 S list
|
||||
00000001200268a8 b lit_base
|
||||
00000001200267a8 b literal
|
||||
0000000120001b60 T lm_init
|
||||
0000000120001d90 T longest_match
|
||||
00000001200210f8 D longopts
|
||||
0000000120023510 s lookahead
|
||||
0000000120006ed0 T lzw
|
||||
0000000120007a80 T main
|
||||
0000000120003040 t make_ofname
|
||||
000000012000ec40 T make_simple_name
|
||||
000000012000c130 t make_table
|
||||
0000000120021680 D mask_bits
|
||||
0000000120023624 S match_start
|
||||
000000012002361c S max_chain_length
|
||||
0000000120023514 s max_lazy_match
|
||||
00000001200235d8 s max_len
|
||||
00000001200234c0 G maxbits
|
||||
00000001200234c4 G method
|
||||
0000000120021470 d methods.3
|
||||
0000000120023570 s msg_done
|
||||
0000000120004310 t name_too_long
|
||||
0000000120023608 S nice_match
|
||||
00000001200234b8 G no_name
|
||||
00000001200234bc G no_time
|
||||
0000000120023630 S ofd
|
||||
000000012003eaa8 B ofname
|
||||
0000000120023590 s opt_len
|
||||
00000001200235d0 s orig_len
|
||||
000000012005f2a8 B outbuf
|
||||
0000000120023648 S outcnt
|
||||
00000001200234a8 g p.0
|
||||
0000000120026978 b parents
|
||||
0000000120023680 S part_nb
|
||||
00000001200235dc s peek_bits
|
||||
00000001200235f0 S pkzip
|
||||
000000012003eea8 B prev
|
||||
000000012002360c S prev_length
|
||||
0000000120023628 S progname
|
||||
0000000120026594 b pt_len
|
||||
00000001200265a8 b pt_table
|
||||
000000012002353c S quiet
|
||||
00000001200080c0 T ran
|
||||
0000000120023600 S read_buf
|
||||
000000012000b8c0 t read_c_len
|
||||
000000012000ed50 T read_error
|
||||
000000012000b130 t read_pt_len
|
||||
000000012000d2a0 t read_tree
|
||||
0000000120023530 S recursive
|
||||
0000000120023568 S remove_ofname
|
||||
0000000120023660 S save_orig_name
|
||||
0000000120009d90 t scan_tree
|
||||
00000001200236a8 S seedi
|
||||
0000000120001390 T send_bits
|
||||
0000000120009f40 t send_tree
|
||||
0000000120009540 t set_file_type
|
||||
0000000120004420 t shorten_name
|
||||
0000000120007f90 T spec_compress
|
||||
0000000120073ac8 B spec_fd
|
||||
0000000120007800 T spec_getc
|
||||
0000000120006f70 T spec_init
|
||||
0000000120007f40 T spec_initbufs
|
||||
0000000120007430 T spec_load
|
||||
0000000120008350 T spec_putc
|
||||
0000000120007090 T spec_random_load
|
||||
0000000120007670 T spec_read
|
||||
00000001200081b0 T spec_reset
|
||||
0000000120008190 T spec_rewind
|
||||
0000000120008010 T spec_uncompress
|
||||
0000000120007930 T spec_ungetc
|
||||
0000000120008210 T spec_write
|
||||
0000000120024540 b static_dtree
|
||||
0000000120023598 s static_len
|
||||
00000001200240c0 b static_ltree
|
||||
000000012000eb20 T strlwr
|
||||
0000000120023620 S strstart
|
||||
00000001200235bc s subbitbuf
|
||||
0000000120021440 d suffixes.1
|
||||
0000000120023544 S test
|
||||
0000000120023638 S time_stamp
|
||||
0000000120023524 S to_stdout
|
||||
0000000120023558 S total_in
|
||||
0000000120023560 S total_out
|
||||
000000012000a510 T unlzh
|
||||
000000012000c5c0 T unlzw
|
||||
000000012000cde0 T unpack
|
||||
000000012000d7a0 T unzip
|
||||
000000012000e4c0 T updcrc
|
||||
00000001200235e8 s valid
|
||||
0000000120023538 S verbose
|
||||
000000012000ecd0 T warn
|
||||
0000000120063aa8 B window
|
||||
00000001200234b0 G window_size
|
||||
00000001200234d0 G work
|
||||
000000012000ea20 T write_buf
|
||||
000000012000ee00 T write_error
|
||||
000000012000e220 T xmalloc
|
||||
0000000120023670 S z_len
|
||||
0000000120073aa8 B z_suffix
|
||||
0000000120023504 s zfile
|
||||
000000012000ef80 T zip
|
||||
62
simulators/gem5/configs/boot/hack_back_ckpt.rcS
Normal file
62
simulators/gem5/configs/boot/hack_back_ckpt.rcS
Normal file
@ -0,0 +1,62 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# This is a tricky script to understand. When run in M5, it creates
|
||||
# a checkpoint after Linux boot up, but before any benchmarks have
|
||||
# been run. By playing around with environment variables, we can
|
||||
# detect whether the checkpoint has been taken.
|
||||
# - If the checkpoint hasn't been taken, the script allows M5 to checkpoint the system,
|
||||
# re-read this script into a new tmp file, and re-run it. On the
|
||||
# second execution of this script (checkpoint has been taken), the
|
||||
# environment variable is already set, so the script will exit the
|
||||
# simulation
|
||||
# - When we restore the simulation from a checkpoint, we can
|
||||
# specify a new script for M5 to execute in the full-system simulation,
|
||||
# and it will be executed as if a checkpoint had just been taken.
|
||||
#
|
||||
# Author:
|
||||
# Joel Hestness, hestness@cs.utexas.edu
|
||||
# while at AMD Research and Advanced Development Lab
|
||||
# Date:
|
||||
# 10/5/2010
|
||||
#
|
||||
|
||||
# Test if the RUNSCRIPT_VAR environment variable is already set
|
||||
if [ "${RUNSCRIPT_VAR+set}" != set ]
|
||||
then
|
||||
# Signal our future self that it's safe to continue
|
||||
export RUNSCRIPT_VAR=1
|
||||
else
|
||||
# We've already executed once, so we should exit
|
||||
/sbin/m5 exit
|
||||
fi
|
||||
|
||||
# Checkpoint the first execution
|
||||
echo "Checkpointing simulation..."
|
||||
/sbin/m5 checkpoint
|
||||
|
||||
# Test if we previously okayed ourselves to run this script
|
||||
if [ "$RUNSCRIPT_VAR" -eq 1 ]
|
||||
then
|
||||
|
||||
# Signal our future self not to recurse infinitely
|
||||
export RUNSCRIPT_VAR=2
|
||||
|
||||
# Read the script for the checkpoint restored execution
|
||||
echo "Loading new script..."
|
||||
/sbin/m5 readfile > /tmp/runscript
|
||||
chmod 755 /tmp/runscript
|
||||
|
||||
# Execute the new runscript
|
||||
if [ -s /tmp/runscript ]
|
||||
then
|
||||
exec /tmp/runscript
|
||||
else
|
||||
echo "Script not specified. Dropping into shell..."
|
||||
/bin/bash
|
||||
fi
|
||||
|
||||
fi
|
||||
|
||||
echo "Fell through script. Exiting..."
|
||||
/sbin/m5 exit
|
||||
1
simulators/gem5/configs/boot/halt.sh
Normal file
1
simulators/gem5/configs/boot/halt.sh
Normal file
@ -0,0 +1 @@
|
||||
m5 exit
|
||||
107
simulators/gem5/configs/boot/iscsi-client.rcS
Normal file
107
simulators/gem5/configs/boot/iscsi-client.rcS
Normal file
@ -0,0 +1,107 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
/sbin/ifconfig eth0 192.168.0.10 txqueuelen 1000
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
#echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "1" > /proc/sys/vm/dirty_writeback_centisecs
|
||||
echo "done."
|
||||
|
||||
cat > /etc/initiatorname.iscsi <<EOF
|
||||
InitiatorName=iqn.1987-05.10.0.168.192
|
||||
EOF
|
||||
|
||||
cat > /etc/iscsid.conf <<EOF
|
||||
node.active_cnx = 1
|
||||
node.startup = manual
|
||||
#node.session.auth.username = dima
|
||||
#node.session.auth.password = aloha
|
||||
node.session.timeo.replacement_timeout = 0
|
||||
node.session.err_timeo.abort_timeout = 10
|
||||
node.session.err_timeo.reset_timeout = 30
|
||||
node.session.iscsi.InitialR2T = No
|
||||
node.session.iscsi.ImmediateData = Yes
|
||||
node.session.iscsi.FirstBurstLength = 262144
|
||||
node.session.iscsi.MaxBurstLength = 16776192
|
||||
node.session.iscsi.DefaultTime2Wait = 0
|
||||
node.session.iscsi.DefaultTime2Retain = 0
|
||||
node.session.iscsi.MaxConnections = 0
|
||||
node.cnx[0].iscsi.HeaderDigest = None
|
||||
node.cnx[0].iscsi.DataDigest = None
|
||||
node.cnx[0].iscsi.MaxRecvDataSegmentLength = 65536
|
||||
#discovery.sendtargets.auth.authmethod = CHAP
|
||||
#discovery.sendtargets.auth.username = dima
|
||||
#discovery.sendtargets.auth.password = aloha
|
||||
EOF
|
||||
|
||||
#mount -t sysfs none /sys
|
||||
|
||||
echo "" > /var/log/iscsi.log
|
||||
chmod 0600 /var/log/iscsi.log
|
||||
chmod 0666 -R /var/db/iscsi
|
||||
|
||||
# Required for udev to activate/deactivate devices.
|
||||
echo "/sbin/hotplug" > /proc/sys/kernel/hotplug
|
||||
|
||||
/sbin/insmod /modules/scsi_transport_iscsi.ko
|
||||
/sbin/insmod /modules/iscsi_tcp.ko
|
||||
|
||||
echo "Starting iscsid..."
|
||||
/iscsi/iscsid -f &
|
||||
|
||||
sleep 1
|
||||
|
||||
echo "Waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo "Attaching target..."
|
||||
/iscsi/iscsiadm -m discovery -t st -p 192.168.0.1
|
||||
/iscsi/iscsiadm -m node -r a0c049 --login
|
||||
echo "done."
|
||||
|
||||
sleep 5
|
||||
|
||||
#PARAMS="-n 8 -s 8 -r .666 -c 50" # lisa default
|
||||
#PARAMS="-n 8 -s 5120 -r .666 -c 20" # very unstable
|
||||
#PARAMS="-n 8 -s 8 -r 0 -c 20" # very unstable
|
||||
#PARAMS="-n 8 -s 8 -r 1 -c 20" # stable 960 Mbps
|
||||
#PARAMS="-n 8 -s 1024 -r 1 -c 20" # very unstable
|
||||
#PARAMS="-n 16 -s 32 -r 1 -c 50" # stable ~1.5 Gbps
|
||||
#PARAMS="-n 50 -s 32 -r 1 -c 50" # stable ~1.5 Gbps
|
||||
PARAMS="-n 50 -s 8 -r .666 -c 50"
|
||||
COMMAND="/benchmarks/aio-bench $PARAMS -i 1000000 -C 50000 /dev/sda"
|
||||
|
||||
echo "Starting aio benchmark..."
|
||||
echo $COMMAND
|
||||
eval $COMMAND
|
||||
|
||||
echo "starting bash shell..."
|
||||
/bin/bash
|
||||
|
||||
echo -n "halting machine"
|
||||
m5 exit
|
||||
59
simulators/gem5/configs/boot/iscsi-server.rcS
Normal file
59
simulators/gem5/configs/boot/iscsi-server.rcS
Normal file
@ -0,0 +1,59 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
/sbin/ifconfig eth0 192.168.0.1 txqueuelen 1000
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "10" > /proc/sys/vm/dirty_writeback_centisecs
|
||||
echo "done."
|
||||
|
||||
# specific for iscsi-target
|
||||
MEM_SIZE=1048576
|
||||
echo ${MEM_SIZE} > /proc/sys/net/core/wmem_max
|
||||
echo ${MEM_SIZE} > /proc/sys/net/core/rmem_max
|
||||
echo ${MEM_SIZE} > /proc/sys/net/core/wmem_default
|
||||
echo ${MEM_SIZE} > /proc/sys/net/core/rmem_default
|
||||
echo "${MEM_SIZE} ${MEM_SIZE} ${MEM_SIZE}" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "${MEM_SIZE} ${MEM_SIZE} ${MEM_SIZE}" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "${MEM_SIZE} ${MEM_SIZE} ${MEM_SIZE}" > /proc/sys/net/ipv4/tcp_wmem
|
||||
|
||||
mke2fs -F /dev/sda
|
||||
|
||||
cat > /etc/ietd.conf <<EOF
|
||||
Target iqn.2005-05.1.0.168.192
|
||||
Lun 0 Sectors=8000000,Type=nullio
|
||||
EOF
|
||||
|
||||
/sbin/insmod /modules/iscsi_trgt.ko
|
||||
|
||||
echo -n "start enterprise target..."
|
||||
/iscsi/ietd -f &
|
||||
echo "done."
|
||||
|
||||
sleep 3
|
||||
|
||||
echo "notifying client..."
|
||||
echo "server ready" | netcat -c 192.168.0.10 8000
|
||||
echo "done"
|
||||
|
||||
echo "starting bash shell..."
|
||||
/bin/bash
|
||||
18
simulators/gem5/configs/boot/ls.rcS
Normal file
18
simulators/gem5/configs/boot/ls.rcS
Normal file
@ -0,0 +1,18 @@
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
cd bin
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
cd ../benchmarks
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
ls
|
||||
12
simulators/gem5/configs/boot/mcf.rcS
Normal file
12
simulators/gem5/configs/boot/mcf.rcS
Normal file
@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/mcf00/
|
||||
|
||||
/sbin/m5 checkpoint 0 0
|
||||
/sbin/m5 checkpoint 100000000 200000000
|
||||
|
||||
/sbin/m5 loadsymbol
|
||||
|
||||
/sbin/m5 resetstats
|
||||
/benchmarks/spec/mcf00/mcf mdred.in
|
||||
/sbin/m5 exit
|
||||
65
simulators/gem5/configs/boot/mcf.symbol
Normal file
65
simulators/gem5/configs/boot/mcf.symbol
Normal file
@ -0,0 +1,65 @@
|
||||
0000000120014350 D _DYNAMIC
|
||||
0000000120014608 D _GLOBAL_OFFSET_TABLE_
|
||||
0000000120014770 G _IO_stdin_used
|
||||
0000000120014518 T _PROCEDURE_LINKAGE_TABLE_
|
||||
00000001200144f8 d __CTOR_END__
|
||||
00000001200144f0 d __CTOR_LIST__
|
||||
0000000120014508 d __DTOR_END__
|
||||
0000000120014500 d __DTOR_LIST__
|
||||
000000012001434c r __FRAME_END__
|
||||
0000000120014510 d __JCR_END__
|
||||
0000000120014510 d __JCR_LIST__
|
||||
0000000120014790 A __bss_start
|
||||
0000000120014000 D __data_start
|
||||
00000001200034d0 t __do_global_ctors_aux
|
||||
0000000120000a40 t __do_global_dtors_aux
|
||||
0000000120014778 G __dso_handle
|
||||
0000000120014000 A __fini_array_end
|
||||
0000000120014000 A __fini_array_start
|
||||
0000000120014000 A __init_array_end
|
||||
0000000120014000 A __init_array_start
|
||||
0000000120003430 T __libc_csu_fini
|
||||
0000000120003380 T __libc_csu_init
|
||||
0000000120000a00 W __start
|
||||
0000000120014790 A _edata
|
||||
0000000120017c30 A _end
|
||||
0000000120003530 T _fini
|
||||
0000000120000998 T _init
|
||||
0000000120000a00 T _start
|
||||
00000001200147b0 b basket
|
||||
0000000120014798 s basket_size
|
||||
0000000120003320 T bea_compute_red_cost
|
||||
0000000120003340 T bea_is_dual_infeasible
|
||||
0000000120014790 s completed.1
|
||||
0000000120002410 T compute_red_cost
|
||||
0000000120014000 W data_start
|
||||
0000000120001480 T dual_feasible
|
||||
0000000120001090 T flow_cost
|
||||
00000001200011d0 T flow_org_cost
|
||||
0000000120000ae0 t frame_dummy
|
||||
00000001200015f0 T getfree
|
||||
0000000120000e30 T global_opt
|
||||
00000001200147a8 s group_pos
|
||||
0000000120014788 g initialize
|
||||
0000000120002420 T insert_new_arc
|
||||
0000000120000b30 T main
|
||||
00000001200179d0 B net
|
||||
00000001200147a0 s nr_group
|
||||
0000000120014780 g p.0
|
||||
0000000120016d48 b perm
|
||||
0000000120001d20 T price_out_impl
|
||||
0000000120003080 T primal_bea_mpp
|
||||
0000000120001310 T primal_feasible
|
||||
0000000120002a60 T primal_iminus
|
||||
0000000120002c00 T primal_net_simplex
|
||||
0000000120002510 T primal_start_artificial
|
||||
0000000120002ba0 T primal_update_flow
|
||||
00000001200016b0 T read_min
|
||||
0000000120001580 T refresh_neighbour_lists
|
||||
0000000120000fa0 T refresh_potential
|
||||
0000000120001c10 T replace_weaker_arc
|
||||
0000000120002310 T resize_prob
|
||||
0000000120002f30 T sort_basket
|
||||
00000001200021b0 T suspend_impl
|
||||
00000001200027e0 T update_tree
|
||||
0000000120002600 T write_circulations
|
||||
12
simulators/gem5/configs/boot/mesa.rcS
Normal file
12
simulators/gem5/configs/boot/mesa.rcS
Normal file
@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks/spec/mesa00/
|
||||
|
||||
/sbin/m5 checkpoint 0 0
|
||||
/sbin/m5 checkpoint 100000000 200000000
|
||||
|
||||
/sbin/m5 loadsymbol
|
||||
|
||||
/sbin/m5 resetstats
|
||||
/benchmarks/spec/mesa00/mesa -frames 1 -meshfile lgred.in
|
||||
/sbin/m5 exit
|
||||
1135
simulators/gem5/configs/boot/mesa.symbol
Normal file
1135
simulators/gem5/configs/boot/mesa.symbol
Normal file
File diff suppressed because it is too large
Load Diff
3
simulators/gem5/configs/boot/micro_ctx.rcS
Normal file
3
simulators/gem5/configs/boot/micro_ctx.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_ctx 2 4 8 16
|
||||
m5 exit
|
||||
|
||||
4
simulators/gem5/configs/boot/micro_memlat.rcS
Normal file
4
simulators/gem5/configs/boot/micro_memlat.rcS
Normal file
@ -0,0 +1,4 @@
|
||||
m5 checkpoint 1 999999999
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 64
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_memlat2mb.rcS
Normal file
3
simulators/gem5/configs/boot/micro_memlat2mb.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 2 64
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_memlat8.rcS
Normal file
3
simulators/gem5/configs/boot/micro_memlat8.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 128 8
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_memlat8mb.rcS
Normal file
3
simulators/gem5/configs/boot/micro_memlat8mb.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_8MB 8 64
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_stream.rcS
Normal file
3
simulators/gem5/configs/boot/micro_stream.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/simstream
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_streamcopy.rcS
Normal file
3
simulators/gem5/configs/boot/micro_streamcopy.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/simstreamcopy
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_streamscale.rcS
Normal file
3
simulators/gem5/configs/boot/micro_streamscale.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/simstreamscale
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_syscall.rcS
Normal file
3
simulators/gem5/configs/boot/micro_syscall.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_syscall read
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_tlblat.rcS
Normal file
3
simulators/gem5/configs/boot/micro_tlblat.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 20 8192
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_tlblat2.rcS
Normal file
3
simulators/gem5/configs/boot/micro_tlblat2.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 2 8192
|
||||
m5 exit
|
||||
|
||||
3
simulators/gem5/configs/boot/micro_tlblat3.rcS
Normal file
3
simulators/gem5/configs/boot/micro_tlblat3.rcS
Normal file
@ -0,0 +1,3 @@
|
||||
/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 20 8192
|
||||
m5 exit
|
||||
|
||||
6
simulators/gem5/configs/boot/mutex-test.rcS
Normal file
6
simulators/gem5/configs/boot/mutex-test.rcS
Normal file
@ -0,0 +1,6 @@
|
||||
#!/bin/sh
|
||||
|
||||
cd /benchmarks
|
||||
/sbin/m5 resetstats
|
||||
./pthread_mutex_test 4 10000
|
||||
/sbin/m5 exit
|
||||
48
simulators/gem5/configs/boot/nat-netperf-maerts-client.rcS
Normal file
48
simulators/gem5/configs/boot/nat-netperf-maerts-client.rcS
Normal file
@ -0,0 +1,48 @@
|
||||
#!/bin/sh
|
||||
SERVER=192.168.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "modifying route table..."
|
||||
route add default gw 10.0.0.1
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for natbox..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="TCP_MAERTS"
|
||||
SHORT_ARGS="-l -100k"
|
||||
LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
echo "netperf benchmark"
|
||||
echo $LONG
|
||||
/sbin/m5 resetstats
|
||||
/sbin/m5 dumpresetstats 200000000 2000000000
|
||||
/sbin/m5 checkpoint 200000000 2000000000
|
||||
eval $LONG
|
||||
/sbin/m5 exit
|
||||
32
simulators/gem5/configs/boot/nat-netperf-server.rcS
Normal file
32
simulators/gem5/configs/boot/nat-netperf-server.rcS
Normal file
@ -0,0 +1,32 @@
|
||||
#!/bin/sh
|
||||
SERVER=192.168.0.1
|
||||
CLIENT=10.0.0.2
|
||||
NATBOX=192.168.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $SERVER txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo "running netserver..."
|
||||
/benchmarks/netperf-bin/netserver
|
||||
|
||||
echo -n "signal natbox to begin..."
|
||||
sleep 5
|
||||
echo "server ready" | netcat -c $NATBOX 8000
|
||||
echo "done."
|
||||
|
||||
echo "starting bash..."
|
||||
exec /bin/bash
|
||||
50
simulators/gem5/configs/boot/nat-netperf-stream-client.rcS
Normal file
50
simulators/gem5/configs/boot/nat-netperf-stream-client.rcS
Normal file
@ -0,0 +1,50 @@
|
||||
#!/bin/sh
|
||||
SERVER=192.168.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo "modifying route table"
|
||||
route add default gw 10.0.0.1
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="TCP_STREAM"
|
||||
SHORT_ARGS="-l -100k"
|
||||
LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
echo "netperf benchmark"
|
||||
echo $LONG
|
||||
/sbin/m5 ivlb 1
|
||||
/sbin/m5 resetstats
|
||||
/sbin/m5 dumpresetstats 200000000 2000000000
|
||||
/sbin/m5 checkpoint 200000000 2000000000
|
||||
eval $LONG
|
||||
/sbin/m5 exit
|
||||
51
simulators/gem5/configs/boot/nat-spec-surge-client.rcS
Normal file
51
simulators/gem5/configs/boot/nat-spec-surge-client.rcS
Normal file
@ -0,0 +1,51 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
CLIENT=10.0.0.2
|
||||
SERVER=192.168.0.1
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo "changing route table..."
|
||||
route add default gw 10.0.0.1
|
||||
|
||||
echo "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "running surge client..."
|
||||
/bin/bash -c "cd /benchmarks/surge && ./spec-m5 1 20 1 $SERVER 5 40000 1000000000 1000"
|
||||
echo "done."
|
||||
|
||||
echo -n "halting machine"
|
||||
m5 exit
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
56
simulators/gem5/configs/boot/nat-spec-surge-server.rcS
Executable file
56
simulators/gem5/configs/boot/nat-spec-surge-server.rcS
Executable file
@ -0,0 +1,56 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
NATBOX=192.168.0.7
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 192.168.0.1 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:1 192.168.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:2 192.168.0.3 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:3 192.168.0.4 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:4 192.168.0.5 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "mounting file set..."
|
||||
mkdir -p /z/htdocs
|
||||
mount /dev/hdb1 /z/htdocs
|
||||
echo "done."
|
||||
|
||||
echo -n "starting httpd..."
|
||||
/benchmarks/apache2/bin/apachectl start
|
||||
sleep 2
|
||||
cat /benchmarks/apache2/logs/error_log
|
||||
echo "done."
|
||||
|
||||
echo "notifying natbox..."
|
||||
sleep 5
|
||||
echo "server ready" | netcat -c $NATBOX 8000
|
||||
echo "done"
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
53
simulators/gem5/configs/boot/natbox-netperf.rcS
Normal file
53
simulators/gem5/configs/boot/natbox-netperf.rcS
Normal file
@ -0,0 +1,53 @@
|
||||
#!/bin/sh
|
||||
EXTIF=192.168.0.2
|
||||
INTIF=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $EXTIF txqueuelen 1000
|
||||
ifconfig eth1 $INTIF txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "1" > /proc/sys/net/ipv4/ip_forward
|
||||
|
||||
echo "waiting for netserver..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo "setting up iptables..."
|
||||
IPTABLES=/sbin/iptables
|
||||
EXTIF=eth0
|
||||
INTIF=eth1
|
||||
|
||||
$IPTABLES -P INPUT ACCEPT
|
||||
$IPTABLES -F INPUT
|
||||
$IPTABLES -P OUTPUT ACCEPT
|
||||
$IPTABLES -F OUTPUT
|
||||
$IPTABLES -P FORWARD DROP
|
||||
$IPTABLES -F FORWARD
|
||||
$IPTABLES -t nat -F
|
||||
|
||||
$IPTABLES -A FORWARD -i $EXTIF -o $INTIF -m state --state ESTABLISHED,RELATED -j ACCEPT
|
||||
$IPTABLES -A FORWARD -i $INTIF -o $EXTIF -j ACCEPT
|
||||
$IPTABLES -A FORWARD -j LOG
|
||||
|
||||
$IPTABLES -t nat -A POSTROUTING -o $EXTIF -j MASQUERADE
|
||||
|
||||
echo "informing client..."
|
||||
sleep 5
|
||||
echo "server ready" | netcat -c $CLIENT 8000
|
||||
|
||||
echo "starting bash..."
|
||||
exec /bin/bash
|
||||
56
simulators/gem5/configs/boot/natbox-spec-surge.rcS
Normal file
56
simulators/gem5/configs/boot/natbox-spec-surge.rcS
Normal file
@ -0,0 +1,56 @@
|
||||
#!/bin/sh
|
||||
EXTIF=192.168.0.7
|
||||
INTIF=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $EXTIF txqueuelen 1000
|
||||
ifconfig eth1 $INTIF txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_vegas_cong_avoid
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/ip_forward
|
||||
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
|
||||
echo "waiting for netserver..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo "setting up iptables..."
|
||||
IPTABLES=/sbin/iptables
|
||||
EXTIF=eth0
|
||||
INTIF=eth1
|
||||
|
||||
$IPTABLES -P INPUT ACCEPT
|
||||
$IPTABLES -F INPUT
|
||||
$IPTABLES -P OUTPUT ACCEPT
|
||||
$IPTABLES -F OUTPUT
|
||||
$IPTABLES -P FORWARD DROP
|
||||
$IPTABLES -F FORWARD
|
||||
$IPTABLES -t nat -F
|
||||
|
||||
$IPTABLES -A FORWARD -i $EXTIF -o $INTIF -m state --state ESTABLISHED,RELATED -j ACCEPT
|
||||
$IPTABLES -A FORWARD -i $INTIF -o $EXTIF -j ACCEPT
|
||||
$IPTABLES -A FORWARD -j LOG
|
||||
|
||||
$IPTABLES -t nat -A POSTROUTING -o $EXTIF -j MASQUERADE
|
||||
|
||||
echo "informing client..."
|
||||
sleep 5
|
||||
echo "server ready" | netcat -c $CLIENT 8000
|
||||
|
||||
echo "starting bash..."
|
||||
exec /bin/bash
|
||||
57
simulators/gem5/configs/boot/netperf-maerts-client.rcS
Normal file
57
simulators/gem5/configs/boot/netperf-maerts-client.rcS
Normal file
@ -0,0 +1,57 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for server..."
|
||||
/usr/bin/netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="TCP_MAERTS"
|
||||
SHORT_ARGS="-l -100k"
|
||||
LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
NUMCLNTS=`/sbin/m5 initparam`
|
||||
[ "$NUMCLNTS" -eq "0" ] && NUMCLNTS=1
|
||||
|
||||
echo "netperf benchmark... starting $NUMCLNTS..."
|
||||
lcv=0
|
||||
|
||||
while [ "$lcv" -lt "$NUMCLNTS" ]
|
||||
do
|
||||
echo $LONG
|
||||
eval $LONG &
|
||||
((lcv += 1))
|
||||
done
|
||||
|
||||
ckpt=200000000
|
||||
((ckpt = ckpt * 12/3 + 600000000))
|
||||
|
||||
echo "configuring checkpointing at $ckpt..."
|
||||
/sbin/m5 checkpoint $ckpt 2000000000
|
||||
echo "done configuring checkpointing..."
|
||||
sleep 100000
|
||||
|
||||
45
simulators/gem5/configs/boot/netperf-rr.rcS
Normal file
45
simulators/gem5/configs/boot/netperf-rr.rcS
Normal file
@ -0,0 +1,45 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="TCP_RR"
|
||||
SHORT_ARGS="-l -1k"
|
||||
LONG_ARGS="-k10000,0 -K10000,0"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
echo "netperf benchmark"
|
||||
echo $LONG
|
||||
/sbin/m5 ivlb 1
|
||||
/sbin/m5 resetstats
|
||||
/sbin/m5 dumpresetstats 200000000 2000000000
|
||||
/sbin/m5 checkpoint 200000000 2000000000
|
||||
eval $LONG
|
||||
/sbin/m5 exit
|
||||
30
simulators/gem5/configs/boot/netperf-server.rcS
Normal file
30
simulators/gem5/configs/boot/netperf-server.rcS
Normal file
@ -0,0 +1,30 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $SERVER txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo "running netserver..."
|
||||
/benchmarks/netperf-bin/netserver
|
||||
|
||||
echo -n "signal client to begin..."
|
||||
sleep 1
|
||||
echo "server ready" | netcat -c $CLIENT 8000
|
||||
echo "done."
|
||||
|
||||
echo "starting bash..."
|
||||
exec /bin/bash
|
||||
45
simulators/gem5/configs/boot/netperf-stream-client.rcS
Normal file
45
simulators/gem5/configs/boot/netperf-stream-client.rcS
Normal file
@ -0,0 +1,45 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="TCP_STREAM"
|
||||
SHORT_ARGS="-l -100k"
|
||||
LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
echo "netperf benchmark"
|
||||
echo $LONG
|
||||
/sbin/m5 ivlb 1
|
||||
/sbin/m5 resetstats
|
||||
/sbin/m5 dumpresetstats 200000000 2000000000
|
||||
/sbin/m5 checkpoint 200000000 2000000000
|
||||
eval $LONG
|
||||
/sbin/m5 exit
|
||||
45
simulators/gem5/configs/boot/netperf-stream-nt-client.rcS
Normal file
45
simulators/gem5/configs/boot/netperf-stream-nt-client.rcS
Normal file
@ -0,0 +1,45 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="TCP_STREAM"
|
||||
SHORT_ARGS="-l -100k"
|
||||
LONG_ARGS="-- -m 65536 -M 65536 -s 262144 -S 262144"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
echo "netperf benchmark"
|
||||
echo $LONG
|
||||
/sbin/m5 ivlb 1
|
||||
/sbin/m5 resetstats
|
||||
/sbin/m5 dumpresetstats 200000000 2000000000
|
||||
/sbin/m5 checkpoint 200000000 2000000000
|
||||
eval $LONG
|
||||
/sbin/m5 exit
|
||||
45
simulators/gem5/configs/boot/netperf-stream-udp-client.rcS
Normal file
45
simulators/gem5/configs/boot/netperf-stream-udp-client.rcS
Normal file
@ -0,0 +1,45 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="UDP_STREAM"
|
||||
SHORT_ARGS="-l 2 -- -m 16384 -M 16384 -s 262144 -S 262144"
|
||||
#LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144"
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
LONG="$BINARY -H $SERVER -t $TEST $LONG_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo "netperf warmup"
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
#echo "netperf benchmark"
|
||||
#echo $LONG
|
||||
#/sbin/m5 ivlb 1
|
||||
#/sbin/m5 resetstats
|
||||
#/sbin/m5 dumpresetstats 200000000 2000000000
|
||||
#/sbin/m5 checkpoint 200000000 2000000000
|
||||
#eval $LONG
|
||||
/sbin/m5 exit
|
||||
22
simulators/gem5/configs/boot/netperf-stream-udp-local.rcS
Normal file
22
simulators/gem5/configs/boot/netperf-stream-udp-local.rcS
Normal file
@ -0,0 +1,22 @@
|
||||
#!/bin/sh
|
||||
SERVER=127.0.0.1
|
||||
CLIENT=127.0.0.1
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
|
||||
BINARY=/benchmarks/netperf-bin/netperf
|
||||
TEST="UDP_STREAM"
|
||||
SHORT_ARGS="-l 2 -- -m 4096"
|
||||
|
||||
echo "running netserver..."
|
||||
/benchmarks/netperf-bin/netserver
|
||||
|
||||
|
||||
SHORT="$BINARY -H $SERVER -t $TEST $SHORT_ARGS"
|
||||
|
||||
echo "starting test..."
|
||||
echo $SHORT
|
||||
eval $SHORT
|
||||
|
||||
/sbin/m5 exit
|
||||
59
simulators/gem5/configs/boot/nfs-client-dbench.rcS
Normal file
59
simulators/gem5/configs/boot/nfs-client-dbench.rcS
Normal file
@ -0,0 +1,59 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "10" > /proc/sys/vm/dirty_writeback_centisecs
|
||||
echo "done."
|
||||
|
||||
echo -n "starting nfs client..."
|
||||
/sbin/portmap &
|
||||
/sbin/lockd &
|
||||
echo "done."
|
||||
|
||||
echo -n "waiting for server..."
|
||||
/usr/bin/netcat -c -l -p 8000
|
||||
|
||||
echo -n "mounting remote share..."
|
||||
mkdir /nfs
|
||||
mount 10.0.0.1:/nfs /nfs
|
||||
echo "done."
|
||||
|
||||
cd /nfs
|
||||
|
||||
initparam=`m5 initparam`
|
||||
|
||||
if test X$initparam == X0; then
|
||||
/sbin/m5 checkpoint 100000000 2000000000
|
||||
dd if=/dev/zero of=foo bs=1024k count=512
|
||||
else
|
||||
/sbin/m5 checkpoint 1000000000 2000000000
|
||||
/benchmarks/dbench/dbench $initparam
|
||||
fi
|
||||
|
||||
/sbin/m5 exit
|
||||
49
simulators/gem5/configs/boot/nfs-client-nhfsstone.rcS
Executable file
49
simulators/gem5/configs/boot/nfs-client-nhfsstone.rcS
Executable file
@ -0,0 +1,49 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "starting nfs client..."
|
||||
/sbin/portmap &
|
||||
/sbin/lockd &
|
||||
echo "done."
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "mounting remote share..."
|
||||
mkdir /nfs
|
||||
mount 10.0.0.1:/nfs /nfs
|
||||
echo "done."
|
||||
|
||||
/sbin/m5 checkpoint 8000000000 2000000000
|
||||
/sbin/nhfsstone /nfs
|
||||
|
||||
/sbin/m5 exit
|
||||
48
simulators/gem5/configs/boot/nfs-client-smallb.rcS
Executable file
48
simulators/gem5/configs/boot/nfs-client-smallb.rcS
Executable file
@ -0,0 +1,48 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "starting nfs client..."
|
||||
/sbin/portmap &
|
||||
/sbin/lockd &
|
||||
echo "done."
|
||||
|
||||
echo -n "waiting for server..."
|
||||
/usr/bin/netcat -c -l -p 8000
|
||||
|
||||
echo -n "mounting remote share..."
|
||||
mkdir /nfs
|
||||
mount -o rsize=1460,wsize=1460 10.0.0.1:/nfs /nfs
|
||||
echo "done."
|
||||
|
||||
/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs
|
||||
|
||||
/sbin/m5 exit
|
||||
48
simulators/gem5/configs/boot/nfs-client-tcp-smallb.rcS
Executable file
48
simulators/gem5/configs/boot/nfs-client-tcp-smallb.rcS
Executable file
@ -0,0 +1,48 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "starting nfs client..."
|
||||
/sbin/portmap &
|
||||
/sbin/lockd &
|
||||
echo "done."
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "mounting remote share..."
|
||||
mkdir /nfs
|
||||
mount -o rsize=1460,wsize=1460,tcp 10.0.0.1:/nfs /nfs
|
||||
echo "done."
|
||||
|
||||
/usr/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs
|
||||
|
||||
/sbin/m5 exit
|
||||
48
simulators/gem5/configs/boot/nfs-client-tcp.rcS
Executable file
48
simulators/gem5/configs/boot/nfs-client-tcp.rcS
Executable file
@ -0,0 +1,48 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "starting nfs client..."
|
||||
/sbin/portmap &
|
||||
/sbin/lockd &
|
||||
echo "done."
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "mounting remote share..."
|
||||
mkdir /nfs
|
||||
mount -o tcp 10.0.0.1:/nfs /nfs
|
||||
echo "done."
|
||||
|
||||
/usr/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs
|
||||
|
||||
/sbin/m5 exit
|
||||
48
simulators/gem5/configs/boot/nfs-client.rcS
Executable file
48
simulators/gem5/configs/boot/nfs-client.rcS
Executable file
@ -0,0 +1,48 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "starting nfs client..."
|
||||
/sbin/portmap &
|
||||
/sbin/lockd &
|
||||
echo "done."
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "mounting remote share..."
|
||||
mkdir /nfs
|
||||
mount 10.0.0.1:/nfs /nfs
|
||||
echo "done."
|
||||
|
||||
/usr/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /nfs
|
||||
|
||||
/sbin/m5 exit
|
||||
66
simulators/gem5/configs/boot/nfs-server-nhfsstone.rcS
Executable file
66
simulators/gem5/configs/boot/nfs-server-nhfsstone.rcS
Executable file
@ -0,0 +1,66 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.1 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
#if [ ! -x /dev/sda ]
|
||||
#then
|
||||
# mknod /dev/sda b 8 0
|
||||
# mknod /dev/sda1 b 8 1
|
||||
#fi
|
||||
|
||||
/sbin/insmod /modules/scsi_debug.ko dev_size_mb=80
|
||||
|
||||
echo -n "creating partition and formatting..."
|
||||
/sbin/mke2fs -F /dev/sda
|
||||
mkdir /nfs
|
||||
/bin/mount /dev/sda /nfs
|
||||
chmod a+rwx /nfs
|
||||
echo "done."
|
||||
|
||||
echo "/nfs 10.0.0.0/255.0.0.0(rw,sync,no_root_squash)" > /etc/exports
|
||||
echo -n "starting nfs kernel server..."
|
||||
/sbin/portmap
|
||||
/sbin/lockd
|
||||
/sbin/statd
|
||||
/sbin/nfsd 8
|
||||
/sbin/mountd
|
||||
echo "done."
|
||||
|
||||
echo "Exporting shares..."
|
||||
/sbin/exportfs -r -v
|
||||
|
||||
echo -n "signal client to mount..."
|
||||
sleep 5
|
||||
echo "server ready" | netcat -c 10.0.0.2 8000
|
||||
echo "done."
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
68
simulators/gem5/configs/boot/nfs-server.rcS
Executable file
68
simulators/gem5/configs/boot/nfs-server.rcS
Executable file
@ -0,0 +1,68 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 10.0.0.1 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
#if [ ! -x /dev/sda ]
|
||||
#then
|
||||
# mknod /dev/sda b 8 0
|
||||
# mknod /dev/sda1 b 8 1
|
||||
#fi
|
||||
|
||||
/sbin/insmod /modules/scsi_debug.ko dev_size_mb=768
|
||||
|
||||
echo -n "creating partition and formatting..."
|
||||
#echo "1,767,L" > /tmp/sfdisk.run
|
||||
#/usr/sbin/sfdisk -uM --force /dev/sda < /tmp/sfdisk.run
|
||||
/sbin/mke2fs -F /dev/sda
|
||||
mkdir /nfs
|
||||
/bin/mount /dev/sda /nfs
|
||||
chmod a+rwx /nfs
|
||||
#/usr/sbin/sfdisk -uM -l /dev/sda
|
||||
echo "done."
|
||||
|
||||
echo "/nfs 10.0.0.0/255.0.0.0(rw,sync,no_root_squash)" > /etc/exports
|
||||
echo -n "starting nfs kernel server..."
|
||||
/sbin/portmap
|
||||
/sbin/lockd
|
||||
/sbin/statd
|
||||
/sbin/nfsd 15
|
||||
/sbin/mountd
|
||||
echo "done."
|
||||
|
||||
echo "Exporting shares..."
|
||||
/sbin/exportfs -r -v
|
||||
|
||||
echo -n "signal client to mount..."
|
||||
echo "server ready" | netcat -c 10.0.0.2 8000
|
||||
echo "done."
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
0
simulators/gem5/configs/boot/null.rcS
Normal file
0
simulators/gem5/configs/boot/null.rcS
Normal file
25
simulators/gem5/configs/boot/ping-client.rcS
Normal file
25
simulators/gem5/configs/boot/ping-client.rcS
Normal file
@ -0,0 +1,25 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $CLIENT txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
ping -c 5 $SERVER
|
||||
/sbin/m5 exit
|
||||
26
simulators/gem5/configs/boot/ping-server.rcS
Normal file
26
simulators/gem5/configs/boot/ping-server.rcS
Normal file
@ -0,0 +1,26 @@
|
||||
#!/bin/sh
|
||||
SERVER=10.0.0.1
|
||||
CLIENT=10.0.0.2
|
||||
|
||||
echo "setting up network..."
|
||||
ifconfig lo 127.0.0.1
|
||||
ifconfig eth0 $SERVER txqueuelen 1000
|
||||
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "5000000 5000000 5000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262143" > /proc/sys/net/core/rmem_max
|
||||
echo "262143" > /proc/sys/net/core/wmem_max
|
||||
echo "262143" > /proc/sys/net/core/rmem_default
|
||||
echo "262143" > /proc/sys/net/core/wmem_default
|
||||
echo "262143" > /proc/sys/net/core/optmem_max
|
||||
echo "100000" > /proc/sys/net/core/netdev_max_backlog
|
||||
|
||||
echo -n "signal client to begin..."
|
||||
echo "server ready" | netcat -c $CLIENT 8000
|
||||
echo "done."
|
||||
|
||||
echo "starting bash..."
|
||||
exec /bin/bash
|
||||
37
simulators/gem5/configs/boot/setup
Normal file
37
simulators/gem5/configs/boot/setup
Normal file
@ -0,0 +1,37 @@
|
||||
ifconfig eth1 mtu 9000 txqueuelen 1000 up
|
||||
|
||||
### IPV4 specific settings
|
||||
# turns TCP timestamp support off, default 1, reduces CPU use
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
|
||||
# turn SACK support off, default on
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
|
||||
# sets min/default/max TCP read buffer, default 4096 87380 174760
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
|
||||
# sets min/pressure/max TCP write buffer, default 4096 16384 131072
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
|
||||
# sets min/pressure/max TCP buffer space, default 31744 32256 32768
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
|
||||
### CORE settings (mostly for socket and UDP effect)
|
||||
# maximum receive socket buffer size, default 131071
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
|
||||
# maximum send socket buffer size, default 131071
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
|
||||
# default receive socket buffer size, default 65535
|
||||
echo "524287" > /proc/sys/net/core/rmem_default
|
||||
|
||||
# default send socket buffer size, default 65535
|
||||
echo "524287" > /proc/sys/net/core/wmem_default
|
||||
|
||||
# maximum amount of option memory buffers, default 10240
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
|
||||
# number of unprocessed input packets before kernel starts dropping them,
|
||||
# default 300
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
45
simulators/gem5/configs/boot/spec-surge-client.rcS
Normal file
45
simulators/gem5/configs/boot/spec-surge-client.rcS
Normal file
@ -0,0 +1,45 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 192.168.0.10 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "running surge client..."
|
||||
/bin/bash -c "cd /benchmarks/surge && ./spec-m5 1 20 1 192.168.0.1 5 40000 1000000000 1000"
|
||||
echo "done."
|
||||
|
||||
echo -n "halting machine"
|
||||
m5 exit
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
53
simulators/gem5/configs/boot/spec-surge-server.rcS
Executable file
53
simulators/gem5/configs/boot/spec-surge-server.rcS
Executable file
@ -0,0 +1,53 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 192.168.0.1 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:1 192.168.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:2 192.168.0.3 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:3 192.168.0.4 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:4 192.168.0.5 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "mounting file set..."
|
||||
mkdir -p /z/htdocs
|
||||
mount /dev/hdb1 /z/htdocs
|
||||
echo "done."
|
||||
|
||||
echo -n "starting httpd..."
|
||||
/usr/sbin/apache2 -f /etc/apache2/httpd.conf -k start
|
||||
sleep 2
|
||||
cat /usr/share/apache2/logs/error_log
|
||||
echo "done."
|
||||
|
||||
echo "notifying client..."
|
||||
echo "server ready" | netcat -c 192.168.0.10 8000
|
||||
echo "done"
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
44
simulators/gem5/configs/boot/surge-client.rcS
Executable file
44
simulators/gem5/configs/boot/surge-client.rcS
Executable file
@ -0,0 +1,44 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 192.168.0.10 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo "waiting for server..."
|
||||
netcat -c -l -p 8000
|
||||
|
||||
echo -n "running surge client..."
|
||||
/bin/bash -c "cd /benchmarks/specsurge && ./Surge 2 100 1 192.168.0.1 5"
|
||||
echo "done."
|
||||
|
||||
echo -n "halting machine"
|
||||
m5 exit
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
52
simulators/gem5/configs/boot/surge-server.rcS
Executable file
52
simulators/gem5/configs/boot/surge-server.rcS
Executable file
@ -0,0 +1,52 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# /etc/init.d/rcS
|
||||
#
|
||||
|
||||
|
||||
echo -n "mounting swap..."
|
||||
/sbin/swapon /dev/hdc
|
||||
echo "done."
|
||||
|
||||
echo -n "setting up network..."
|
||||
/sbin/ifconfig eth0 192.168.0.1 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:1 192.168.0.2 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:2 192.168.0.3 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:3 192.168.0.4 txqueuelen 1000
|
||||
/sbin/ifconfig eth0:4 192.168.0.5 txqueuelen 1000
|
||||
/sbin/ifconfig lo 127.0.0.1
|
||||
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_recycle
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_tw_reuse
|
||||
echo "1" > /proc/sys/net/ipv4/tcp_window_scaling
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_timestamps
|
||||
echo "0" > /proc/sys/net/ipv4/tcp_sack
|
||||
echo "15" > /proc/sys/net/ipv4/tcp_fin_timeout
|
||||
echo "16384" > /proc/sys/net/ipv4/tcp_max_syn_backlog
|
||||
echo "262144" > /proc/sys/net/ipv4/ip_conntrack_max
|
||||
echo "1024 65535" > /proc/sys/net/ipv4/ip_local_port_range
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_rmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_wmem
|
||||
echo "10000000 10000000 10000000" > /proc/sys/net/ipv4/tcp_mem
|
||||
echo "524287" > /proc/sys/net/core/rmem_max
|
||||
echo "524287" > /proc/sys/net/core/wmem_max
|
||||
echo "524287" > /proc/sys/net/core/optmem_max
|
||||
echo "300000" > /proc/sys/net/core/netdev_max_backlog
|
||||
echo "131072" > /proc/sys/fs/file-max
|
||||
echo "done."
|
||||
|
||||
echo -n "mounting file set..."
|
||||
mkdir -p /z/htdocs
|
||||
mount /dev/hdb1 /z/htdocs
|
||||
echo "done."
|
||||
|
||||
echo -n "starting httpd..."
|
||||
/usr/sbin/apache2 -f /etc/apache2/httpd.conf -k start
|
||||
sleep 2
|
||||
cat /usr/share/apache2/logs/error_log
|
||||
echo "done."
|
||||
|
||||
echo "server ready" | netcat -c 192.168.10 8000
|
||||
|
||||
echo -n "starting bash shell..."
|
||||
/bin/bash
|
||||
126
simulators/gem5/configs/common/Benchmarks.py
Normal file
126
simulators/gem5/configs/common/Benchmarks.py
Normal file
@ -0,0 +1,126 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
from SysPaths import script, disk, binary
|
||||
from os import environ as env
|
||||
from m5.defines import buildEnv
|
||||
|
||||
class SysConfig:
|
||||
def __init__(self, script=None, mem=None, disk=None):
|
||||
self.scriptname = script
|
||||
self.diskname = disk
|
||||
self.memsize = mem
|
||||
|
||||
def script(self):
|
||||
if self.scriptname:
|
||||
return script(self.scriptname)
|
||||
else:
|
||||
return ''
|
||||
|
||||
def mem(self):
|
||||
if self.memsize:
|
||||
return self.memsize
|
||||
else:
|
||||
return '128MB'
|
||||
|
||||
def disk(self):
|
||||
if self.diskname:
|
||||
return disk(self.diskname)
|
||||
elif buildEnv['TARGET_ISA'] == 'alpha':
|
||||
return env.get('LINUX_IMAGE', disk('linux-latest.img'))
|
||||
elif buildEnv['TARGET_ISA'] == 'x86':
|
||||
return env.get('LINUX_IMAGE', disk('x86root.img'))
|
||||
elif buildEnv['TARGET_ISA'] == 'arm':
|
||||
return env.get('LINUX_IMAGE', disk('linux-arm-ael.img'))
|
||||
else:
|
||||
print "Don't know what default disk image to use for %s ISA" % \
|
||||
buildEnv['TARGET_ISA']
|
||||
exit(1)
|
||||
|
||||
# Benchmarks are defined as a key in a dict which is a list of SysConfigs
|
||||
# The first defined machine is the test system, the others are driving systems
|
||||
|
||||
Benchmarks = {
|
||||
'PovrayBench': [SysConfig('povray-bench.rcS', '512MB', 'povray.img')],
|
||||
'PovrayAutumn': [SysConfig('povray-autumn.rcS', '512MB', 'povray.img')],
|
||||
|
||||
'NetperfStream': [SysConfig('netperf-stream-client.rcS'),
|
||||
SysConfig('netperf-server.rcS')],
|
||||
'NetperfStreamUdp': [SysConfig('netperf-stream-udp-client.rcS'),
|
||||
SysConfig('netperf-server.rcS')],
|
||||
'NetperfUdpLocal': [SysConfig('netperf-stream-udp-local.rcS')],
|
||||
'NetperfStreamNT': [SysConfig('netperf-stream-nt-client.rcS'),
|
||||
SysConfig('netperf-server.rcS')],
|
||||
'NetperfMaerts': [SysConfig('netperf-maerts-client.rcS'),
|
||||
SysConfig('netperf-server.rcS')],
|
||||
'SurgeStandard': [SysConfig('surge-server.rcS', '512MB'),
|
||||
SysConfig('surge-client.rcS', '256MB')],
|
||||
'SurgeSpecweb': [SysConfig('spec-surge-server.rcS', '512MB'),
|
||||
SysConfig('spec-surge-client.rcS', '256MB')],
|
||||
'Nhfsstone': [SysConfig('nfs-server-nhfsstone.rcS', '512MB'),
|
||||
SysConfig('nfs-client-nhfsstone.rcS')],
|
||||
'Nfs': [SysConfig('nfs-server.rcS', '900MB'),
|
||||
SysConfig('nfs-client-dbench.rcS')],
|
||||
'NfsTcp': [SysConfig('nfs-server.rcS', '900MB'),
|
||||
SysConfig('nfs-client-tcp.rcS')],
|
||||
'IScsiInitiator': [SysConfig('iscsi-client.rcS', '512MB'),
|
||||
SysConfig('iscsi-server.rcS', '512MB')],
|
||||
'IScsiTarget': [SysConfig('iscsi-server.rcS', '512MB'),
|
||||
SysConfig('iscsi-client.rcS', '512MB')],
|
||||
'Validation': [SysConfig('iscsi-server.rcS', '512MB'),
|
||||
SysConfig('iscsi-client.rcS', '512MB')],
|
||||
'Ping': [SysConfig('ping-server.rcS',),
|
||||
SysConfig('ping-client.rcS')],
|
||||
|
||||
'ValAccDelay': [SysConfig('devtime.rcS', '512MB')],
|
||||
'ValAccDelay2': [SysConfig('devtimewmr.rcS', '512MB')],
|
||||
'ValMemLat': [SysConfig('micro_memlat.rcS', '512MB')],
|
||||
'ValMemLat2MB': [SysConfig('micro_memlat2mb.rcS', '512MB')],
|
||||
'ValMemLat8MB': [SysConfig('micro_memlat8mb.rcS', '512MB')],
|
||||
'ValMemLat': [SysConfig('micro_memlat8.rcS', '512MB')],
|
||||
'ValTlbLat': [SysConfig('micro_tlblat.rcS', '512MB')],
|
||||
'ValSysLat': [SysConfig('micro_syscall.rcS', '512MB')],
|
||||
'ValCtxLat': [SysConfig('micro_ctx.rcS', '512MB')],
|
||||
'ValStream': [SysConfig('micro_stream.rcS', '512MB')],
|
||||
'ValStreamScale': [SysConfig('micro_streamscale.rcS', '512MB')],
|
||||
'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
|
||||
|
||||
'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
|
||||
'ArmAndroid-GB': [SysConfig('null.rcS', '256MB',
|
||||
'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img')],
|
||||
'bbench-gb': [SysConfig('bbench-gb.rcS', '256MB',
|
||||
'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img')],
|
||||
'ArmAndroid-ICS': [SysConfig('null.rcS', '256MB',
|
||||
'ARMv7a-ICS-Android.SMP.nolock.clean.img')],
|
||||
'bbench-ics': [SysConfig('bbench-ics.rcS', '256MB',
|
||||
'ARMv7a-ICS-Android.SMP.nolock.img')]
|
||||
}
|
||||
|
||||
benchs = Benchmarks.keys()
|
||||
benchs.sort()
|
||||
DefinedBenchmarks = ", ".join(benchs)
|
||||
79
simulators/gem5/configs/common/CacheConfig.py
Normal file
79
simulators/gem5/configs/common/CacheConfig.py
Normal file
@ -0,0 +1,79 @@
|
||||
# Copyright (c) 2010 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Lisa Hsu
|
||||
|
||||
# Configure the M5 cache hierarchy config in one place
|
||||
#
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from Caches import *
|
||||
from O3_ARM_v7a import *
|
||||
|
||||
def config_cache(options, system):
|
||||
if options.l2cache:
|
||||
if options.cpu_type == "arm_detailed":
|
||||
system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
|
||||
block_size=options.cacheline_size)
|
||||
else:
|
||||
system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
|
||||
block_size=options.cacheline_size)
|
||||
|
||||
system.tol2bus = CoherentBus()
|
||||
system.l2.cpu_side = system.tol2bus.master
|
||||
system.l2.mem_side = system.membus.slave
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
if options.caches:
|
||||
if options.cpu_type == "arm_detailed":
|
||||
icache = O3_ARM_v7a_ICache(size = options.l1i_size,
|
||||
assoc = options.l1i_assoc,
|
||||
block_size=options.cacheline_size)
|
||||
dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
block_size=options.cacheline_size)
|
||||
else:
|
||||
icache = L1Cache(size = options.l1i_size,
|
||||
assoc = options.l1i_assoc,
|
||||
block_size=options.cacheline_size)
|
||||
dcache = L1Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
block_size=options.cacheline_size)
|
||||
|
||||
if buildEnv['TARGET_ISA'] == 'x86':
|
||||
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
|
||||
PageTableWalkerCache(),
|
||||
PageTableWalkerCache())
|
||||
else:
|
||||
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
|
||||
system.cpu[i].createInterruptController()
|
||||
if options.l2cache:
|
||||
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
|
||||
else:
|
||||
system.cpu[i].connectAllPorts(system.membus)
|
||||
|
||||
return system
|
||||
63
simulators/gem5/configs/common/Caches.py
Normal file
63
simulators/gem5/configs/common/Caches.py
Normal file
@ -0,0 +1,63 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Lisa Hsu
|
||||
|
||||
from m5.objects import *
|
||||
|
||||
class L1Cache(BaseCache):
|
||||
assoc = 2
|
||||
block_size = 64
|
||||
latency = '1ns'
|
||||
mshrs = 10
|
||||
tgts_per_mshr = 20
|
||||
is_top_level = True
|
||||
|
||||
class L2Cache(BaseCache):
|
||||
assoc = 8
|
||||
block_size = 64
|
||||
latency = '10ns'
|
||||
mshrs = 20
|
||||
tgts_per_mshr = 12
|
||||
|
||||
class PageTableWalkerCache(BaseCache):
|
||||
assoc = 2
|
||||
block_size = 64
|
||||
latency = '1ns'
|
||||
mshrs = 10
|
||||
size = '1kB'
|
||||
tgts_per_mshr = 12
|
||||
is_top_level = True
|
||||
|
||||
class IOCache(BaseCache):
|
||||
assoc = 8
|
||||
block_size = 64
|
||||
latency = '10ns'
|
||||
mshrs = 20
|
||||
size = '1kB'
|
||||
tgts_per_mshr = 12
|
||||
forward_snoops = False
|
||||
is_top_level = True
|
||||
561
simulators/gem5/configs/common/FSConfig.py
Normal file
561
simulators/gem5/configs/common/FSConfig.py
Normal file
@ -0,0 +1,561 @@
|
||||
# Copyright (c) 2010-2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
|
||||
# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Kevin Lim
|
||||
|
||||
from m5.objects import *
|
||||
from Benchmarks import *
|
||||
from m5.util import convert
|
||||
|
||||
class CowIdeDisk(IdeDisk):
|
||||
image = CowDiskImage(child=RawDiskImage(read_only=True),
|
||||
read_only=False)
|
||||
|
||||
def childImage(self, ci):
|
||||
self.image.child.image_file = ci
|
||||
|
||||
class MemBus(CoherentBus):
|
||||
badaddr_responder = BadAddr()
|
||||
default = Self.badaddr_responder.pio
|
||||
|
||||
|
||||
def makeLinuxAlphaSystem(mem_mode, mdesc = None):
|
||||
IO_address_space_base = 0x80000000000
|
||||
class BaseTsunami(Tsunami):
|
||||
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
|
||||
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
|
||||
pci_func=0, pci_dev=0, pci_bus=0)
|
||||
|
||||
self = LinuxAlphaSystem()
|
||||
if not mdesc:
|
||||
# generic system
|
||||
mdesc = SysConfig()
|
||||
self.readfile = mdesc.script()
|
||||
self.iobus = NoncoherentBus()
|
||||
self.membus = MemBus()
|
||||
# By default the bridge responds to all addresses above the I/O
|
||||
# base address (including the PCI config space)
|
||||
self.bridge = Bridge(delay='50ns', nack_delay='4ns',
|
||||
ranges = [AddrRange(IO_address_space_base, Addr.max)])
|
||||
self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
|
||||
self.bridge.master = self.iobus.slave
|
||||
self.bridge.slave = self.membus.master
|
||||
self.physmem.port = self.membus.master
|
||||
self.disk0 = CowIdeDisk(driveID='master')
|
||||
self.disk2 = CowIdeDisk(driveID='master')
|
||||
self.disk0.childImage(mdesc.disk())
|
||||
self.disk2.childImage(disk('linux-bigswap2.img'))
|
||||
self.tsunami = BaseTsunami()
|
||||
self.tsunami.attachIO(self.iobus)
|
||||
self.tsunami.ide.pio = self.iobus.master
|
||||
self.tsunami.ide.config = self.iobus.master
|
||||
self.tsunami.ide.dma = self.iobus.slave
|
||||
self.tsunami.ethernet.pio = self.iobus.master
|
||||
self.tsunami.ethernet.config = self.iobus.master
|
||||
self.tsunami.ethernet.dma = self.iobus.slave
|
||||
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
|
||||
read_only = True))
|
||||
self.intrctrl = IntrControl()
|
||||
self.mem_mode = mem_mode
|
||||
self.terminal = Terminal()
|
||||
self.kernel = binary('vmlinux')
|
||||
self.pal = binary('ts_osfpal')
|
||||
self.console = binary('console')
|
||||
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
|
||||
|
||||
self.system_port = self.membus.slave
|
||||
|
||||
return self
|
||||
|
||||
def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
|
||||
class BaseTsunami(Tsunami):
|
||||
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
|
||||
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
|
||||
pci_func=0, pci_dev=0, pci_bus=0)
|
||||
|
||||
physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
|
||||
self = LinuxAlphaSystem(physmem = physmem)
|
||||
if not mdesc:
|
||||
# generic system
|
||||
mdesc = SysConfig()
|
||||
self.readfile = mdesc.script()
|
||||
|
||||
# Create pio bus to connect all device pio ports to rubymem's pio port
|
||||
self.piobus = NoncoherentBus()
|
||||
|
||||
#
|
||||
# Pio functional accesses from devices need direct access to memory
|
||||
# RubyPort currently does support functional accesses. Therefore provide
|
||||
# the piobus a direct connection to physical memory
|
||||
#
|
||||
self.piobus.master = physmem.port
|
||||
|
||||
self.disk0 = CowIdeDisk(driveID='master')
|
||||
self.disk2 = CowIdeDisk(driveID='master')
|
||||
self.disk0.childImage(mdesc.disk())
|
||||
self.disk2.childImage(disk('linux-bigswap2.img'))
|
||||
self.tsunami = BaseTsunami()
|
||||
self.tsunami.attachIO(self.piobus)
|
||||
self.tsunami.ide.pio = self.piobus.master
|
||||
self.tsunami.ide.config = self.piobus.master
|
||||
self.tsunami.ethernet.pio = self.piobus.master
|
||||
self.tsunami.ethernet.config = self.piobus.master
|
||||
|
||||
#
|
||||
# Store the dma devices for later connection to dma ruby ports.
|
||||
# Append an underscore to dma_devices to avoid the SimObjectVector check.
|
||||
#
|
||||
self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
|
||||
|
||||
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
|
||||
read_only = True))
|
||||
self.intrctrl = IntrControl()
|
||||
self.mem_mode = mem_mode
|
||||
self.terminal = Terminal()
|
||||
self.kernel = binary('vmlinux')
|
||||
self.pal = binary('ts_osfpal')
|
||||
self.console = binary('console')
|
||||
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
|
||||
|
||||
return self
|
||||
|
||||
def makeSparcSystem(mem_mode, mdesc = None):
|
||||
# Constants from iob.cc and uart8250.cc
|
||||
iob_man_addr = 0x9800000000
|
||||
uart_pio_size = 8
|
||||
|
||||
class CowMmDisk(MmDisk):
|
||||
image = CowDiskImage(child=RawDiskImage(read_only=True),
|
||||
read_only=False)
|
||||
|
||||
def childImage(self, ci):
|
||||
self.image.child.image_file = ci
|
||||
|
||||
self = SparcSystem()
|
||||
if not mdesc:
|
||||
# generic system
|
||||
mdesc = SysConfig()
|
||||
self.readfile = mdesc.script()
|
||||
self.iobus = NoncoherentBus()
|
||||
self.membus = MemBus()
|
||||
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
|
||||
self.t1000 = T1000()
|
||||
self.t1000.attachOnChipIO(self.membus)
|
||||
self.t1000.attachIO(self.iobus)
|
||||
self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
|
||||
zero = True)
|
||||
self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
|
||||
zero = True)
|
||||
self.bridge.master = self.iobus.slave
|
||||
self.bridge.slave = self.membus.master
|
||||
self.physmem.port = self.membus.master
|
||||
self.physmem2.port = self.membus.master
|
||||
self.rom.port = self.membus.master
|
||||
self.nvram.port = self.membus.master
|
||||
self.hypervisor_desc.port = self.membus.master
|
||||
self.partition_desc.port = self.membus.master
|
||||
self.intrctrl = IntrControl()
|
||||
self.disk0 = CowMmDisk()
|
||||
self.disk0.childImage(disk('disk.s10hw2'))
|
||||
self.disk0.pio = self.iobus.master
|
||||
|
||||
# The puart0 and hvuart are placed on the IO bus, so create ranges
|
||||
# for them. The remaining IO range is rather fragmented, so poke
|
||||
# holes for the iob and partition descriptors etc.
|
||||
self.bridge.ranges = \
|
||||
[
|
||||
AddrRange(self.t1000.puart0.pio_addr,
|
||||
self.t1000.puart0.pio_addr + uart_pio_size - 1),
|
||||
AddrRange(self.disk0.pio_addr,
|
||||
self.t1000.fake_jbi.pio_addr +
|
||||
self.t1000.fake_jbi.pio_size - 1),
|
||||
AddrRange(self.t1000.fake_clk.pio_addr,
|
||||
iob_man_addr - 1),
|
||||
AddrRange(self.t1000.fake_l2_1.pio_addr,
|
||||
self.t1000.fake_ssi.pio_addr +
|
||||
self.t1000.fake_ssi.pio_size - 1),
|
||||
AddrRange(self.t1000.hvuart.pio_addr,
|
||||
self.t1000.hvuart.pio_addr + uart_pio_size - 1)
|
||||
]
|
||||
self.reset_bin = binary('reset_new.bin')
|
||||
self.hypervisor_bin = binary('q_new.bin')
|
||||
self.openboot_bin = binary('openboot_new.bin')
|
||||
self.nvram_bin = binary('nvram1')
|
||||
self.hypervisor_desc_bin = binary('1up-hv.bin')
|
||||
self.partition_desc_bin = binary('1up-md.bin')
|
||||
|
||||
self.system_port = self.membus.slave
|
||||
|
||||
return self
|
||||
|
||||
def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
|
||||
assert machine_type
|
||||
|
||||
if bare_metal:
|
||||
self = ArmSystem()
|
||||
else:
|
||||
self = LinuxArmSystem()
|
||||
|
||||
if not mdesc:
|
||||
# generic system
|
||||
mdesc = SysConfig()
|
||||
|
||||
self.readfile = mdesc.script()
|
||||
self.iobus = NoncoherentBus()
|
||||
self.membus = MemBus()
|
||||
self.membus.badaddr_responder.warn_access = "warn"
|
||||
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
|
||||
self.bridge.master = self.iobus.slave
|
||||
self.bridge.slave = self.membus.master
|
||||
|
||||
self.mem_mode = mem_mode
|
||||
|
||||
if machine_type == "RealView_PBX":
|
||||
self.realview = RealViewPBX()
|
||||
elif machine_type == "RealView_EB":
|
||||
self.realview = RealViewEB()
|
||||
elif machine_type == "VExpress_ELT":
|
||||
self.realview = VExpress_ELT()
|
||||
elif machine_type == "VExpress_EMM":
|
||||
self.realview = VExpress_EMM()
|
||||
self.load_addr_mask = 0xffffffff
|
||||
else:
|
||||
print "Unknown Machine Type"
|
||||
sys.exit(1)
|
||||
|
||||
self.cf0 = CowIdeDisk(driveID='master')
|
||||
self.cf0.childImage(mdesc.disk())
|
||||
# default to an IDE controller rather than a CF one
|
||||
# assuming we've got one
|
||||
try:
|
||||
self.realview.ide.disks = [self.cf0]
|
||||
except:
|
||||
self.realview.cf_ctrl.disks = [self.cf0]
|
||||
|
||||
if bare_metal:
|
||||
# EOT character on UART will end the simulation
|
||||
self.realview.uart.end_on_eot = True
|
||||
self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
|
||||
zero = True)
|
||||
else:
|
||||
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
|
||||
self.machine_type = machine_type
|
||||
if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
|
||||
print "The currently selected ARM platforms doesn't support"
|
||||
print " the amount of DRAM you've selected. Please try"
|
||||
print " another platform"
|
||||
sys.exit(1)
|
||||
|
||||
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
|
||||
'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
|
||||
|
||||
self.physmem = SimpleMemory(range =
|
||||
AddrRange(self.realview.mem_start_addr,
|
||||
size = mdesc.mem()),
|
||||
conf_table_reported = True)
|
||||
self.realview.setupBootLoader(self.membus, self, binary)
|
||||
self.gic_cpu_addr = self.realview.gic.cpu_addr
|
||||
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
|
||||
|
||||
if mdesc.disk().lower().count('android'):
|
||||
boot_flags += " init=/init "
|
||||
self.boot_osflags = boot_flags
|
||||
|
||||
self.physmem.port = self.membus.master
|
||||
self.realview.attachOnChipIO(self.membus, self.bridge)
|
||||
self.realview.attachIO(self.iobus)
|
||||
self.intrctrl = IntrControl()
|
||||
self.terminal = Terminal()
|
||||
self.vncserver = VncServer()
|
||||
|
||||
self.system_port = self.membus.slave
|
||||
|
||||
return self
|
||||
|
||||
|
||||
def makeLinuxMipsSystem(mem_mode, mdesc = None):
|
||||
class BaseMalta(Malta):
|
||||
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
|
||||
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
|
||||
pci_func=0, pci_dev=0, pci_bus=0)
|
||||
|
||||
self = LinuxMipsSystem()
|
||||
if not mdesc:
|
||||
# generic system
|
||||
mdesc = SysConfig()
|
||||
self.readfile = mdesc.script()
|
||||
self.iobus = NoncoherentBus()
|
||||
self.membus = MemBus()
|
||||
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
|
||||
self.physmem = SimpleMemory(range = AddrRange('1GB'))
|
||||
self.bridge.master = self.iobus.slave
|
||||
self.bridge.slave = self.membus.master
|
||||
self.physmem.port = self.membus.master
|
||||
self.disk0 = CowIdeDisk(driveID='master')
|
||||
self.disk2 = CowIdeDisk(driveID='master')
|
||||
self.disk0.childImage(mdesc.disk())
|
||||
self.disk2.childImage(disk('linux-bigswap2.img'))
|
||||
self.malta = BaseMalta()
|
||||
self.malta.attachIO(self.iobus)
|
||||
self.malta.ide.pio = self.iobus.master
|
||||
self.malta.ide.config = self.iobus.master
|
||||
self.malta.ide.dma = self.iobus.slave
|
||||
self.malta.ethernet.pio = self.iobus.master
|
||||
self.malta.ethernet.config = self.iobus.master
|
||||
self.malta.ethernet.dma = self.iobus.slave
|
||||
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
|
||||
read_only = True))
|
||||
self.intrctrl = IntrControl()
|
||||
self.mem_mode = mem_mode
|
||||
self.terminal = Terminal()
|
||||
self.kernel = binary('mips/vmlinux')
|
||||
self.console = binary('mips/console')
|
||||
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
|
||||
|
||||
self.system_port = self.membus.slave
|
||||
|
||||
return self
|
||||
|
||||
def x86IOAddress(port):
|
||||
IO_address_space_base = 0x8000000000000000
|
||||
return IO_address_space_base + port
|
||||
|
||||
def connectX86ClassicSystem(x86_sys, numCPUs):
|
||||
# Constants similar to x86_traits.hh
|
||||
IO_address_space_base = 0x8000000000000000
|
||||
pci_config_address_space_base = 0xc000000000000000
|
||||
interrupts_address_space_base = 0xa000000000000000
|
||||
APIC_range_size = 1 << 12;
|
||||
|
||||
x86_sys.membus = MemBus()
|
||||
x86_sys.physmem.port = x86_sys.membus.master
|
||||
|
||||
# North Bridge
|
||||
x86_sys.iobus = NoncoherentBus()
|
||||
x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
|
||||
x86_sys.bridge.master = x86_sys.iobus.slave
|
||||
x86_sys.bridge.slave = x86_sys.membus.master
|
||||
# Allow the bridge to pass through the IO APIC (two pages),
|
||||
# everything in the IO address range up to the local APIC, and
|
||||
# then the entire PCI address space and beyond
|
||||
x86_sys.bridge.ranges = \
|
||||
[
|
||||
AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
|
||||
x86_sys.pc.south_bridge.io_apic.pio_addr +
|
||||
APIC_range_size - 1),
|
||||
AddrRange(IO_address_space_base,
|
||||
interrupts_address_space_base - 1),
|
||||
AddrRange(pci_config_address_space_base,
|
||||
Addr.max)
|
||||
]
|
||||
|
||||
# Create a bridge from the IO bus to the memory bus to allow access to
|
||||
# the local APIC (two pages)
|
||||
x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
|
||||
x86_sys.apicbridge.slave = x86_sys.iobus.master
|
||||
x86_sys.apicbridge.master = x86_sys.membus.slave
|
||||
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
|
||||
interrupts_address_space_base +
|
||||
numCPUs * APIC_range_size
|
||||
- 1)]
|
||||
|
||||
# connect the io bus
|
||||
x86_sys.pc.attachIO(x86_sys.iobus)
|
||||
|
||||
x86_sys.system_port = x86_sys.membus.slave
|
||||
|
||||
def connectX86RubySystem(x86_sys):
|
||||
# North Bridge
|
||||
x86_sys.piobus = NoncoherentBus()
|
||||
|
||||
#
|
||||
# Pio functional accesses from devices need direct access to memory
|
||||
# RubyPort currently does support functional accesses. Therefore provide
|
||||
# the piobus a direct connection to physical memory
|
||||
#
|
||||
x86_sys.piobus.master = x86_sys.physmem.port
|
||||
# add the ide to the list of dma devices that later need to attach to
|
||||
# dma controllers
|
||||
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
|
||||
x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
|
||||
|
||||
|
||||
def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
|
||||
if self == None:
|
||||
self = X86System()
|
||||
|
||||
if not mdesc:
|
||||
# generic system
|
||||
mdesc = SysConfig()
|
||||
self.readfile = mdesc.script()
|
||||
|
||||
self.mem_mode = mem_mode
|
||||
|
||||
# Physical memory
|
||||
self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
|
||||
|
||||
# Platform
|
||||
self.pc = Pc()
|
||||
|
||||
# Create and connect the busses required by each memory system
|
||||
if Ruby:
|
||||
connectX86RubySystem(self)
|
||||
else:
|
||||
connectX86ClassicSystem(self, numCPUs)
|
||||
|
||||
self.intrctrl = IntrControl()
|
||||
|
||||
# Disks
|
||||
disk0 = CowIdeDisk(driveID='master')
|
||||
disk2 = CowIdeDisk(driveID='master')
|
||||
disk0.childImage(mdesc.disk())
|
||||
disk2.childImage(disk('linux-bigswap2.img'))
|
||||
self.pc.south_bridge.ide.disks = [disk0, disk2]
|
||||
|
||||
# Add in a Bios information structure.
|
||||
structures = [X86SMBiosBiosInformation()]
|
||||
self.smbios_table.structures = structures
|
||||
|
||||
# Set up the Intel MP table
|
||||
base_entries = []
|
||||
ext_entries = []
|
||||
for i in xrange(numCPUs):
|
||||
bp = X86IntelMPProcessor(
|
||||
local_apic_id = i,
|
||||
local_apic_version = 0x14,
|
||||
enable = True,
|
||||
bootstrap = (i == 0))
|
||||
base_entries.append(bp)
|
||||
io_apic = X86IntelMPIOAPIC(
|
||||
id = numCPUs,
|
||||
version = 0x11,
|
||||
enable = True,
|
||||
address = 0xfec00000)
|
||||
self.pc.south_bridge.io_apic.apic_id = io_apic.id
|
||||
base_entries.append(io_apic)
|
||||
isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
|
||||
base_entries.append(isa_bus)
|
||||
pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
|
||||
base_entries.append(pci_bus)
|
||||
connect_busses = X86IntelMPBusHierarchy(bus_id=0,
|
||||
subtractive_decode=True, parent_bus=1)
|
||||
ext_entries.append(connect_busses)
|
||||
pci_dev4_inta = X86IntelMPIOIntAssignment(
|
||||
interrupt_type = 'INT',
|
||||
polarity = 'ConformPolarity',
|
||||
trigger = 'ConformTrigger',
|
||||
source_bus_id = 1,
|
||||
source_bus_irq = 0 + (4 << 2),
|
||||
dest_io_apic_id = io_apic.id,
|
||||
dest_io_apic_intin = 16)
|
||||
base_entries.append(pci_dev4_inta)
|
||||
def assignISAInt(irq, apicPin):
|
||||
assign_8259_to_apic = X86IntelMPIOIntAssignment(
|
||||
interrupt_type = 'ExtInt',
|
||||
polarity = 'ConformPolarity',
|
||||
trigger = 'ConformTrigger',
|
||||
source_bus_id = 0,
|
||||
source_bus_irq = irq,
|
||||
dest_io_apic_id = io_apic.id,
|
||||
dest_io_apic_intin = 0)
|
||||
base_entries.append(assign_8259_to_apic)
|
||||
assign_to_apic = X86IntelMPIOIntAssignment(
|
||||
interrupt_type = 'INT',
|
||||
polarity = 'ConformPolarity',
|
||||
trigger = 'ConformTrigger',
|
||||
source_bus_id = 0,
|
||||
source_bus_irq = irq,
|
||||
dest_io_apic_id = io_apic.id,
|
||||
dest_io_apic_intin = apicPin)
|
||||
base_entries.append(assign_to_apic)
|
||||
assignISAInt(0, 2)
|
||||
assignISAInt(1, 1)
|
||||
for i in range(3, 15):
|
||||
assignISAInt(i, i)
|
||||
self.intel_mp_table.base_entries = base_entries
|
||||
self.intel_mp_table.ext_entries = ext_entries
|
||||
|
||||
def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
|
||||
self = LinuxX86System()
|
||||
|
||||
# Build up the x86 system and then specialize it for Linux
|
||||
makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
|
||||
|
||||
# We assume below that there's at least 1MB of memory. We'll require 2
|
||||
# just to avoid corner cases.
|
||||
assert(self.physmem.range.second.getValue() >= 0x200000)
|
||||
|
||||
self.e820_table.entries = \
|
||||
[
|
||||
# Mark the first megabyte of memory as reserved
|
||||
X86E820Entry(addr = 0, size = '1MB', range_type = 2),
|
||||
# Mark the rest as available
|
||||
X86E820Entry(addr = 0x100000,
|
||||
size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
|
||||
range_type = 1)
|
||||
]
|
||||
|
||||
# Command line
|
||||
self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
|
||||
'root=/dev/hda1'
|
||||
return self
|
||||
|
||||
|
||||
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
|
||||
self = Root(full_system = full_system)
|
||||
self.testsys = testSystem
|
||||
self.drivesys = driveSystem
|
||||
self.etherlink = EtherLink()
|
||||
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
||||
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
||||
|
||||
if hasattr(testSystem, 'realview'):
|
||||
self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
|
||||
self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
|
||||
elif hasattr(testSystem, 'tsunami'):
|
||||
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
|
||||
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
|
||||
else:
|
||||
fatal("Don't know how to connect these system together")
|
||||
|
||||
if dumpfile:
|
||||
self.etherdump = EtherDump(file=dumpfile)
|
||||
self.etherlink.dump = Parent.etherdump
|
||||
|
||||
return self
|
||||
196
simulators/gem5/configs/common/O3_ARM_v7a.py
Normal file
196
simulators/gem5/configs/common/O3_ARM_v7a.py
Normal file
@ -0,0 +1,196 @@
|
||||
# Copyright (c) 2012 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
|
||||
|
||||
from m5.objects import *
|
||||
|
||||
# Simple ALU Instructions have a latency of 1
|
||||
class O3_ARM_v7a_Simple_Int(FUDesc):
|
||||
opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
|
||||
count = 2
|
||||
|
||||
# Complex ALU instructions have a variable latencies
|
||||
class O3_ARM_v7a_Complex_Int(FUDesc):
|
||||
opList = [ OpDesc(opClass='IntMult', opLat=3, issueLat=1),
|
||||
OpDesc(opClass='IntDiv', opLat=12, issueLat=12),
|
||||
OpDesc(opClass='IprAccess', opLat=3, issueLat=1) ]
|
||||
count = 1
|
||||
|
||||
|
||||
# Floating point and SIMD instructions
|
||||
class O3_ARM_v7a_FP(FUDesc):
|
||||
opList = [ OpDesc(opClass='SimdAdd', opLat=4),
|
||||
OpDesc(opClass='SimdAddAcc', opLat=4),
|
||||
OpDesc(opClass='SimdAlu', opLat=4),
|
||||
OpDesc(opClass='SimdCmp', opLat=4),
|
||||
OpDesc(opClass='SimdCvt', opLat=3),
|
||||
OpDesc(opClass='SimdMisc', opLat=3),
|
||||
OpDesc(opClass='SimdMult',opLat=5),
|
||||
OpDesc(opClass='SimdMultAcc',opLat=5),
|
||||
OpDesc(opClass='SimdShift',opLat=3),
|
||||
OpDesc(opClass='SimdShiftAcc', opLat=3),
|
||||
OpDesc(opClass='SimdSqrt', opLat=9),
|
||||
OpDesc(opClass='SimdFloatAdd',opLat=5),
|
||||
OpDesc(opClass='SimdFloatAlu',opLat=5),
|
||||
OpDesc(opClass='SimdFloatCmp', opLat=3),
|
||||
OpDesc(opClass='SimdFloatCvt', opLat=3),
|
||||
OpDesc(opClass='SimdFloatDiv', opLat=3),
|
||||
OpDesc(opClass='SimdFloatMisc', opLat=3),
|
||||
OpDesc(opClass='SimdFloatMult', opLat=3),
|
||||
OpDesc(opClass='SimdFloatMultAcc',opLat=1),
|
||||
OpDesc(opClass='SimdFloatSqrt', opLat=9),
|
||||
OpDesc(opClass='FloatAdd', opLat=5),
|
||||
OpDesc(opClass='FloatCmp', opLat=5),
|
||||
OpDesc(opClass='FloatCvt', opLat=5),
|
||||
OpDesc(opClass='FloatDiv', opLat=9, issueLat=9),
|
||||
OpDesc(opClass='FloatSqrt', opLat=33, issueLat=33),
|
||||
OpDesc(opClass='FloatMult', opLat=4) ]
|
||||
count = 2
|
||||
|
||||
|
||||
# Load/Store Units
|
||||
class O3_ARM_v7a_Load(FUDesc):
|
||||
opList = [ OpDesc(opClass='MemRead',opLat=2) ]
|
||||
count = 1
|
||||
|
||||
class O3_ARM_v7a_Store(FUDesc):
|
||||
opList = [OpDesc(opClass='MemWrite',opLat=2) ]
|
||||
count = 1
|
||||
|
||||
# Functional Units for this CPU
|
||||
class O3_ARM_v7a_FUP(FUPool):
|
||||
FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
|
||||
O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
|
||||
|
||||
|
||||
class O3_ARM_v7a_3(DerivO3CPU):
|
||||
predType = "tournament"
|
||||
localPredictorSize = 64
|
||||
localCtrBits = 2
|
||||
localHistoryTableSize = 64
|
||||
localHistoryBits = 6
|
||||
globalPredictorSize = 8192
|
||||
globalCtrBits = 2
|
||||
globalHistoryBits = 13
|
||||
choicePredictorSize = 8192
|
||||
choiceCtrBits = 2
|
||||
BTBEntries = 2048
|
||||
BTBTagSize = 18
|
||||
RASSize = 16
|
||||
instShiftAmt = 2
|
||||
LQEntries = 16
|
||||
SQEntries = 16
|
||||
LSQDepCheckShift = 0
|
||||
LFSTSize = 1024
|
||||
SSITSize = 1024
|
||||
decodeToFetchDelay = 1
|
||||
renameToFetchDelay = 1
|
||||
iewToFetchDelay = 1
|
||||
commitToFetchDelay = 1
|
||||
renameToDecodeDelay = 1
|
||||
iewToDecodeDelay = 1
|
||||
commitToDecodeDelay = 1
|
||||
iewToRenameDelay = 1
|
||||
commitToRenameDelay = 1
|
||||
commitToIEWDelay = 1
|
||||
fetchWidth = 3
|
||||
fetchToDecodeDelay = 3
|
||||
decodeWidth = 3
|
||||
decodeToRenameDelay = 2
|
||||
renameWidth = 3
|
||||
renameToIEWDelay = 1
|
||||
issueToExecuteDelay = 1
|
||||
dispatchWidth = 6
|
||||
issueWidth = 8
|
||||
wbWidth = 8
|
||||
wbDepth = 1
|
||||
fuPool = O3_ARM_v7a_FUP()
|
||||
iewToCommitDelay = 1
|
||||
renameToROBDelay = 1
|
||||
commitWidth = 8
|
||||
squashWidth = 8
|
||||
trapLatency = 13
|
||||
backComSize = 5
|
||||
forwardComSize = 5
|
||||
numPhysIntRegs = 128
|
||||
numPhysFloatRegs = 128
|
||||
numIQEntries = 32
|
||||
numROBEntries = 40
|
||||
|
||||
defer_registration= False
|
||||
|
||||
# Instruction Cache
|
||||
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
|
||||
class O3_ARM_v7a_ICache(BaseCache):
|
||||
latency = '1ns'
|
||||
block_size = 64
|
||||
mshrs = 2
|
||||
tgts_per_mshr = 8
|
||||
size = '32kB'
|
||||
assoc = 2
|
||||
is_top_level = 'true'
|
||||
|
||||
# Data Cache
|
||||
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
|
||||
class O3_ARM_v7a_DCache(BaseCache):
|
||||
latency = '2ns'
|
||||
block_size = 64
|
||||
mshrs = 6
|
||||
tgts_per_mshr = 8
|
||||
size = '32kB'
|
||||
assoc = 2
|
||||
write_buffers = 16
|
||||
is_top_level = 'true'
|
||||
|
||||
# TLB Cache
|
||||
# Use a cache as a L2 TLB
|
||||
class O3_ARM_v7aWalkCache(BaseCache):
|
||||
latency = '4ns'
|
||||
block_size = 64
|
||||
mshrs = 6
|
||||
tgts_per_mshr = 8
|
||||
size = '1kB'
|
||||
assoc = 8
|
||||
write_buffers = 16
|
||||
is_top_level = 'true'
|
||||
|
||||
|
||||
# L2 Cache
|
||||
# All latencys assume a 1GHz clock rate, with a faster clock they would be faster
|
||||
class O3_ARM_v7aL2(BaseCache):
|
||||
latency = '12ns'
|
||||
block_size = 64
|
||||
mshrs = 16
|
||||
tgts_per_mshr = 8
|
||||
size = '1MB'
|
||||
assoc = 16
|
||||
write_buffers = 8
|
||||
prefetch_on_access = 'true'
|
||||
# Simple stride prefetcher
|
||||
prefetcher = StridePrefetcher(degree=8, latency='1.0ns')
|
||||
|
||||
181
simulators/gem5/configs/common/Options.py
Normal file
181
simulators/gem5/configs/common/Options.py
Normal file
@ -0,0 +1,181 @@
|
||||
# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Lisa Hsu
|
||||
|
||||
import m5
|
||||
from m5.defines import buildEnv
|
||||
from m5.objects import *
|
||||
from Benchmarks import *
|
||||
|
||||
def addCommonOptions(parser):
|
||||
# system options
|
||||
parser.add_option("--cpu-type", type="choice", default="atomic",
|
||||
choices = ["atomic", "timing", "detailed", "inorder",
|
||||
"arm_detailed"],
|
||||
help = "type of cpu to run with")
|
||||
parser.add_option("--checker", action="store_true");
|
||||
parser.add_option("-n", "--num-cpus", type="int", default=1)
|
||||
parser.add_option("--caches", action="store_true")
|
||||
parser.add_option("--l2cache", action="store_true")
|
||||
parser.add_option("--fastmem", action="store_true")
|
||||
parser.add_option("--clock", action="store", type="string", default='2GHz')
|
||||
parser.add_option("--num-dirs", type="int", default=1)
|
||||
parser.add_option("--num-l2caches", type="int", default=1)
|
||||
parser.add_option("--num-l3caches", type="int", default=1)
|
||||
parser.add_option("--l1d_size", type="string", default="64kB")
|
||||
parser.add_option("--l1i_size", type="string", default="32kB")
|
||||
parser.add_option("--l2_size", type="string", default="2MB")
|
||||
parser.add_option("--l3_size", type="string", default="16MB")
|
||||
parser.add_option("--l1d_assoc", type="int", default=2)
|
||||
parser.add_option("--l1i_assoc", type="int", default=2)
|
||||
parser.add_option("--l2_assoc", type="int", default=8)
|
||||
parser.add_option("--l3_assoc", type="int", default=16)
|
||||
parser.add_option("--cacheline_size", type="int", default=64)
|
||||
parser.add_option("--ruby", action="store_true")
|
||||
|
||||
# Run duration options
|
||||
parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
|
||||
metavar="T", help="Stop after T ticks")
|
||||
parser.add_option("--maxtime", type="float")
|
||||
parser.add_option("-I", "--maxinsts", action="store", type="int",
|
||||
default=None, help="""Total number of instructions to
|
||||
simulate (default: run forever)""")
|
||||
parser.add_option("--work-item-id", action="store", type="int",
|
||||
help="the specific work id for exit & checkpointing")
|
||||
parser.add_option("--work-begin-cpu-id-exit", action="store", type="int",
|
||||
help="exit when work starts on the specified cpu")
|
||||
parser.add_option("--work-end-exit-count", action="store", type="int",
|
||||
help="exit at specified work end count")
|
||||
parser.add_option("--work-begin-exit-count", action="store", type="int",
|
||||
help="exit at specified work begin count")
|
||||
parser.add_option("--init-param", action="store", type="int", default=0,
|
||||
help="""Parameter available in simulation with m5
|
||||
initparam""")
|
||||
|
||||
# Checkpointing options
|
||||
###Note that performing checkpointing via python script files will override
|
||||
###checkpoint instructions built into binaries.
|
||||
parser.add_option("--take-checkpoints", action="store", type="string",
|
||||
help="<M,N> will take checkpoint at cycle M and every N cycles thereafter")
|
||||
parser.add_option("--max-checkpoints", action="store", type="int",
|
||||
help="the maximum number of checkpoints to drop", default=5)
|
||||
parser.add_option("--checkpoint-dir", action="store", type="string",
|
||||
help="Place all checkpoints in this absolute directory")
|
||||
parser.add_option("-r", "--checkpoint-restore", action="store", type="int",
|
||||
help="restore from checkpoint <N>")
|
||||
parser.add_option("--checkpoint-at-end", action="store_true",
|
||||
help="take a checkpoint at end of run")
|
||||
parser.add_option("--work-begin-checkpoint-count", action="store", type="int",
|
||||
help="checkpoint at specified work begin count")
|
||||
parser.add_option("--work-end-checkpoint-count", action="store", type="int",
|
||||
help="checkpoint at specified work end count")
|
||||
parser.add_option("--work-cpus-checkpoint-count", action="store", type="int",
|
||||
help="checkpoint and exit when active cpu count is reached")
|
||||
parser.add_option("--restore-with-cpu", action="store", type="choice",
|
||||
default="atomic", choices = ["atomic", "timing",
|
||||
"detailed", "inorder"],
|
||||
help = "cpu type for restoring from a checkpoint")
|
||||
|
||||
|
||||
# CPU Switching - default switch model goes from a checkpoint
|
||||
# to a timing simple CPU with caches to warm up, then to detailed CPU for
|
||||
# data measurement
|
||||
parser.add_option("-s", "--standard-switch", action="store_true",
|
||||
help="switch from timing CPU to Detailed CPU")
|
||||
parser.add_option("-w", "--warmup", action="store", type="int",
|
||||
help="if -s, then this is the warmup period. else, this is ignored",
|
||||
default=5000000000)
|
||||
parser.add_option("-p", "--prog-interval", type="int",
|
||||
help="CPU Progress Interval")
|
||||
|
||||
# Fastforwarding and simpoint related materials
|
||||
parser.add_option("-W", "--warmup-insts", action="store", type="int",
|
||||
default=None,
|
||||
help="Warmup period in total instructions (requires --standard-switch)")
|
||||
parser.add_option("--bench", action="store", type="string", default=None,
|
||||
help="base names for --take-checkpoint and --checkpoint-restore")
|
||||
parser.add_option("-F", "--fast-forward", action="store", type="string",
|
||||
default=None,
|
||||
help="Number of instructions to fast forward before switching")
|
||||
parser.add_option("-S", "--simpoint", action="store_true", default=False,
|
||||
help="""Use workload simpoints as an instruction offset for
|
||||
--checkpoint-restore or --take-checkpoint.""")
|
||||
parser.add_option("--at-instruction", action="store_true", default=False,
|
||||
help="""Treat value of --checkpoint-restore or --take-checkpoint as a
|
||||
number of instructions.""")
|
||||
|
||||
def addSEOptions(parser):
|
||||
# Benchmark options
|
||||
parser.add_option("-c", "--cmd", default="",
|
||||
help="The binary to run in syscall emulation mode.")
|
||||
parser.add_option("-o", "--options", default="",
|
||||
help="""The options to pass to the binary, use " "
|
||||
around the entire string""")
|
||||
parser.add_option("-i", "--input", default="",
|
||||
help="Read stdin from a file.")
|
||||
parser.add_option("--output", default="",
|
||||
help="Redirect stdout to a file.")
|
||||
parser.add_option("--errout", default="",
|
||||
help="Redirect stderr to a file.")
|
||||
|
||||
def addFSOptions(parser):
|
||||
# Simulation options
|
||||
parser.add_option("--timesync", action="store_true",
|
||||
help="Prevent simulated time from getting ahead of real time")
|
||||
|
||||
# System options
|
||||
parser.add_option("--kernel", action="store", type="string")
|
||||
parser.add_option("--script", action="store", type="string")
|
||||
parser.add_option("--frame-capture", action="store_true",
|
||||
help="Stores changed frame buffers from the VNC server to compressed "\
|
||||
"files in the gem5 output directory")
|
||||
|
||||
if buildEnv['TARGET_ISA'] == "arm":
|
||||
parser.add_option("--bare-metal", action="store_true",
|
||||
help="Provide the raw system without the linux specific bits")
|
||||
parser.add_option("--machine-type", action="store", type="choice",
|
||||
choices=ArmMachineType.map.keys(), default="RealView_PBX")
|
||||
# Benchmark options
|
||||
parser.add_option("--dual", action="store_true",
|
||||
help="Simulate two systems attached with an ethernet link")
|
||||
parser.add_option("-b", "--benchmark", action="store", type="string",
|
||||
dest="benchmark",
|
||||
help="Specify the benchmark to run. Available benchmarks: %s"\
|
||||
% DefinedBenchmarks)
|
||||
|
||||
# Metafile options
|
||||
parser.add_option("--etherdump", action="store", type="string", dest="etherdump",
|
||||
help="Specify the filename to dump a pcap capture of the" \
|
||||
"ethernet traffic")
|
||||
|
||||
# Disk Image Options
|
||||
parser.add_option("--disk-image", action="store", type="string", default=None,
|
||||
help="Path to the disk image to use.")
|
||||
|
||||
# Memory Size Options
|
||||
parser.add_option("--mem-size", action="store", type="string", default=None,
|
||||
help="Specify the physical memory size (single memory)")
|
||||
407
simulators/gem5/configs/common/Simulation.py
Normal file
407
simulators/gem5/configs/common/Simulation.py
Normal file
@ -0,0 +1,407 @@
|
||||
# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
||||
# Copyright (c) 2010 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Lisa Hsu
|
||||
|
||||
from os import getcwd
|
||||
from os.path import join as joinpath
|
||||
|
||||
import m5
|
||||
from m5.defines import buildEnv
|
||||
from m5.objects import *
|
||||
from m5.util import *
|
||||
from O3_ARM_v7a import *
|
||||
|
||||
addToPath('../common')
|
||||
|
||||
def setCPUClass(options):
|
||||
|
||||
atomic = False
|
||||
if options.cpu_type == "timing":
|
||||
class TmpClass(TimingSimpleCPU): pass
|
||||
elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
|
||||
if not options.caches and not options.ruby:
|
||||
print "O3 CPU must be used with caches"
|
||||
sys.exit(1)
|
||||
if options.cpu_type == "arm_detailed":
|
||||
class TmpClass(O3_ARM_v7a_3): pass
|
||||
else:
|
||||
class TmpClass(DerivO3CPU): pass
|
||||
elif options.cpu_type == "inorder":
|
||||
if not options.caches:
|
||||
print "InOrder CPU must be used with caches"
|
||||
sys.exit(1)
|
||||
class TmpClass(InOrderCPU): pass
|
||||
else:
|
||||
class TmpClass(AtomicSimpleCPU): pass
|
||||
atomic = True
|
||||
|
||||
CPUClass = None
|
||||
test_mem_mode = 'atomic'
|
||||
|
||||
if not atomic:
|
||||
if options.checkpoint_restore != None:
|
||||
if options.restore_with_cpu != options.cpu_type:
|
||||
CPUClass = TmpClass
|
||||
class TmpClass(AtomicSimpleCPU): pass
|
||||
else:
|
||||
if options.restore_with_cpu != "atomic":
|
||||
test_mem_mode = 'timing'
|
||||
|
||||
elif options.fast_forward:
|
||||
CPUClass = TmpClass
|
||||
class TmpClass(AtomicSimpleCPU): pass
|
||||
else:
|
||||
test_mem_mode = 'timing'
|
||||
|
||||
return (TmpClass, test_mem_mode, CPUClass)
|
||||
|
||||
def setWorkCountOptions(system, options):
|
||||
if options.work_item_id != None:
|
||||
system.work_item_id = options.work_item_id
|
||||
if options.work_begin_cpu_id_exit != None:
|
||||
system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
|
||||
if options.work_end_exit_count != None:
|
||||
system.work_end_exit_count = options.work_end_exit_count
|
||||
if options.work_end_checkpoint_count != None:
|
||||
system.work_end_ckpt_count = options.work_end_checkpoint_count
|
||||
if options.work_begin_exit_count != None:
|
||||
system.work_begin_exit_count = options.work_begin_exit_count
|
||||
if options.work_begin_checkpoint_count != None:
|
||||
system.work_begin_ckpt_count = options.work_begin_checkpoint_count
|
||||
if options.work_cpus_checkpoint_count != None:
|
||||
system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
|
||||
|
||||
def run(options, root, testsys, cpu_class):
|
||||
if options.maxtick:
|
||||
maxtick = options.maxtick
|
||||
elif options.maxtime:
|
||||
simtime = m5.ticks.seconds(simtime)
|
||||
print "simulating for: ", simtime
|
||||
maxtick = simtime
|
||||
else:
|
||||
maxtick = m5.MaxTick
|
||||
|
||||
if options.checkpoint_dir:
|
||||
cptdir = options.checkpoint_dir
|
||||
elif m5.options.outdir:
|
||||
cptdir = m5.options.outdir
|
||||
else:
|
||||
cptdir = getcwd()
|
||||
|
||||
if options.fast_forward and options.checkpoint_restore != None:
|
||||
fatal("Can't specify both --fast-forward and --checkpoint-restore")
|
||||
|
||||
if options.standard_switch and not options.caches:
|
||||
fatal("Must specify --caches when using --standard-switch")
|
||||
|
||||
np = options.num_cpus
|
||||
max_checkpoints = options.max_checkpoints
|
||||
switch_cpus = None
|
||||
|
||||
if options.prog_interval:
|
||||
for i in xrange(np):
|
||||
testsys.cpu[i].progress_interval = options.prog_interval
|
||||
|
||||
if options.maxinsts:
|
||||
for i in xrange(np):
|
||||
testsys.cpu[i].max_insts_any_thread = options.maxinsts
|
||||
|
||||
if cpu_class:
|
||||
switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
|
||||
for i in xrange(np)]
|
||||
|
||||
for i in xrange(np):
|
||||
if options.fast_forward:
|
||||
testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
|
||||
switch_cpus[i].system = testsys
|
||||
switch_cpus[i].workload = testsys.cpu[i].workload
|
||||
switch_cpus[i].clock = testsys.cpu[0].clock
|
||||
# simulation period
|
||||
if options.maxinsts:
|
||||
switch_cpus[i].max_insts_any_thread = options.maxinsts
|
||||
# Add checker cpu if selected
|
||||
if options.checker:
|
||||
switch_cpus[i].addCheckerCpu()
|
||||
|
||||
testsys.switch_cpus = switch_cpus
|
||||
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
|
||||
|
||||
if options.standard_switch:
|
||||
if not options.caches:
|
||||
# O3 CPU must have a cache to work.
|
||||
print "O3 CPU must be used with caches"
|
||||
sys.exit(1)
|
||||
|
||||
switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
|
||||
for i in xrange(np)]
|
||||
switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
|
||||
for i in xrange(np)]
|
||||
|
||||
for i in xrange(np):
|
||||
switch_cpus[i].system = testsys
|
||||
switch_cpus_1[i].system = testsys
|
||||
switch_cpus[i].workload = testsys.cpu[i].workload
|
||||
switch_cpus_1[i].workload = testsys.cpu[i].workload
|
||||
switch_cpus[i].clock = testsys.cpu[0].clock
|
||||
switch_cpus_1[i].clock = testsys.cpu[0].clock
|
||||
|
||||
# if restoring, make atomic cpu simulate only a few instructions
|
||||
if options.checkpoint_restore != None:
|
||||
testsys.cpu[i].max_insts_any_thread = 1
|
||||
# Fast forward to specified location if we are not restoring
|
||||
elif options.fast_forward:
|
||||
testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
|
||||
# Fast forward to a simpoint (warning: time consuming)
|
||||
elif options.simpoint:
|
||||
if testsys.cpu[i].workload[0].simpoint == 0:
|
||||
fatal('simpoint not found')
|
||||
testsys.cpu[i].max_insts_any_thread = \
|
||||
testsys.cpu[i].workload[0].simpoint
|
||||
# No distance specified, just switch
|
||||
else:
|
||||
testsys.cpu[i].max_insts_any_thread = 1
|
||||
|
||||
# warmup period
|
||||
if options.warmup_insts:
|
||||
switch_cpus[i].max_insts_any_thread = options.warmup_insts
|
||||
|
||||
# simulation period
|
||||
if options.maxinsts:
|
||||
switch_cpus_1[i].max_insts_any_thread = options.maxinsts
|
||||
|
||||
# attach the checker cpu if selected
|
||||
if options.checker:
|
||||
switch_cpus[i].addCheckerCpu()
|
||||
switch_cpus_1[i].addCheckerCpu()
|
||||
|
||||
testsys.switch_cpus = switch_cpus
|
||||
testsys.switch_cpus_1 = switch_cpus_1
|
||||
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
|
||||
switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
|
||||
|
||||
# set the checkpoint in the cpu before m5.instantiate is called
|
||||
if options.take_checkpoints != None and \
|
||||
(options.simpoint or options.at_instruction):
|
||||
offset = int(options.take_checkpoints)
|
||||
# Set an instruction break point
|
||||
if options.simpoint:
|
||||
for i in xrange(np):
|
||||
if testsys.cpu[i].workload[0].simpoint == 0:
|
||||
fatal('no simpoint for testsys.cpu[%d].workload[0]', i)
|
||||
checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint) + offset
|
||||
testsys.cpu[i].max_insts_any_thread = checkpoint_inst
|
||||
# used for output below
|
||||
options.take_checkpoints = checkpoint_inst
|
||||
else:
|
||||
options.take_checkpoints = offset
|
||||
# Set all test cpus with the right number of instructions
|
||||
# for the upcoming simulation
|
||||
for i in xrange(np):
|
||||
testsys.cpu[i].max_insts_any_thread = offset
|
||||
|
||||
checkpoint_dir = None
|
||||
if options.checkpoint_restore != None:
|
||||
from os.path import isdir, exists
|
||||
from os import listdir
|
||||
import re
|
||||
|
||||
if not isdir(cptdir):
|
||||
fatal("checkpoint dir %s does not exist!", cptdir)
|
||||
|
||||
if options.at_instruction or options.simpoint:
|
||||
inst = options.checkpoint_restore
|
||||
if options.simpoint:
|
||||
# assume workload 0 has the simpoint
|
||||
if testsys.cpu[0].workload[0].simpoint == 0:
|
||||
fatal('Unable to find simpoint')
|
||||
inst += int(testsys.cpu[0].workload[0].simpoint)
|
||||
|
||||
checkpoint_dir = joinpath(cptdir,
|
||||
"cpt.%s.%s" % (options.bench, inst))
|
||||
if not exists(checkpoint_dir):
|
||||
fatal("Unable to find checkpoint directory %s", checkpoint_dir)
|
||||
else:
|
||||
dirs = listdir(cptdir)
|
||||
expr = re.compile('cpt\.([0-9]*)')
|
||||
cpts = []
|
||||
for dir in dirs:
|
||||
match = expr.match(dir)
|
||||
if match:
|
||||
cpts.append(match.group(1))
|
||||
|
||||
cpts.sort(lambda a,b: cmp(long(a), long(b)))
|
||||
|
||||
cpt_num = options.checkpoint_restore
|
||||
|
||||
if cpt_num > len(cpts):
|
||||
fatal('Checkpoint %d not found', cpt_num)
|
||||
|
||||
## Adjust max tick based on our starting tick
|
||||
maxtick = maxtick - int(cpts[cpt_num - 1])
|
||||
checkpoint_dir = joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1])
|
||||
|
||||
m5.instantiate(checkpoint_dir)
|
||||
|
||||
if options.standard_switch or cpu_class:
|
||||
if options.standard_switch:
|
||||
print "Switch at instruction count:%s" % \
|
||||
str(testsys.cpu[0].max_insts_any_thread)
|
||||
exit_event = m5.simulate()
|
||||
elif cpu_class and options.fast_forward:
|
||||
print "Switch at instruction count:%s" % \
|
||||
str(testsys.cpu[0].max_insts_any_thread)
|
||||
exit_event = m5.simulate()
|
||||
else:
|
||||
print "Switch at curTick count:%s" % str(10000)
|
||||
exit_event = m5.simulate(10000)
|
||||
print "Switched CPUS @ tick %s" % (m5.curTick())
|
||||
|
||||
# when you change to Timing (or Atomic), you halt the system
|
||||
# given as argument. When you are finished with the system
|
||||
# changes (including switchCpus), you must resume the system
|
||||
# manually. You DON'T need to resume after just switching
|
||||
# CPUs if you haven't changed anything on the system level.
|
||||
|
||||
m5.changeToTiming(testsys)
|
||||
m5.switchCpus(switch_cpu_list)
|
||||
m5.resume(testsys)
|
||||
|
||||
if options.standard_switch:
|
||||
print "Switch at instruction count:%d" % \
|
||||
(testsys.switch_cpus[0].max_insts_any_thread)
|
||||
|
||||
#warmup instruction count may have already been set
|
||||
if options.warmup_insts:
|
||||
exit_event = m5.simulate()
|
||||
else:
|
||||
exit_event = m5.simulate(options.warmup)
|
||||
print "Switching CPUS @ tick %s" % (m5.curTick())
|
||||
print "Simulation ends instruction count:%d" % \
|
||||
(testsys.switch_cpus_1[0].max_insts_any_thread)
|
||||
m5.drain(testsys)
|
||||
m5.switchCpus(switch_cpu_list1)
|
||||
m5.resume(testsys)
|
||||
|
||||
num_checkpoints = 0
|
||||
exit_cause = ''
|
||||
|
||||
# If we're taking and restoring checkpoints, use checkpoint_dir
|
||||
# option only for finding the checkpoints to restore from. This
|
||||
# lets us test checkpointing by restoring from one set of
|
||||
# checkpoints, generating a second set, and then comparing them.
|
||||
if options.take_checkpoints and options.checkpoint_restore:
|
||||
if m5.options.outdir:
|
||||
cptdir = m5.options.outdir
|
||||
else:
|
||||
cptdir = getcwd()
|
||||
|
||||
# Checkpoints being taken via the command line at <when> and at
|
||||
# subsequent periods of <period>. Checkpoint instructions
|
||||
# received from the benchmark running are ignored and skipped in
|
||||
# favor of command line checkpoint instructions.
|
||||
if options.take_checkpoints != None :
|
||||
if options.at_instruction or options.simpoint:
|
||||
checkpoint_inst = int(options.take_checkpoints)
|
||||
|
||||
# maintain correct offset if we restored from some instruction
|
||||
if options.checkpoint_restore != None:
|
||||
checkpoint_inst += options.checkpoint_restore
|
||||
|
||||
print "Creating checkpoint at inst:%d" % (checkpoint_inst)
|
||||
exit_event = m5.simulate()
|
||||
print "exit cause = %s" % (exit_event.getCause())
|
||||
|
||||
# skip checkpoint instructions should they exist
|
||||
while exit_event.getCause() == "checkpoint":
|
||||
exit_event = m5.simulate()
|
||||
|
||||
if exit_event.getCause() == \
|
||||
"a thread reached the max instruction count":
|
||||
m5.checkpoint(joinpath(cptdir, "cpt.%s.%d" % \
|
||||
(options.bench, checkpoint_inst)))
|
||||
print "Checkpoint written."
|
||||
num_checkpoints += 1
|
||||
|
||||
if exit_event.getCause() == "user interrupt received":
|
||||
exit_cause = exit_event.getCause();
|
||||
else:
|
||||
when, period = options.take_checkpoints.split(",", 1)
|
||||
when = int(when)
|
||||
period = int(period)
|
||||
|
||||
exit_event = m5.simulate(when)
|
||||
while exit_event.getCause() == "checkpoint":
|
||||
exit_event = m5.simulate(when - m5.curTick())
|
||||
|
||||
if exit_event.getCause() == "simulate() limit reached":
|
||||
m5.checkpoint(joinpath(cptdir, "cpt.%d"))
|
||||
num_checkpoints += 1
|
||||
|
||||
sim_ticks = when
|
||||
exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
|
||||
while num_checkpoints < max_checkpoints and \
|
||||
exit_event.getCause() == "simulate() limit reached":
|
||||
if (sim_ticks + period) > maxtick:
|
||||
exit_event = m5.simulate(maxtick - sim_ticks)
|
||||
exit_cause = exit_event.getCause()
|
||||
break
|
||||
else:
|
||||
exit_event = m5.simulate(period)
|
||||
sim_ticks += period
|
||||
while exit_event.getCause() == "checkpoint":
|
||||
exit_event = m5.simulate(sim_ticks - m5.curTick())
|
||||
if exit_event.getCause() == "simulate() limit reached":
|
||||
m5.checkpoint(joinpath(cptdir, "cpt.%d"))
|
||||
num_checkpoints += 1
|
||||
|
||||
if exit_event.getCause() != "simulate() limit reached":
|
||||
exit_cause = exit_event.getCause();
|
||||
|
||||
else: # no checkpoints being taken via this script
|
||||
if options.fast_forward:
|
||||
m5.stats.reset()
|
||||
print "**** REAL SIMULATION ****"
|
||||
exit_event = m5.simulate(maxtick)
|
||||
|
||||
while exit_event.getCause() == "checkpoint":
|
||||
m5.checkpoint(joinpath(cptdir, "cpt.%d"))
|
||||
num_checkpoints += 1
|
||||
if num_checkpoints == max_checkpoints:
|
||||
exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
|
||||
break
|
||||
|
||||
exit_event = m5.simulate(maxtick - m5.curTick())
|
||||
exit_cause = exit_event.getCause()
|
||||
|
||||
if exit_cause == '':
|
||||
exit_cause = exit_event.getCause()
|
||||
print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause)
|
||||
|
||||
if options.checkpoint_at_end:
|
||||
m5.checkpoint(joinpath(cptdir, "cpt.%d"))
|
||||
|
||||
71
simulators/gem5/configs/common/SysPaths.py
Normal file
71
simulators/gem5/configs/common/SysPaths.py
Normal file
@ -0,0 +1,71 @@
|
||||
# Copyright (c) 2006 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
import os, sys
|
||||
from os.path import isdir, join as joinpath
|
||||
from os import environ as env
|
||||
|
||||
config_path = os.path.dirname(os.path.abspath(__file__))
|
||||
config_root = os.path.dirname(config_path)
|
||||
|
||||
def disk(file):
|
||||
system()
|
||||
return joinpath(disk.dir, file)
|
||||
|
||||
def binary(file):
|
||||
system()
|
||||
return joinpath(binary.dir, file)
|
||||
|
||||
def script(file):
|
||||
system()
|
||||
return joinpath(script.dir, file)
|
||||
|
||||
def system():
|
||||
if not system.dir:
|
||||
try:
|
||||
path = env['M5_PATH'].split(':')
|
||||
except KeyError:
|
||||
path = [ '/dist/m5/system', '/n/poolfs/z/dist/m5/system' ]
|
||||
|
||||
for system.dir in path:
|
||||
if os.path.isdir(system.dir):
|
||||
break
|
||||
else:
|
||||
raise ImportError, "Can't find a path to system files."
|
||||
|
||||
if not binary.dir:
|
||||
binary.dir = joinpath(system.dir, 'binaries')
|
||||
if not disk.dir:
|
||||
disk.dir = joinpath(system.dir, 'disks')
|
||||
if not script.dir:
|
||||
script.dir = joinpath(config_root, 'boot')
|
||||
|
||||
system.dir = None
|
||||
binary.dir = None
|
||||
disk.dir = None
|
||||
script.dir = None
|
||||
754
simulators/gem5/configs/common/cpu2000.py
Normal file
754
simulators/gem5/configs/common/cpu2000.py
Normal file
@ -0,0 +1,754 @@
|
||||
# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
import os
|
||||
import sys
|
||||
from os.path import basename, exists, join as joinpath, normpath
|
||||
from os.path import isdir, isfile, islink
|
||||
|
||||
spec_dist = os.environ.get('M5_CPU2000', '/dist/m5/cpu2000')
|
||||
|
||||
def copyfiles(srcdir, dstdir):
|
||||
from filecmp import cmp as filecmp
|
||||
from shutil import copyfile
|
||||
|
||||
srcdir = normpath(srcdir)
|
||||
dstdir = normpath(dstdir)
|
||||
|
||||
if not isdir(dstdir):
|
||||
os.mkdir(dstdir)
|
||||
|
||||
for root, dirs, files in os.walk(srcdir):
|
||||
root = normpath(root)
|
||||
prefix = os.path.commonprefix([root, srcdir])
|
||||
|
||||
root = root[len(prefix):]
|
||||
if root.startswith('/'):
|
||||
root = root[1:]
|
||||
|
||||
for entry in dirs:
|
||||
newdir = joinpath(dstdir, root, entry)
|
||||
if not isdir(newdir):
|
||||
os.mkdir(newdir)
|
||||
|
||||
for entry in files:
|
||||
dest = normpath(joinpath(dstdir, root, entry))
|
||||
src = normpath(joinpath(srcdir, root, entry))
|
||||
if not isfile(dest) or not filecmp(src, dest):
|
||||
copyfile(src, dest)
|
||||
|
||||
# some of the spec benchmarks expect to be run from one directory up.
|
||||
# just create some symlinks that solve the problem
|
||||
inlink = joinpath(dstdir, 'input')
|
||||
outlink = joinpath(dstdir, 'output')
|
||||
if not exists(inlink):
|
||||
os.symlink('.', inlink)
|
||||
if not exists(outlink):
|
||||
os.symlink('.', outlink)
|
||||
|
||||
class Benchmark(object):
|
||||
def __init__(self, isa, os, input_set):
|
||||
if not hasattr(self.__class__, 'name'):
|
||||
self.name = self.__class__.__name__
|
||||
|
||||
if not hasattr(self.__class__, 'binary'):
|
||||
self.binary = self.name
|
||||
|
||||
if not hasattr(self.__class__, 'args'):
|
||||
self.args = []
|
||||
|
||||
if not hasattr(self.__class__, 'output'):
|
||||
self.output = '%s.out' % self.name
|
||||
|
||||
if not hasattr(self.__class__, 'simpoint'):
|
||||
self.simpoint = None
|
||||
|
||||
try:
|
||||
func = getattr(self.__class__, input_set)
|
||||
except AttributeError:
|
||||
raise AttributeError, \
|
||||
'The benchmark %s does not have the %s input set' % \
|
||||
(self.name, input_set)
|
||||
|
||||
executable = joinpath(spec_dist, 'binaries', isa, os, self.binary)
|
||||
if not isfile(executable):
|
||||
raise AttributeError, '%s not found' % executable
|
||||
self.executable = executable
|
||||
|
||||
# root of tree for input & output data files
|
||||
data_dir = joinpath(spec_dist, 'data', self.name)
|
||||
# optional subtree with files shared across input sets
|
||||
all_dir = joinpath(data_dir, 'all')
|
||||
# dirs for input & output files for this input set
|
||||
inputs_dir = joinpath(data_dir, input_set, 'input')
|
||||
outputs_dir = joinpath(data_dir, input_set, 'output')
|
||||
# keep around which input set was specified
|
||||
self.input_set = input_set
|
||||
|
||||
if not isdir(inputs_dir):
|
||||
raise AttributeError, '%s not found' % inputs_dir
|
||||
|
||||
self.inputs_dir = [ inputs_dir ]
|
||||
if isdir(all_dir):
|
||||
self.inputs_dir += [ joinpath(all_dir, 'input') ]
|
||||
if isdir(outputs_dir):
|
||||
self.outputs_dir = outputs_dir
|
||||
|
||||
if not hasattr(self.__class__, 'stdin'):
|
||||
self.stdin = joinpath(inputs_dir, '%s.in' % self.name)
|
||||
if not isfile(self.stdin):
|
||||
self.stdin = None
|
||||
|
||||
if not hasattr(self.__class__, 'stdout'):
|
||||
self.stdout = joinpath(outputs_dir, '%s.out' % self.name)
|
||||
if not isfile(self.stdout):
|
||||
self.stdout = None
|
||||
|
||||
func(self, isa, os)
|
||||
|
||||
def makeLiveProcessArgs(self, **kwargs):
|
||||
# set up default args for LiveProcess object
|
||||
process_args = {}
|
||||
process_args['cmd'] = [ self.name ] + self.args
|
||||
process_args['executable'] = self.executable
|
||||
if self.stdin:
|
||||
process_args['input'] = self.stdin
|
||||
if self.stdout:
|
||||
process_args['output'] = self.stdout
|
||||
if self.simpoint:
|
||||
process_args['simpoint'] = self.simpoint
|
||||
# explicit keywords override defaults
|
||||
process_args.update(kwargs)
|
||||
|
||||
return process_args
|
||||
|
||||
def makeLiveProcess(self, **kwargs):
|
||||
process_args = self.makeLiveProcessArgs(**kwargs)
|
||||
|
||||
# figure out working directory: use m5's outdir unless
|
||||
# overridden by LiveProcess's cwd param
|
||||
cwd = process_args.get('cwd')
|
||||
|
||||
if not cwd:
|
||||
from m5 import options
|
||||
cwd = options.outdir
|
||||
process_args['cwd'] = cwd
|
||||
if not isdir(cwd):
|
||||
os.makedirs(cwd)
|
||||
# copy input files to working directory
|
||||
for d in self.inputs_dir:
|
||||
copyfiles(d, cwd)
|
||||
# generate LiveProcess object
|
||||
from m5.objects import LiveProcess
|
||||
return LiveProcess(**process_args)
|
||||
|
||||
def __str__(self):
|
||||
return self.name
|
||||
|
||||
class DefaultBenchmark(Benchmark):
|
||||
def ref(self, isa, os): pass
|
||||
def test(self, isa, os): pass
|
||||
def train(self, isa, os): pass
|
||||
|
||||
class MinneDefaultBenchmark(DefaultBenchmark):
|
||||
def smred(self, isa, os): pass
|
||||
def mdred(self, isa, os): pass
|
||||
def lgred(self, isa, os): pass
|
||||
|
||||
class ammp(MinneDefaultBenchmark):
|
||||
name = 'ammp'
|
||||
number = 188
|
||||
lang = 'C'
|
||||
simpoint = 108*100E6
|
||||
|
||||
class applu(MinneDefaultBenchmark):
|
||||
name = 'applu'
|
||||
number = 173
|
||||
lang = 'F77'
|
||||
simpoint = 2179*100E6
|
||||
|
||||
class apsi(MinneDefaultBenchmark):
|
||||
name = 'apsi'
|
||||
number = 301
|
||||
lang = 'F77'
|
||||
simpoint = 3408*100E6
|
||||
|
||||
class art(DefaultBenchmark):
|
||||
name = 'art'
|
||||
number = 179
|
||||
lang = 'C'
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ '-scanfile', 'c756hel.in',
|
||||
'-trainfile1', 'a10.img',
|
||||
'-stride', '2',
|
||||
'-startx', '134',
|
||||
'-starty', '220',
|
||||
'-endx', '139',
|
||||
'-endy', '225',
|
||||
'-objects', '1' ]
|
||||
self.output = 'test.out'
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ '-scanfile', 'c756hel.in',
|
||||
'-trainfile1', 'a10.img',
|
||||
'-stride', '2',
|
||||
'-startx', '134',
|
||||
'-starty', '220',
|
||||
'-endx', '184',
|
||||
'-endy', '240',
|
||||
'-objects', '3' ]
|
||||
self.output = 'train.out'
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = ['-scanfile', 'c756hel.in',
|
||||
'-trainfile1', 'a10.img',
|
||||
'-stride', '5',
|
||||
'-startx', '134',
|
||||
'-starty', '220',
|
||||
'-endx', '184',
|
||||
'-endy', '240',
|
||||
'-objects', '1' ]
|
||||
self.output = 'lgred.out'
|
||||
|
||||
|
||||
class art110(art):
|
||||
def ref(self, isa, os):
|
||||
self.args = [ '-scanfile', 'c756hel.in',
|
||||
'-trainfile1', 'a10.img',
|
||||
'-trainfile2', 'hc.img',
|
||||
'-stride', '2',
|
||||
'-startx', '110',
|
||||
'-starty', '200',
|
||||
'-endx', '160',
|
||||
'-endy', '240',
|
||||
'-objects', '10' ]
|
||||
self.output = 'ref.1.out'
|
||||
self.simpoint = 340*100E6
|
||||
|
||||
class art470(art):
|
||||
def ref(self, isa, os):
|
||||
self.args = [ '-scanfile', 'c756hel.in',
|
||||
'-trainfile1', 'a10.img',
|
||||
'-trainfile2', 'hc.img',
|
||||
'-stride', '2',
|
||||
'-startx', '470',
|
||||
'-starty', '140',
|
||||
'-endx', '520',
|
||||
'-endy', '180',
|
||||
'-objects', '10' ]
|
||||
self.output = 'ref.2.out'
|
||||
self.simpoint = 365*100E6
|
||||
|
||||
class equake(DefaultBenchmark):
|
||||
name = 'equake'
|
||||
number = 183
|
||||
lang = 'C'
|
||||
simpoint = 812*100E6
|
||||
|
||||
def lgred(self, isa, os): pass
|
||||
|
||||
class facerec(MinneDefaultBenchmark):
|
||||
name = 'facerec'
|
||||
number = 187
|
||||
lang = 'F'
|
||||
simpoint = 375*100E6
|
||||
|
||||
class fma3d(MinneDefaultBenchmark):
|
||||
name = 'fma3d'
|
||||
number = 191
|
||||
lang = 'F'
|
||||
simpoint = 2541*100E6
|
||||
|
||||
class galgel(MinneDefaultBenchmark):
|
||||
name = 'galgel'
|
||||
number = 178
|
||||
lang = 'F'
|
||||
simpoint = 2491*100E6
|
||||
|
||||
class lucas(MinneDefaultBenchmark):
|
||||
name = 'lucas'
|
||||
number = 189
|
||||
lang = 'F'
|
||||
simpoint = 545*100E6
|
||||
|
||||
class mesa(Benchmark):
|
||||
name = 'mesa'
|
||||
number = 177
|
||||
lang = 'C'
|
||||
stdin = None
|
||||
|
||||
def __set_args(self, frames):
|
||||
self.args = [ '-frames', frames, '-meshfile', '%s.in' % self.name,
|
||||
'-ppmfile', '%s.ppm' % self.name ]
|
||||
|
||||
def test(self, isa, os):
|
||||
self.__set_args('10')
|
||||
|
||||
def train(self, isa, os):
|
||||
self.__set_args('500')
|
||||
|
||||
def ref(self, isa, os):
|
||||
self.__set_args('1000')
|
||||
self.simpoint = 1135*100E6
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.__set_args('1')
|
||||
|
||||
class mgrid(MinneDefaultBenchmark):
|
||||
name = 'mgrid'
|
||||
number = 172
|
||||
lang = 'F77'
|
||||
simpoint = 3292*100E6
|
||||
|
||||
class sixtrack(DefaultBenchmark):
|
||||
name = 'sixtrack'
|
||||
number = 200
|
||||
lang = 'F77'
|
||||
simpoint = 3043*100E6
|
||||
|
||||
def lgred(self, isa, os): pass
|
||||
|
||||
class swim(MinneDefaultBenchmark):
|
||||
name = 'swim'
|
||||
number = 171
|
||||
lang = 'F77'
|
||||
simpoint = 2079*100E6
|
||||
|
||||
class wupwise(DefaultBenchmark):
|
||||
name = 'wupwise'
|
||||
number = 168
|
||||
lang = 'F77'
|
||||
simpoint = 3237*100E6
|
||||
|
||||
def lgred(self, isa, os): pass
|
||||
|
||||
class bzip2(DefaultBenchmark):
|
||||
name = 'bzip2'
|
||||
number = 256
|
||||
lang = 'C'
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ 'input.random' ]
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ 'input.compressed' ]
|
||||
|
||||
class bzip2_source(bzip2):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 977*100E6
|
||||
self.args = [ 'input.source', '58' ]
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.source', '1' ]
|
||||
|
||||
class bzip2_graphic(bzip2):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 718*100E6
|
||||
self.args = [ 'input.graphic', '58' ]
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.graphic', '1' ]
|
||||
|
||||
class bzip2_program(bzip2):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 458*100E6
|
||||
self.args = [ 'input.program', '58' ]
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.program', '1' ]
|
||||
|
||||
class crafty(MinneDefaultBenchmark):
|
||||
name = 'crafty'
|
||||
number = 186
|
||||
lang = 'C'
|
||||
simpoint = 774*100E6
|
||||
|
||||
class eon(MinneDefaultBenchmark):
|
||||
name = 'eon'
|
||||
number = 252
|
||||
lang = 'CXX'
|
||||
stdin = None
|
||||
|
||||
class eon_kajiya(eon):
|
||||
args = [ 'chair.control.kajiya', 'chair.camera', 'chair.surfaces',
|
||||
'chair.kajiya.ppm', 'ppm', 'pixels_out.kajiya']
|
||||
output = 'kajiya_log.out'
|
||||
|
||||
|
||||
class eon_cook(eon):
|
||||
args = [ 'chair.control.cook', 'chair.camera', 'chair.surfaces',
|
||||
'chair.cook.ppm', 'ppm', 'pixels_out.cook' ]
|
||||
output = 'cook_log.out'
|
||||
|
||||
class eon_rushmeier(eon):
|
||||
args = [ 'chair.control.rushmeier', 'chair.camera', 'chair.surfaces',
|
||||
'chair.rushmeier.ppm', 'ppm', 'pixels_out.rushmeier' ]
|
||||
output = 'rushmeier_log.out'
|
||||
simpoint = 403*100E6
|
||||
|
||||
class gap(DefaultBenchmark):
|
||||
name = 'gap'
|
||||
number = 254
|
||||
lang = 'C'
|
||||
|
||||
def __set_args(self, size):
|
||||
self.args = [ '-l', './', '-q', '-m', size ]
|
||||
|
||||
def test(self, isa, os):
|
||||
self.__set_args('64M')
|
||||
|
||||
def train(self, isa, os):
|
||||
self.__set_args('128M')
|
||||
|
||||
def ref(self, isa, os):
|
||||
self.__set_args('192M')
|
||||
self.simpoint = 674*100E6
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.__set_args('64M')
|
||||
|
||||
def mdred(self, isa, os):
|
||||
self.__set_args('64M')
|
||||
|
||||
def smred(self, isa, os):
|
||||
self.__set_args('64M')
|
||||
|
||||
class gcc(DefaultBenchmark):
|
||||
name = 'gcc'
|
||||
number = 176
|
||||
lang = 'C'
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ 'cccp.i', '-o', 'cccp.s' ]
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ 'cp-decl.i', '-o', 'cp-decl.s' ]
|
||||
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'c-iterate.i', '-o', 'c-iterate.s' ]
|
||||
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'rdlanal.i', '-o', 'rdlanal.s' ]
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'cp-decl.i', '-o', 'cp-decl.s' ]
|
||||
|
||||
class gcc_166(gcc):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 389*100E6
|
||||
self.args = [ '166.i', '-o', '166.s' ]
|
||||
|
||||
class gcc_200(gcc):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 736*100E6
|
||||
self.args = [ '200.i', '-o', '200.s' ]
|
||||
|
||||
class gcc_expr(gcc):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 36*100E6
|
||||
self.args = [ 'expr.i', '-o', 'expr.s' ]
|
||||
|
||||
class gcc_integrate(gcc):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 4*100E6
|
||||
self.args = [ 'integrate.i', '-o', 'integrate.s' ]
|
||||
|
||||
class gcc_scilab(gcc):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 207*100E6
|
||||
self.args = [ 'scilab.i', '-o', 'scilab.s' ]
|
||||
|
||||
class gzip(DefaultBenchmark):
|
||||
name = 'gzip'
|
||||
number = 164
|
||||
lang = 'C'
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ 'input.compressed', '2' ]
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ 'input.combined', '32' ]
|
||||
|
||||
class gzip_source(gzip):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 334*100E6
|
||||
self.args = [ 'input.source', '1' ]
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'input.source', '1' ]
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'input.source', '1' ]
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.source', '1' ]
|
||||
|
||||
class gzip_log(gzip):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 265*100E6
|
||||
self.args = [ 'input.log', '60' ]
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'input.log', '1' ]
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'input.log', '1' ]
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.log', '1' ]
|
||||
|
||||
class gzip_graphic(gzip):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 653*100E6
|
||||
self.args = [ 'input.graphic', '60' ]
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'input.graphic', '1' ]
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'input.graphic', '1' ]
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.graphic', '1' ]
|
||||
|
||||
class gzip_random(gzip):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 623*100E6
|
||||
self.args = [ 'input.random', '60' ]
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'input.random', '1' ]
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'input.random', '1' ]
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.random', '1' ]
|
||||
|
||||
class gzip_program(gzip):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 1189*100E6
|
||||
self.args = [ 'input.program', '60' ]
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'input.program', '1' ]
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'input.program', '1' ]
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'input.program', '1' ]
|
||||
|
||||
class mcf(MinneDefaultBenchmark):
|
||||
name = 'mcf'
|
||||
number = 181
|
||||
lang = 'C'
|
||||
args = [ 'mcf.in' ]
|
||||
simpoint = 553*100E6
|
||||
|
||||
class parser(MinneDefaultBenchmark):
|
||||
name = 'parser'
|
||||
number = 197
|
||||
lang = 'C'
|
||||
args = [ '2.1.dict', '-batch' ]
|
||||
simpoint = 1146*100E6
|
||||
|
||||
class perlbmk(DefaultBenchmark):
|
||||
name = 'perlbmk'
|
||||
number = 253
|
||||
lang = 'C'
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ '-I.', '-I', 'lib', 'test.pl' ]
|
||||
self.stdin = 'test.in'
|
||||
|
||||
class perlbmk_diffmail(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 141*100E6
|
||||
self.args = [ '-I', 'lib', 'diffmail.pl', '2', '550', '15', '24',
|
||||
'23', '100' ]
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ '-I', 'lib', 'diffmail.pl', '2', '350', '15', '24',
|
||||
'23', '150' ]
|
||||
|
||||
class perlbmk_scrabbl(perlbmk):
|
||||
def train(self, isa, os):
|
||||
self.args = [ '-I.', '-I', 'lib', 'scrabbl.pl' ]
|
||||
self.stdin = 'scrabbl.in'
|
||||
|
||||
class perlbmk_makerand(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 11*100E6
|
||||
self.args = [ '-I', 'lib', 'makerand.pl' ]
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ '-I.', '-I', 'lib', 'lgred.makerand.pl' ]
|
||||
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ '-I.', '-I', 'lib', 'mdred.makerand.pl' ]
|
||||
|
||||
def smred(self, isa, os):
|
||||
self.args = [ '-I.', '-I', 'lib', 'smred.makerand.pl' ]
|
||||
|
||||
class perlbmk_perfect(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 5*100E6
|
||||
self.args = [ '-I', 'lib', 'perfect.pl', 'b', '3', 'm', '4' ]
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ '-I', 'lib', 'perfect.pl', 'b', '3' ]
|
||||
|
||||
class perlbmk_splitmail1(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 405*100E6
|
||||
self.args = [ '-I', 'lib', 'splitmail.pl', '850', '5', '19',
|
||||
'18', '1500' ]
|
||||
|
||||
class perlbmk_splitmail2(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.args = [ '-I', 'lib', 'splitmail.pl', '704', '12', '26',
|
||||
'16', '836' ]
|
||||
|
||||
class perlbmk_splitmail3(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.args = [ '-I', 'lib', 'splitmail.pl', '535', '13', '25',
|
||||
'24', '1091' ]
|
||||
|
||||
class perlbmk_splitmail4(perlbmk):
|
||||
def ref(self, isa, os):
|
||||
self.args = [ '-I', 'lib', 'splitmail.pl', '957', '12', '23',
|
||||
'26', '1014' ]
|
||||
|
||||
class twolf(Benchmark):
|
||||
name = 'twolf'
|
||||
number = 300
|
||||
lang = 'C'
|
||||
stdin = None
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ 'test' ]
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ 'train' ]
|
||||
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 1066*100E6
|
||||
self.args = [ 'ref' ]
|
||||
|
||||
def smred(self, isa, os):
|
||||
self.args = [ 'smred' ]
|
||||
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ 'mdred' ]
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ 'lgred' ]
|
||||
|
||||
class vortex(Benchmark):
|
||||
name = 'vortex'
|
||||
number = 255
|
||||
lang = 'C'
|
||||
stdin = None
|
||||
|
||||
def __init__(self, isa, os, input_set):
|
||||
if (isa == 'alpha' or isa == 'arm'):
|
||||
self.endian = 'lendian'
|
||||
elif (isa == 'sparc' or isa == 'sparc32'):
|
||||
self.endian = 'bendian'
|
||||
else:
|
||||
raise AttributeError, "unknown ISA %s" % isa
|
||||
|
||||
super(vortex, self).__init__(isa, os, input_set)
|
||||
|
||||
def test(self, isa, os):
|
||||
self.args = [ '%s.raw' % self.endian ]
|
||||
self.output = 'vortex.out'
|
||||
|
||||
def train(self, isa, os):
|
||||
self.args = [ '%s.raw' % self.endian ]
|
||||
self.output = 'vortex.out'
|
||||
|
||||
def smred(self, isa, os):
|
||||
self.args = [ '%s.raw' % self.endian ]
|
||||
self.output = 'vortex.out'
|
||||
|
||||
def mdred(self, isa, os):
|
||||
self.args = [ '%s.raw' % self.endian ]
|
||||
self.output = 'vortex.out'
|
||||
|
||||
def lgred(self, isa, os):
|
||||
self.args = [ '%s.raw' % self.endian ]
|
||||
self.output = 'vortex.out'
|
||||
|
||||
class vortex1(vortex):
|
||||
def ref(self, isa, os):
|
||||
self.args = [ '%s1.raw' % self.endian ]
|
||||
self.output = 'vortex1.out'
|
||||
self.simpoint = 271*100E6
|
||||
|
||||
|
||||
class vortex2(vortex):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 1024*100E6
|
||||
self.args = [ '%s2.raw' % self.endian ]
|
||||
self.output = 'vortex2.out'
|
||||
|
||||
class vortex3(vortex):
|
||||
def ref(self, isa, os):
|
||||
self.simpoint = 564*100E6
|
||||
self.args = [ '%s3.raw' % self.endian ]
|
||||
self.output = 'vortex3.out'
|
||||
|
||||
class vpr(MinneDefaultBenchmark):
|
||||
name = 'vpr'
|
||||
number = 175
|
||||
lang = 'C'
|
||||
|
||||
# not sure about vpr minnespec place.in
|
||||
class vpr_place(vpr):
|
||||
args = [ 'net.in', 'arch.in', 'place.out', 'dum.out', '-nodisp',
|
||||
'-place_only', '-init_t', '5', '-exit_t', '0.005',
|
||||
'-alpha_t', '0.9412', '-inner_num', '2' ]
|
||||
output = 'place_log.out'
|
||||
|
||||
class vpr_route(vpr):
|
||||
simpoint = 476*100E6
|
||||
args = [ 'net.in', 'arch.in', 'place.in', 'route.out', '-nodisp',
|
||||
'-route_only', '-route_chan_width', '15',
|
||||
'-pres_fac_mult', '2', '-acc_fac', '1',
|
||||
'-first_iter_pres_fac', '4', '-initial_pres_fac', '8' ]
|
||||
output = 'route_log.out'
|
||||
|
||||
all = [ ammp, applu, apsi, art, art110, art470, equake, facerec, fma3d, galgel,
|
||||
lucas, mesa, mgrid, sixtrack, swim, wupwise, bzip2_source,
|
||||
bzip2_graphic, bzip2_program, crafty, eon_kajiya, eon_cook,
|
||||
eon_rushmeier, gap, gcc_166, gcc_200, gcc_expr, gcc_integrate,
|
||||
gcc_scilab, gzip_source, gzip_log, gzip_graphic, gzip_random,
|
||||
gzip_program, mcf, parser, perlbmk_diffmail, perlbmk_makerand,
|
||||
perlbmk_perfect, perlbmk_splitmail1, perlbmk_splitmail2,
|
||||
perlbmk_splitmail3, perlbmk_splitmail4, twolf, vortex1, vortex2,
|
||||
vortex3, vpr_place, vpr_route ]
|
||||
|
||||
__all__ = [ x.__name__ for x in all ]
|
||||
|
||||
if __name__ == '__main__':
|
||||
from pprint import pprint
|
||||
for bench in all:
|
||||
for input_set in 'ref', 'test', 'train':
|
||||
print 'class: %s' % bench.__name__
|
||||
x = bench('alpha', 'tru64', input_set)
|
||||
print '%s: %s' % (x, input_set)
|
||||
pprint(x.makeLiveProcessArgs())
|
||||
print
|
||||
185
simulators/gem5/configs/example/fs.py
Normal file
185
simulators/gem5/configs/example/fs.py
Normal file
@ -0,0 +1,185 @@
|
||||
# Copyright (c) 2010-2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
import optparse
|
||||
import sys
|
||||
|
||||
import m5
|
||||
from m5.defines import buildEnv
|
||||
from m5.objects import *
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../common')
|
||||
|
||||
from FSConfig import *
|
||||
from SysPaths import *
|
||||
from Benchmarks import *
|
||||
import Simulation
|
||||
import CacheConfig
|
||||
from Caches import *
|
||||
import Options
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
Options.addFSOptions(parser)
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
# driver system CPU is always simple... note this is an assignment of
|
||||
# a class, not an instance.
|
||||
DriveCPUClass = AtomicSimpleCPU
|
||||
drive_mem_mode = 'atomic'
|
||||
|
||||
# system under test can be any CPU
|
||||
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
|
||||
|
||||
TestCPUClass.clock = '2GHz'
|
||||
DriveCPUClass.clock = '2GHz'
|
||||
|
||||
if options.benchmark:
|
||||
try:
|
||||
bm = Benchmarks[options.benchmark]
|
||||
except KeyError:
|
||||
print "Error benchmark %s has not been defined." % options.benchmark
|
||||
print "Valid benchmarks are: %s" % DefinedBenchmarks
|
||||
sys.exit(1)
|
||||
else:
|
||||
if options.dual:
|
||||
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
|
||||
else:
|
||||
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
|
||||
|
||||
np = options.num_cpus
|
||||
|
||||
if buildEnv['TARGET_ISA'] == "alpha":
|
||||
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
|
||||
elif buildEnv['TARGET_ISA'] == "mips":
|
||||
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
|
||||
elif buildEnv['TARGET_ISA'] == "sparc":
|
||||
test_sys = makeSparcSystem(test_mem_mode, bm[0])
|
||||
elif buildEnv['TARGET_ISA'] == "x86":
|
||||
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
|
||||
elif buildEnv['TARGET_ISA'] == "arm":
|
||||
test_sys = makeArmSystem(test_mem_mode,
|
||||
options.machine_type, bm[0],
|
||||
bare_metal=options.bare_metal)
|
||||
else:
|
||||
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
|
||||
|
||||
if options.kernel is not None:
|
||||
test_sys.kernel = binary(options.kernel)
|
||||
|
||||
if options.script is not None:
|
||||
test_sys.readfile = options.script
|
||||
|
||||
test_sys.init_param = options.init_param
|
||||
|
||||
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
|
||||
|
||||
if bm[0]:
|
||||
mem_size = bm[0].mem()
|
||||
else:
|
||||
mem_size = SysConfig().mem()
|
||||
if options.caches or options.l2cache:
|
||||
test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
|
||||
test_sys.iocache.cpu_side = test_sys.iobus.master
|
||||
test_sys.iocache.mem_side = test_sys.membus.slave
|
||||
else:
|
||||
test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
|
||||
ranges = [test_sys.physmem.range])
|
||||
test_sys.iobridge.slave = test_sys.iobus.master
|
||||
test_sys.iobridge.master = test_sys.membus.slave
|
||||
|
||||
# Sanity check
|
||||
if options.fastmem and (options.caches or options.l2cache):
|
||||
fatal("You cannot use fastmem in combination with caches!")
|
||||
|
||||
for i in xrange(np):
|
||||
if options.fastmem:
|
||||
test_sys.cpu[i].fastmem = True
|
||||
if options.checker:
|
||||
test_sys.cpu[i].addCheckerCpu()
|
||||
|
||||
CacheConfig.config_cache(options, test_sys)
|
||||
|
||||
if len(bm) == 2:
|
||||
if buildEnv['TARGET_ISA'] == 'alpha':
|
||||
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
|
||||
elif buildEnv['TARGET_ISA'] == 'mips':
|
||||
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
|
||||
elif buildEnv['TARGET_ISA'] == 'sparc':
|
||||
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
|
||||
elif buildEnv['TARGET_ISA'] == 'x86':
|
||||
drive_sys = makeX86System(drive_mem_mode, np, bm[1])
|
||||
elif buildEnv['TARGET_ISA'] == 'arm':
|
||||
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
|
||||
|
||||
drive_sys.cpu = DriveCPUClass(cpu_id=0)
|
||||
drive_sys.cpu.createInterruptController()
|
||||
drive_sys.cpu.connectAllPorts(drive_sys.membus)
|
||||
if options.fastmem:
|
||||
drive_sys.cpu.fastmem = True
|
||||
if options.kernel is not None:
|
||||
drive_sys.kernel = binary(options.kernel)
|
||||
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
|
||||
ranges = [drive_sys.physmem.range])
|
||||
drive_sys.iobridge.slave = drive_sys.iobus.master
|
||||
drive_sys.iobridge.master = drive_sys.membus.slave
|
||||
|
||||
drive_sys.init_param = options.init_param
|
||||
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
|
||||
elif len(bm) == 1:
|
||||
root = Root(full_system=True, system=test_sys)
|
||||
else:
|
||||
print "Error I don't know how to create more than 2 systems."
|
||||
sys.exit(1)
|
||||
|
||||
if options.timesync:
|
||||
root.time_sync_enable = True
|
||||
|
||||
if options.frame_capture:
|
||||
VncServer.frame_capture = True
|
||||
|
||||
Simulation.setWorkCountOptions(test_sys, options)
|
||||
Simulation.run(options, root, test_sys, FutureClass)
|
||||
199
simulators/gem5/configs/example/memtest.py
Normal file
199
simulators/gem5/configs/example/memtest.py
Normal file
@ -0,0 +1,199 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
|
||||
import optparse
|
||||
import sys
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
|
||||
parser.add_option("-a", "--atomic", action="store_true",
|
||||
help="Use atomic (non-timing) mode")
|
||||
parser.add_option("-b", "--blocking", action="store_true",
|
||||
help="Use blocking caches")
|
||||
parser.add_option("-l", "--maxloads", metavar="N", default=0,
|
||||
help="Stop after N loads")
|
||||
parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
|
||||
metavar="T",
|
||||
help="Stop after T ticks")
|
||||
|
||||
#
|
||||
# The "tree" specification is a colon-separated list of one or more
|
||||
# integers. The first integer is the number of caches/testers
|
||||
# connected directly to main memory. The last integer in the list is
|
||||
# the number of testers associated with the uppermost level of memory
|
||||
# (L1 cache, if there are caches, or main memory if no caches). Thus
|
||||
# if there is only one integer, there are no caches, and the integer
|
||||
# specifies the number of testers connected directly to main memory.
|
||||
# The other integers (if any) specify the number of caches at each
|
||||
# level of the hierarchy between.
|
||||
#
|
||||
# Examples:
|
||||
#
|
||||
# "2:1" Two caches connected to memory with a single tester behind each
|
||||
# (single-level hierarchy, two testers total)
|
||||
#
|
||||
# "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
|
||||
#
|
||||
parser.add_option("-t", "--treespec", type="string", default="8:1",
|
||||
help="Colon-separated multilevel tree specification, "
|
||||
"see script comments for details "
|
||||
"[default: %default]")
|
||||
|
||||
parser.add_option("--force-bus", action="store_true",
|
||||
help="Use bus between levels even with single cache")
|
||||
|
||||
parser.add_option("-f", "--functional", type="int", default=0,
|
||||
metavar="PCT",
|
||||
help="Target percentage of functional accesses "
|
||||
"[default: %default]")
|
||||
parser.add_option("-u", "--uncacheable", type="int", default=0,
|
||||
metavar="PCT",
|
||||
help="Target percentage of uncacheable accesses "
|
||||
"[default: %default]")
|
||||
|
||||
parser.add_option("--progress", type="int", default=1000,
|
||||
metavar="NLOADS",
|
||||
help="Progress message interval "
|
||||
"[default: %default]")
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
block_size = 64
|
||||
|
||||
try:
|
||||
treespec = [int(x) for x in options.treespec.split(':')]
|
||||
numtesters = reduce(lambda x,y: x*y, treespec)
|
||||
except:
|
||||
print "Error parsing treespec option"
|
||||
sys.exit(1)
|
||||
|
||||
if numtesters > block_size:
|
||||
print "Error: Number of testers limited to %s because of false sharing" \
|
||||
% (block_size)
|
||||
sys.exit(1)
|
||||
|
||||
if len(treespec) < 1:
|
||||
print "Error parsing treespec"
|
||||
sys.exit(1)
|
||||
|
||||
# define prototype L1 cache
|
||||
proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
|
||||
latency = '1ns', tgts_per_mshr = 8)
|
||||
|
||||
if options.blocking:
|
||||
proto_l1.mshrs = 1
|
||||
else:
|
||||
proto_l1.mshrs = 4
|
||||
|
||||
# build a list of prototypes, one for each level of treespec, starting
|
||||
# at the end (last entry is tester objects)
|
||||
prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
|
||||
percent_functional=options.functional,
|
||||
percent_uncacheable=options.uncacheable,
|
||||
progress_interval=options.progress) ]
|
||||
|
||||
# next comes L1 cache, if any
|
||||
if len(treespec) > 1:
|
||||
prototypes.insert(0, proto_l1)
|
||||
|
||||
# now add additional cache levels (if any) by scaling L1 params
|
||||
for scale in treespec[:-2]:
|
||||
# clone previous level and update params
|
||||
prev = prototypes[0]
|
||||
next = prev()
|
||||
next.size = prev.size * scale
|
||||
next.latency = prev.latency * 10
|
||||
next.assoc = prev.assoc * scale
|
||||
next.mshrs = prev.mshrs * scale
|
||||
prototypes.insert(0, next)
|
||||
|
||||
# system simulated
|
||||
system = System(funcmem = SimpleMemory(in_addr_map = False),
|
||||
physmem = SimpleMemory(latency = "100ns"))
|
||||
|
||||
def make_level(spec, prototypes, attach_obj, attach_port):
|
||||
fanout = spec[0]
|
||||
parent = attach_obj # use attach obj as config parent too
|
||||
if len(spec) > 1 and (fanout > 1 or options.force_bus):
|
||||
port = getattr(attach_obj, attach_port)
|
||||
new_bus = CoherentBus(clock="500MHz", width=16)
|
||||
if (port.role == 'MASTER'):
|
||||
new_bus.slave = port
|
||||
attach_port = "master"
|
||||
else:
|
||||
new_bus.master = port
|
||||
attach_port = "slave"
|
||||
parent.cpu_side_bus = new_bus
|
||||
attach_obj = new_bus
|
||||
objs = [prototypes[0]() for i in xrange(fanout)]
|
||||
if len(spec) > 1:
|
||||
# we just built caches, more levels to go
|
||||
parent.cache = objs
|
||||
for cache in objs:
|
||||
cache.mem_side = getattr(attach_obj, attach_port)
|
||||
make_level(spec[1:], prototypes[1:], cache, "cpu_side")
|
||||
else:
|
||||
# we just built the MemTest objects
|
||||
parent.cpu = objs
|
||||
for t in objs:
|
||||
t.test = getattr(attach_obj, attach_port)
|
||||
t.functional = system.funcmem.port
|
||||
|
||||
make_level(treespec, prototypes, system.physmem, "port")
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
||||
root = Root( full_system = False, system = system )
|
||||
if options.atomic:
|
||||
root.system.mem_mode = 'atomic'
|
||||
else:
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# The system port is never used in the tester so merely connect it
|
||||
# to avoid problems
|
||||
root.system.system_port = root.system.physmem.port
|
||||
|
||||
# Not much point in this being higher than the L1 latency
|
||||
m5.ticks.setGlobalFrequency('1ns')
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
125
simulators/gem5/configs/example/ruby_direct_test.py
Normal file
125
simulators/gem5/configs/example/ruby_direct_test.py
Normal file
@ -0,0 +1,125 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
# Brad Beckmann
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
from m5.util import addToPath
|
||||
import os, optparse, sys
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
|
||||
import Options
|
||||
import Ruby
|
||||
|
||||
# Get paths we might need. It's expected this file is in m5/configs/example.
|
||||
config_path = os.path.dirname(os.path.abspath(__file__))
|
||||
config_root = os.path.dirname(config_path)
|
||||
m5_root = os.path.dirname(config_root)
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
|
||||
parser.add_option("-l", "--requests", metavar="N", default=100,
|
||||
help="Stop after N requests")
|
||||
parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
|
||||
help="Wakeup every N cycles")
|
||||
parser.add_option("--test-type", type="string", default="SeriesGetx",
|
||||
help="SeriesGetx|SeriesGets|Invalidate")
|
||||
|
||||
#
|
||||
# Add the ruby specific and protocol specific options
|
||||
#
|
||||
Ruby.define_options(parser)
|
||||
|
||||
execfile(os.path.join(config_root, "common", "Options.py"))
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
#
|
||||
# Select the direct test generator
|
||||
#
|
||||
if options.test_type == "SeriesGetx":
|
||||
generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
|
||||
issue_writes = True)
|
||||
elif options.test_type == "SeriesGets":
|
||||
generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
|
||||
issue_writes = False)
|
||||
elif options.test_type == "Invalidate":
|
||||
generator = InvalidateGenerator(num_cpus = options.num_cpus)
|
||||
else:
|
||||
print "Error: unknown direct test generator"
|
||||
sys.exit(1)
|
||||
|
||||
#
|
||||
# Create the M5 system. Note that the Memory Object isn't
|
||||
# actually used by the rubytester, but is included to support the
|
||||
# M5 memory size == Ruby memory size checks
|
||||
#
|
||||
system = System(physmem = SimpleMemory())
|
||||
|
||||
#
|
||||
# Create the ruby random tester
|
||||
#
|
||||
system.tester = RubyDirectedTester(requests_to_complete = \
|
||||
options.requests,
|
||||
generator = generator)
|
||||
|
||||
Ruby.create_system(options, system)
|
||||
|
||||
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
|
||||
|
||||
for ruby_port in system.ruby._cpu_ruby_ports:
|
||||
#
|
||||
# Tie the ruby tester ports to the ruby cpu ports
|
||||
#
|
||||
system.tester.cpuPort = ruby_port.slave
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# Not much point in this being higher than the L1 latency
|
||||
m5.ticks.setGlobalFrequency('1ns')
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
116
simulators/gem5/configs/example/ruby_fs.py
Normal file
116
simulators/gem5/configs/example/ruby_fs.py
Normal file
@ -0,0 +1,116 @@
|
||||
# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
#
|
||||
# Full system configuraiton for ruby
|
||||
#
|
||||
|
||||
import optparse
|
||||
import sys
|
||||
|
||||
import m5
|
||||
from m5.defines import buildEnv
|
||||
from m5.objects import *
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
|
||||
import Ruby
|
||||
|
||||
from FSConfig import *
|
||||
from SysPaths import *
|
||||
from Benchmarks import *
|
||||
import Options
|
||||
import Simulation
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
Options.addFSOptions(parser)
|
||||
|
||||
# Add the ruby specific and protocol specific options
|
||||
Ruby.define_options(parser)
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
options.ruby = True
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
if options.benchmark:
|
||||
try:
|
||||
bm = Benchmarks[options.benchmark]
|
||||
except KeyError:
|
||||
print "Error benchmark %s has not been defined." % options.benchmark
|
||||
print "Valid benchmarks are: %s" % DefinedBenchmarks
|
||||
sys.exit(1)
|
||||
else:
|
||||
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
|
||||
|
||||
# Check for timing mode because ruby does not support atomic accesses
|
||||
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
|
||||
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
|
||||
sys.exit(1)
|
||||
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
|
||||
|
||||
CPUClass.clock = options.clock
|
||||
|
||||
if buildEnv['TARGET_ISA'] == "alpha":
|
||||
system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
|
||||
elif buildEnv['TARGET_ISA'] == "x86":
|
||||
system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
|
||||
Simulation.setWorkCountOptions(system, options)
|
||||
else:
|
||||
fatal("incapable of building non-alpha or non-x86 full system!")
|
||||
|
||||
if options.kernel is not None:
|
||||
system.kernel = binary(options.kernel)
|
||||
|
||||
if options.script is not None:
|
||||
system.readfile = options.script
|
||||
|
||||
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
|
||||
Ruby.create_system(options, system, system.piobus, system._dma_ports)
|
||||
|
||||
for (i, cpu) in enumerate(system.cpu):
|
||||
#
|
||||
# Tie the cpu ports to the correct ruby system ports
|
||||
#
|
||||
cpu.createInterruptController()
|
||||
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
|
||||
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
|
||||
if buildEnv['TARGET_ISA'] == "x86":
|
||||
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
|
||||
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
|
||||
cpu.interrupts.pio = system.piobus.master
|
||||
cpu.interrupts.int_master = system.piobus.slave
|
||||
cpu.interrupts.int_slave = system.piobus.master
|
||||
|
||||
root = Root(full_system = True, system = system)
|
||||
Simulation.run(options, root, system, FutureClass)
|
||||
180
simulators/gem5/configs/example/ruby_mem_test.py
Normal file
180
simulators/gem5/configs/example/ruby_mem_test.py
Normal file
@ -0,0 +1,180 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
# Brad Beckmann
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
from m5.util import addToPath
|
||||
import os, optparse, sys
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
|
||||
import Options
|
||||
import Ruby
|
||||
|
||||
# Get paths we might need. It's expected this file is in m5/configs/example.
|
||||
config_path = os.path.dirname(os.path.abspath(__file__))
|
||||
config_root = os.path.dirname(config_path)
|
||||
m5_root = os.path.dirname(config_root)
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
|
||||
parser.add_option("-l", "--maxloads", metavar="N", default=0,
|
||||
help="Stop after N loads")
|
||||
parser.add_option("--progress", type="int", default=1000,
|
||||
metavar="NLOADS",
|
||||
help="Progress message interval "
|
||||
"[default: %default]")
|
||||
parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
|
||||
parser.add_option("--functional", type="int", default=0,
|
||||
help="percentage of accesses that should be functional")
|
||||
parser.add_option("--suppress-func-warnings", action="store_true",
|
||||
help="suppress warnings when functional accesses fail")
|
||||
|
||||
#
|
||||
# Add the ruby specific and protocol specific options
|
||||
#
|
||||
Ruby.define_options(parser)
|
||||
|
||||
execfile(os.path.join(config_root, "common", "Options.py"))
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
#
|
||||
# Set the default cache size and associativity to be very small to encourage
|
||||
# races between requests and writebacks.
|
||||
#
|
||||
options.l1d_size="256B"
|
||||
options.l1i_size="256B"
|
||||
options.l2_size="512B"
|
||||
options.l3_size="1kB"
|
||||
options.l1d_assoc=2
|
||||
options.l1i_assoc=2
|
||||
options.l2_assoc=2
|
||||
options.l3_assoc=2
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
block_size = 64
|
||||
|
||||
if options.num_cpus > block_size:
|
||||
print "Error: Number of testers %d limited to %d because of false sharing" \
|
||||
% (options.num_cpus, block_size)
|
||||
sys.exit(1)
|
||||
|
||||
#
|
||||
# Currently ruby does not support atomic or uncacheable accesses
|
||||
#
|
||||
cpus = [ MemTest(atomic = False,
|
||||
max_loads = options.maxloads,
|
||||
issue_dmas = False,
|
||||
percent_functional = options.functional,
|
||||
percent_uncacheable = 0,
|
||||
progress_interval = options.progress,
|
||||
suppress_func_warnings = options.suppress_func_warnings) \
|
||||
for i in xrange(options.num_cpus) ]
|
||||
|
||||
system = System(cpu = cpus,
|
||||
funcmem = SimpleMemory(in_addr_map = False),
|
||||
physmem = SimpleMemory())
|
||||
|
||||
if options.num_dmas > 0:
|
||||
dmas = [ MemTest(atomic = False,
|
||||
max_loads = options.maxloads,
|
||||
issue_dmas = True,
|
||||
percent_functional = 0,
|
||||
percent_uncacheable = 0,
|
||||
progress_interval = options.progress,
|
||||
suppress_func_warnings =
|
||||
not options.suppress_func_warnings) \
|
||||
for i in xrange(options.num_dmas) ]
|
||||
system.dma_devices = dmas
|
||||
else:
|
||||
dmas = []
|
||||
|
||||
dma_ports = []
|
||||
for (i, dma) in enumerate(dmas):
|
||||
dma_ports.append(dma.test)
|
||||
Ruby.create_system(options, system, dma_ports = dma_ports)
|
||||
|
||||
#
|
||||
# The tester is most effective when randomization is turned on and
|
||||
# artifical delay is randomly inserted on messages
|
||||
#
|
||||
system.ruby.randomization = True
|
||||
|
||||
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
|
||||
|
||||
for (i, cpu) in enumerate(cpus):
|
||||
#
|
||||
# Tie the cpu memtester ports to the correct system ports
|
||||
#
|
||||
cpu.test = system.ruby._cpu_ruby_ports[i].slave
|
||||
cpu.functional = system.funcmem.port
|
||||
|
||||
#
|
||||
# Since the memtester is incredibly bursty, increase the deadlock
|
||||
# threshold to 5 million cycles
|
||||
#
|
||||
system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
|
||||
|
||||
#
|
||||
# Ruby doesn't need the backing image of memory when running with
|
||||
# the tester.
|
||||
#
|
||||
system.ruby._cpu_ruby_ports[i].access_phys_mem = False
|
||||
|
||||
for (i, dma) in enumerate(dmas):
|
||||
#
|
||||
# Tie the dma memtester ports to the correct functional port
|
||||
# Note that the test port has already been connected to the dma_sequencer
|
||||
#
|
||||
dma.functional = system.funcmem.port
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# Not much point in this being higher than the L1 latency
|
||||
m5.ticks.setGlobalFrequency('1ns')
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
136
simulators/gem5/configs/example/ruby_network_test.py
Normal file
136
simulators/gem5/configs/example/ruby_network_test.py
Normal file
@ -0,0 +1,136 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2010 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
# Tushar Krishna
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
from m5.util import addToPath
|
||||
import os, optparse, sys
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
|
||||
import Options
|
||||
import Ruby
|
||||
|
||||
# Get paths we might need. It's expected this file is in m5/configs/example.
|
||||
config_path = os.path.dirname(os.path.abspath(__file__))
|
||||
config_root = os.path.dirname(config_path)
|
||||
m5_root = os.path.dirname(config_root)
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
|
||||
parser.add_option("--synthetic", type="int", default=0,
|
||||
help="Synthetic Traffic type. 0 = Uniform Random,\
|
||||
1 = Tornado, 2 = Bit Complement")
|
||||
|
||||
parser.add_option("-i", "--injectionrate", type="float", default=0.1,
|
||||
metavar="I",
|
||||
help="Injection rate in packets per cycle per node. \
|
||||
Takes decimal value between 0 to 1 (eg. 0.225). \
|
||||
Number of digits after 0 depends upon --precision.")
|
||||
|
||||
parser.add_option("--precision", type="int", default=3,
|
||||
help="Number of digits of precision after decimal point\
|
||||
for injection rate")
|
||||
|
||||
parser.add_option("--sim-cycles", type="int", default=1000,
|
||||
help="Number of simulation cycles")
|
||||
|
||||
parser.add_option("--fixed-pkts", action="store_true",
|
||||
help="Network_test: inject --maxpackets and stop")
|
||||
|
||||
parser.add_option("--maxpackets", type="int", default=1,
|
||||
help="Stop injecting after --maxpackets. \
|
||||
Works only with --fixed-pkts")
|
||||
|
||||
#
|
||||
# Add the ruby specific and protocol specific options
|
||||
#
|
||||
Ruby.define_options(parser)
|
||||
|
||||
execfile(os.path.join(config_root, "common", "Options.py"))
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
block_size = 64
|
||||
|
||||
if options.num_cpus > block_size:
|
||||
print "Error: Number of cores %d limited to %d because of false sharing" \
|
||||
% (options.num_cpus, block_size)
|
||||
sys.exit(1)
|
||||
|
||||
|
||||
cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
|
||||
max_packets=options.maxpackets,
|
||||
sim_cycles=options.sim_cycles,
|
||||
traffic_type=options.synthetic,
|
||||
inj_rate=options.injectionrate,
|
||||
precision=options.precision,
|
||||
num_memories=options.num_dirs) \
|
||||
for i in xrange(options.num_cpus) ]
|
||||
|
||||
# create the desired simulated system
|
||||
system = System(cpu = cpus,
|
||||
physmem = SimpleMemory())
|
||||
|
||||
Ruby.create_system(options, system)
|
||||
|
||||
i = 0
|
||||
for ruby_port in system.ruby._cpu_ruby_ports:
|
||||
#
|
||||
# Tie the cpu test ports to the ruby cpu port
|
||||
#
|
||||
cpus[i].test = ruby_port.slave
|
||||
ruby_port.access_phys_mem = False
|
||||
|
||||
i += 1
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# Not much point in this being higher than the L1 latency
|
||||
m5.ticks.setGlobalFrequency('1ns')
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
149
simulators/gem5/configs/example/ruby_random_test.py
Normal file
149
simulators/gem5/configs/example/ruby_random_test.py
Normal file
@ -0,0 +1,149 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
# Brad Beckmann
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
from m5.util import addToPath
|
||||
import os, optparse, sys
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
|
||||
import Options
|
||||
import Ruby
|
||||
|
||||
# Get paths we might need. It's expected this file is in m5/configs/example.
|
||||
config_path = os.path.dirname(os.path.abspath(__file__))
|
||||
config_root = os.path.dirname(config_path)
|
||||
m5_root = os.path.dirname(config_root)
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
|
||||
parser.add_option("-l", "--checks", metavar="N", default=100,
|
||||
help="Stop after N checks (loads)")
|
||||
parser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
|
||||
help="Wakeup every N cycles")
|
||||
|
||||
#
|
||||
# Add the ruby specific and protocol specific options
|
||||
#
|
||||
Ruby.define_options(parser)
|
||||
|
||||
execfile(os.path.join(config_root, "common", "Options.py"))
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
#
|
||||
# Set the default cache size and associativity to be very small to encourage
|
||||
# races between requests and writebacks.
|
||||
#
|
||||
options.l1d_size="256B"
|
||||
options.l1i_size="256B"
|
||||
options.l2_size="512B"
|
||||
options.l3_size="1kB"
|
||||
options.l1d_assoc=2
|
||||
options.l1i_assoc=2
|
||||
options.l2_assoc=2
|
||||
options.l3_assoc=2
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
#
|
||||
# Create the ruby random tester
|
||||
#
|
||||
|
||||
# Check the protocol
|
||||
check_flush = False
|
||||
if buildEnv['PROTOCOL'] == 'MOESI_hammer':
|
||||
check_flush = True
|
||||
|
||||
tester = RubyTester(check_flush = check_flush,
|
||||
checks_to_complete = options.checks,
|
||||
wakeup_frequency = options.wakeup_freq,
|
||||
num_cpus = options.num_cpus)
|
||||
|
||||
#
|
||||
# Create the M5 system. Note that the Memory Object isn't
|
||||
# actually used by the rubytester, but is included to support the
|
||||
# M5 memory size == Ruby memory size checks
|
||||
#
|
||||
system = System(tester = tester, physmem = SimpleMemory())
|
||||
|
||||
Ruby.create_system(options, system)
|
||||
|
||||
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
|
||||
|
||||
#
|
||||
# The tester is most effective when randomization is turned on and
|
||||
# artifical delay is randomly inserted on messages
|
||||
#
|
||||
system.ruby.randomization = True
|
||||
|
||||
for ruby_port in system.ruby._cpu_ruby_ports:
|
||||
#
|
||||
# Tie the ruby tester ports to the ruby cpu read and write ports
|
||||
#
|
||||
if ruby_port.support_data_reqs:
|
||||
tester.cpuDataPort = ruby_port.slave
|
||||
if ruby_port.support_inst_reqs:
|
||||
tester.cpuInstPort = ruby_port.slave
|
||||
|
||||
#
|
||||
# Tell each sequencer this is the ruby tester so that it
|
||||
# copies the subblock back to the checker
|
||||
#
|
||||
ruby_port.using_ruby_tester = True
|
||||
|
||||
#
|
||||
# Ruby doesn't need the backing image of memory when running with
|
||||
# the tester.
|
||||
#
|
||||
ruby_port.access_phys_mem = False
|
||||
|
||||
# -----------------------
|
||||
# run simulation
|
||||
# -----------------------
|
||||
|
||||
root = Root( full_system = False, system = system )
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# Not much point in this being higher than the L1 latency
|
||||
m5.ticks.setGlobalFrequency('1ns')
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
201
simulators/gem5/configs/example/se.py
Normal file
201
simulators/gem5/configs/example/se.py
Normal file
@ -0,0 +1,201 @@
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
|
||||
# Simple test script
|
||||
#
|
||||
# "m5 test.py"
|
||||
|
||||
import optparse
|
||||
import sys
|
||||
|
||||
import m5
|
||||
from m5.defines import buildEnv
|
||||
from m5.objects import *
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
|
||||
import Options
|
||||
import Ruby
|
||||
import Simulation
|
||||
import CacheConfig
|
||||
from Caches import *
|
||||
from cpu2000 import *
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
Options.addCommonOptions(parser)
|
||||
Options.addSEOptions(parser)
|
||||
|
||||
if '--ruby' in sys.argv:
|
||||
Ruby.define_options(parser)
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
multiprocesses = []
|
||||
apps = []
|
||||
|
||||
if options.bench:
|
||||
apps = options.bench.split("-")
|
||||
if len(apps) != options.num_cpus:
|
||||
print "number of benchmarks not equal to set num_cpus!"
|
||||
sys.exit(1)
|
||||
|
||||
for app in apps:
|
||||
try:
|
||||
if buildEnv['TARGET_ISA'] == 'alpha':
|
||||
exec("workload = %s('alpha', 'tru64', 'ref')" % app)
|
||||
else:
|
||||
exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
|
||||
multiprocesses.append(workload.makeLiveProcess())
|
||||
except:
|
||||
print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
|
||||
sys.exit(1)
|
||||
elif options.cmd:
|
||||
process = LiveProcess()
|
||||
process.executable = options.cmd
|
||||
process.cmd = [options.cmd] + options.options.split()
|
||||
multiprocesses.append(process)
|
||||
else:
|
||||
print >> sys.stderr, "No workload specified. Exiting!\n"
|
||||
sys.exit(1)
|
||||
|
||||
|
||||
if options.input != "":
|
||||
process.input = options.input
|
||||
if options.output != "":
|
||||
process.output = options.output
|
||||
if options.errout != "":
|
||||
process.errout = options.errout
|
||||
|
||||
|
||||
# By default, set workload to path of user-specified binary
|
||||
workloads = options.cmd
|
||||
numThreads = 1
|
||||
|
||||
if options.cpu_type == "detailed" or options.cpu_type == "inorder":
|
||||
#check for SMT workload
|
||||
workloads = options.cmd.split(';')
|
||||
if len(workloads) > 1:
|
||||
process = []
|
||||
smt_idx = 0
|
||||
inputs = []
|
||||
outputs = []
|
||||
errouts = []
|
||||
|
||||
if options.input != "":
|
||||
inputs = options.input.split(';')
|
||||
if options.output != "":
|
||||
outputs = options.output.split(';')
|
||||
if options.errout != "":
|
||||
errouts = options.errout.split(';')
|
||||
|
||||
for wrkld in workloads:
|
||||
smt_process = LiveProcess()
|
||||
smt_process.executable = wrkld
|
||||
smt_process.cmd = wrkld + " " + options.options
|
||||
if inputs and inputs[smt_idx]:
|
||||
smt_process.input = inputs[smt_idx]
|
||||
if outputs and outputs[smt_idx]:
|
||||
smt_process.output = outputs[smt_idx]
|
||||
if errouts and errouts[smt_idx]:
|
||||
smt_process.errout = errouts[smt_idx]
|
||||
process += [smt_process, ]
|
||||
smt_idx += 1
|
||||
numThreads = len(workloads)
|
||||
|
||||
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
|
||||
CPUClass.clock = '2GHz'
|
||||
CPUClass.numThreads = numThreads;
|
||||
|
||||
np = options.num_cpus
|
||||
|
||||
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
|
||||
physmem = SimpleMemory(range=AddrRange("512MB")),
|
||||
membus = CoherentBus(), mem_mode = test_mem_mode)
|
||||
|
||||
# Sanity check
|
||||
if options.fastmem and (options.caches or options.l2cache):
|
||||
fatal("You cannot use fastmem in combination with caches!")
|
||||
|
||||
for i in xrange(np):
|
||||
if len(multiprocesses) == 1:
|
||||
system.cpu[i].workload = multiprocesses[0]
|
||||
else:
|
||||
system.cpu[i].workload = multiprocesses[i]
|
||||
|
||||
if options.fastmem:
|
||||
system.cpu[i].fastmem = True
|
||||
|
||||
if options.checker:
|
||||
system.cpu[i].addCheckerCpu()
|
||||
|
||||
if options.ruby:
|
||||
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
|
||||
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
|
||||
sys.exit(1)
|
||||
|
||||
options.use_map = True
|
||||
Ruby.create_system(options, system)
|
||||
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
|
||||
|
||||
for i in xrange(np):
|
||||
ruby_port = system.ruby._cpu_ruby_ports[i]
|
||||
|
||||
# Create the interrupt controller and connect its ports to Ruby
|
||||
system.cpu[i].createInterruptController()
|
||||
system.cpu[i].interrupts.pio = ruby_port.master
|
||||
system.cpu[i].interrupts.int_master = ruby_port.slave
|
||||
system.cpu[i].interrupts.int_slave = ruby_port.master
|
||||
|
||||
# Connect the cpu's cache ports to Ruby
|
||||
system.cpu[i].icache_port = ruby_port.slave
|
||||
system.cpu[i].dcache_port = ruby_port.slave
|
||||
else:
|
||||
system.system_port = system.membus.slave
|
||||
system.physmem.port = system.membus.master
|
||||
CacheConfig.config_cache(options, system)
|
||||
|
||||
root = Root(full_system = False, system = system)
|
||||
Simulation.run(options, root, system, FutureClass)
|
||||
188
simulators/gem5/configs/ruby/MESI_CMP_directory.py
Normal file
188
simulators/gem5/configs/ruby/MESI_CMP_directory.py
Normal file
@ -0,0 +1,188 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import math
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
|
||||
#
|
||||
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
|
||||
#
|
||||
class L1Cache(RubyCache):
|
||||
latency = 3
|
||||
|
||||
#
|
||||
# Note: the L2 Cache latency is not currently used
|
||||
#
|
||||
class L2Cache(RubyCache):
|
||||
latency = 15
|
||||
|
||||
def define_options(parser):
|
||||
return
|
||||
|
||||
def create_system(options, system, piobus, dma_ports, ruby_system):
|
||||
|
||||
if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
|
||||
panic("This script requires the MESI_CMP_directory protocol to be built.")
|
||||
|
||||
cpu_sequencers = []
|
||||
|
||||
#
|
||||
# The ruby network creation expects the list of nodes in the system to be
|
||||
# consistent with the NetDest list. Therefore the l1 controller nodes must be
|
||||
# listed before the directory nodes and directory nodes before dma nodes, etc.
|
||||
#
|
||||
l1_cntrl_nodes = []
|
||||
l2_cntrl_nodes = []
|
||||
dir_cntrl_nodes = []
|
||||
dma_cntrl_nodes = []
|
||||
|
||||
#
|
||||
# Must create the individual controllers before the network to ensure the
|
||||
# controller constructors are called before the network constructor
|
||||
#
|
||||
l2_bits = int(math.log(options.num_l2caches, 2))
|
||||
block_size_bits = int(math.log(options.cacheline_size, 2))
|
||||
|
||||
cntrl_count = 0
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l1i_cache = L1Cache(size = options.l1i_size,
|
||||
assoc = options.l1i_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
l1d_cache = L1Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
|
||||
l1_cntrl = L1Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L1IcacheMemory = l1i_cache,
|
||||
L1DcacheMemory = l1d_cache,
|
||||
l2_select_num_bits = l2_bits,
|
||||
send_evictions = (
|
||||
options.cpu_type == "detailed"),
|
||||
ruby_system = ruby_system)
|
||||
|
||||
cpu_seq = RubySequencer(version = i,
|
||||
icache = l1i_cache,
|
||||
dcache = l1d_cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
l1_cntrl.sequencer = cpu_seq
|
||||
|
||||
if piobus != None:
|
||||
cpu_seq.pio_port = piobus.slave
|
||||
|
||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||
|
||||
#
|
||||
# Add controllers and sequencers to the appropriate lists
|
||||
#
|
||||
cpu_sequencers.append(cpu_seq)
|
||||
l1_cntrl_nodes.append(l1_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
l2_index_start = block_size_bits + l2_bits
|
||||
|
||||
for i in xrange(options.num_l2caches):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l2_cache = L2Cache(size = options.l2_size,
|
||||
assoc = options.l2_assoc,
|
||||
start_index_bit = l2_index_start)
|
||||
|
||||
l2_cntrl = L2Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L2cacheMemory = l2_cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.l2_cntrl%d = l2_cntrl" % i)
|
||||
l2_cntrl_nodes.append(l2_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
mem_module_size = phys_mem_size / options.num_dirs
|
||||
|
||||
for i in xrange(options.num_dirs):
|
||||
#
|
||||
# Create the Ruby objects associated with the directory controller
|
||||
#
|
||||
|
||||
mem_cntrl = RubyMemoryControl(version = i)
|
||||
|
||||
dir_size = MemorySize('0B')
|
||||
dir_size.value = mem_module_size
|
||||
|
||||
dir_cntrl = Directory_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
directory = \
|
||||
RubyDirectoryMemory(version = i,
|
||||
size = dir_size,
|
||||
use_map =
|
||||
options.use_map),
|
||||
memBuffer = mem_cntrl,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dir_cntrl%d = dir_cntrl" % i)
|
||||
dir_cntrl_nodes.append(dir_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
for i, dma_port in enumerate(dma_ports):
|
||||
#
|
||||
# Create the Ruby objects associated with the dma controller
|
||||
#
|
||||
dma_seq = DMASequencer(version = i,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
dma_cntrl = DMA_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
dma_sequencer = dma_seq,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
|
||||
dma_cntrl_nodes.append(dma_cntrl)
|
||||
cntrl_count += 1
|
||||
|
||||
all_cntrls = l1_cntrl_nodes + \
|
||||
l2_cntrl_nodes + \
|
||||
dir_cntrl_nodes + \
|
||||
dma_cntrl_nodes
|
||||
|
||||
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|
||||
158
simulators/gem5/configs/ruby/MI_example.py
Normal file
158
simulators/gem5/configs/ruby/MI_example.py
Normal file
@ -0,0 +1,158 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import math
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
|
||||
#
|
||||
# Note: the cache latency is only used by the sequencer on fast path hits
|
||||
#
|
||||
class Cache(RubyCache):
|
||||
latency = 3
|
||||
|
||||
def define_options(parser):
|
||||
return
|
||||
|
||||
def create_system(options, system, piobus, dma_ports, ruby_system):
|
||||
|
||||
if buildEnv['PROTOCOL'] != 'MI_example':
|
||||
panic("This script requires the MI_example protocol to be built.")
|
||||
|
||||
cpu_sequencers = []
|
||||
|
||||
#
|
||||
# The ruby network creation expects the list of nodes in the system to be
|
||||
# consistent with the NetDest list. Therefore the l1 controller nodes must be
|
||||
# listed before the directory nodes and directory nodes before dma nodes, etc.
|
||||
#
|
||||
l1_cntrl_nodes = []
|
||||
dir_cntrl_nodes = []
|
||||
dma_cntrl_nodes = []
|
||||
|
||||
#
|
||||
# Must create the individual controllers before the network to ensure the
|
||||
# controller constructors are called before the network constructor
|
||||
#
|
||||
block_size_bits = int(math.log(options.cacheline_size, 2))
|
||||
|
||||
cntrl_count = 0
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
# Only one cache exists for this protocol, so by default use the L1D
|
||||
# config parameters.
|
||||
#
|
||||
cache = Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
|
||||
#
|
||||
# Only one unified L1 cache exists. Can cache instructions and data.
|
||||
#
|
||||
l1_cntrl = L1Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
cacheMemory = cache,
|
||||
send_evictions = (
|
||||
options.cpu_type == "detailed"),
|
||||
ruby_system = ruby_system)
|
||||
|
||||
cpu_seq = RubySequencer(version = i,
|
||||
icache = cache,
|
||||
dcache = cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
l1_cntrl.sequencer = cpu_seq
|
||||
|
||||
if piobus != None:
|
||||
cpu_seq.pio_port = piobus.slave
|
||||
|
||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||
#
|
||||
# Add controllers and sequencers to the appropriate lists
|
||||
#
|
||||
cpu_sequencers.append(cpu_seq)
|
||||
l1_cntrl_nodes.append(l1_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
mem_module_size = phys_mem_size / options.num_dirs
|
||||
|
||||
for i in xrange(options.num_dirs):
|
||||
#
|
||||
# Create the Ruby objects associated with the directory controller
|
||||
#
|
||||
|
||||
mem_cntrl = RubyMemoryControl(version = i)
|
||||
|
||||
dir_size = MemorySize('0B')
|
||||
dir_size.value = mem_module_size
|
||||
|
||||
dir_cntrl = Directory_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
directory = \
|
||||
RubyDirectoryMemory( \
|
||||
version = i,
|
||||
size = dir_size,
|
||||
use_map = options.use_map,
|
||||
map_levels = \
|
||||
options.map_levels),
|
||||
memBuffer = mem_cntrl,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dir_cntrl%d = dir_cntrl" % i)
|
||||
dir_cntrl_nodes.append(dir_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
for i, dma_port in enumerate(dma_ports):
|
||||
#
|
||||
# Create the Ruby objects associated with the dma controller
|
||||
#
|
||||
dma_seq = DMASequencer(version = i,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
dma_cntrl = DMA_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
dma_sequencer = dma_seq,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
|
||||
dma_cntrl_nodes.append(dma_cntrl)
|
||||
cntrl_count += 1
|
||||
|
||||
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
|
||||
|
||||
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|
||||
185
simulators/gem5/configs/ruby/MOESI_CMP_directory.py
Normal file
185
simulators/gem5/configs/ruby/MOESI_CMP_directory.py
Normal file
@ -0,0 +1,185 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import math
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
|
||||
#
|
||||
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
|
||||
#
|
||||
class L1Cache(RubyCache):
|
||||
latency = 3
|
||||
|
||||
#
|
||||
# Note: the L2 Cache latency is not currently used
|
||||
#
|
||||
class L2Cache(RubyCache):
|
||||
latency = 15
|
||||
|
||||
def define_options(parser):
|
||||
return
|
||||
|
||||
def create_system(options, system, piobus, dma_ports, ruby_system):
|
||||
|
||||
if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
|
||||
panic("This script requires the MOESI_CMP_directory protocol to be built.")
|
||||
|
||||
cpu_sequencers = []
|
||||
|
||||
#
|
||||
# The ruby network creation expects the list of nodes in the system to be
|
||||
# consistent with the NetDest list. Therefore the l1 controller nodes must be
|
||||
# listed before the directory nodes and directory nodes before dma nodes, etc.
|
||||
#
|
||||
l1_cntrl_nodes = []
|
||||
l2_cntrl_nodes = []
|
||||
dir_cntrl_nodes = []
|
||||
dma_cntrl_nodes = []
|
||||
|
||||
#
|
||||
# Must create the individual controllers before the network to ensure the
|
||||
# controller constructors are called before the network constructor
|
||||
#
|
||||
l2_bits = int(math.log(options.num_l2caches, 2))
|
||||
block_size_bits = int(math.log(options.cacheline_size, 2))
|
||||
|
||||
cntrl_count = 0
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l1i_cache = L1Cache(size = options.l1i_size,
|
||||
assoc = options.l1i_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
l1d_cache = L1Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
|
||||
l1_cntrl = L1Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L1IcacheMemory = l1i_cache,
|
||||
L1DcacheMemory = l1d_cache,
|
||||
l2_select_num_bits = l2_bits,
|
||||
send_evictions = (
|
||||
options.cpu_type == "detailed"),
|
||||
ruby_system = ruby_system)
|
||||
|
||||
cpu_seq = RubySequencer(version = i,
|
||||
icache = l1i_cache,
|
||||
dcache = l1d_cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
l1_cntrl.sequencer = cpu_seq
|
||||
|
||||
if piobus != None:
|
||||
cpu_seq.pio_port = piobus.slave
|
||||
|
||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||
#
|
||||
# Add controllers and sequencers to the appropriate lists
|
||||
#
|
||||
cpu_sequencers.append(cpu_seq)
|
||||
l1_cntrl_nodes.append(l1_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
l2_index_start = block_size_bits + l2_bits
|
||||
|
||||
for i in xrange(options.num_l2caches):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l2_cache = L2Cache(size = options.l2_size,
|
||||
assoc = options.l2_assoc,
|
||||
start_index_bit = l2_index_start)
|
||||
|
||||
l2_cntrl = L2Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L2cacheMemory = l2_cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.l2_cntrl%d = l2_cntrl" % i)
|
||||
l2_cntrl_nodes.append(l2_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
mem_module_size = phys_mem_size / options.num_dirs
|
||||
|
||||
for i in xrange(options.num_dirs):
|
||||
#
|
||||
# Create the Ruby objects associated with the directory controller
|
||||
#
|
||||
|
||||
mem_cntrl = RubyMemoryControl(version = i)
|
||||
|
||||
dir_size = MemorySize('0B')
|
||||
dir_size.value = mem_module_size
|
||||
|
||||
dir_cntrl = Directory_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
directory = \
|
||||
RubyDirectoryMemory(version = i,
|
||||
size = dir_size),
|
||||
memBuffer = mem_cntrl,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dir_cntrl%d = dir_cntrl" % i)
|
||||
dir_cntrl_nodes.append(dir_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
for i, dma_port in enumerate(dma_ports):
|
||||
#
|
||||
# Create the Ruby objects associated with the dma controller
|
||||
#
|
||||
dma_seq = DMASequencer(version = i,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
dma_cntrl = DMA_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
dma_sequencer = dma_seq,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
|
||||
dma_cntrl_nodes.append(dma_cntrl)
|
||||
cntrl_count += 1
|
||||
|
||||
all_cntrls = l1_cntrl_nodes + \
|
||||
l2_cntrl_nodes + \
|
||||
dir_cntrl_nodes + \
|
||||
dma_cntrl_nodes
|
||||
|
||||
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|
||||
209
simulators/gem5/configs/ruby/MOESI_CMP_token.py
Normal file
209
simulators/gem5/configs/ruby/MOESI_CMP_token.py
Normal file
@ -0,0 +1,209 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import math
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
|
||||
#
|
||||
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
|
||||
#
|
||||
class L1Cache(RubyCache):
|
||||
latency = 2
|
||||
|
||||
#
|
||||
# Note: the L2 Cache latency is not currently used
|
||||
#
|
||||
class L2Cache(RubyCache):
|
||||
latency = 10
|
||||
|
||||
def define_options(parser):
|
||||
parser.add_option("--l1-retries", type="int", default=1,
|
||||
help="Token_CMP: # of l1 retries before going persistent")
|
||||
parser.add_option("--timeout-latency", type="int", default=300,
|
||||
help="Token_CMP: cycles until issuing again");
|
||||
parser.add_option("--disable-dyn-timeouts", action="store_true",
|
||||
help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
|
||||
parser.add_option("--allow-atomic-migration", action="store_true",
|
||||
help="allow migratory sharing for atomic only accessed blocks")
|
||||
|
||||
def create_system(options, system, piobus, dma_ports, ruby_system):
|
||||
|
||||
if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
|
||||
panic("This script requires the MOESI_CMP_token protocol to be built.")
|
||||
|
||||
#
|
||||
# number of tokens that the owner passes to requests so that shared blocks can
|
||||
# respond to read requests
|
||||
#
|
||||
n_tokens = options.num_cpus + 1
|
||||
|
||||
cpu_sequencers = []
|
||||
|
||||
#
|
||||
# The ruby network creation expects the list of nodes in the system to be
|
||||
# consistent with the NetDest list. Therefore the l1 controller nodes must be
|
||||
# listed before the directory nodes and directory nodes before dma nodes, etc.
|
||||
#
|
||||
l1_cntrl_nodes = []
|
||||
l2_cntrl_nodes = []
|
||||
dir_cntrl_nodes = []
|
||||
dma_cntrl_nodes = []
|
||||
|
||||
#
|
||||
# Must create the individual controllers before the network to ensure the
|
||||
# controller constructors are called before the network constructor
|
||||
#
|
||||
l2_bits = int(math.log(options.num_l2caches, 2))
|
||||
block_size_bits = int(math.log(options.cacheline_size, 2))
|
||||
|
||||
cntrl_count = 0
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l1i_cache = L1Cache(size = options.l1i_size,
|
||||
assoc = options.l1i_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
l1d_cache = L1Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
|
||||
l1_cntrl = L1Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L1IcacheMemory = l1i_cache,
|
||||
L1DcacheMemory = l1d_cache,
|
||||
l2_select_num_bits = l2_bits,
|
||||
N_tokens = n_tokens,
|
||||
retry_threshold = \
|
||||
options.l1_retries,
|
||||
fixed_timeout_latency = \
|
||||
options.timeout_latency,
|
||||
dynamic_timeout_enabled = \
|
||||
not options.disable_dyn_timeouts,
|
||||
no_mig_atomic = not \
|
||||
options.allow_atomic_migration,
|
||||
send_evictions = (
|
||||
options.cpu_type == "detailed"),
|
||||
ruby_system = ruby_system)
|
||||
|
||||
cpu_seq = RubySequencer(version = i,
|
||||
icache = l1i_cache,
|
||||
dcache = l1d_cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
l1_cntrl.sequencer = cpu_seq
|
||||
|
||||
if piobus != None:
|
||||
cpu_seq.pio_port = piobus.slave
|
||||
|
||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||
#
|
||||
# Add controllers and sequencers to the appropriate lists
|
||||
#
|
||||
cpu_sequencers.append(cpu_seq)
|
||||
l1_cntrl_nodes.append(l1_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
l2_index_start = block_size_bits + l2_bits
|
||||
|
||||
for i in xrange(options.num_l2caches):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l2_cache = L2Cache(size = options.l2_size,
|
||||
assoc = options.l2_assoc,
|
||||
start_index_bit = l2_index_start)
|
||||
|
||||
l2_cntrl = L2Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L2cacheMemory = l2_cache,
|
||||
N_tokens = n_tokens,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.l2_cntrl%d = l2_cntrl" % i)
|
||||
l2_cntrl_nodes.append(l2_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
mem_module_size = phys_mem_size / options.num_dirs
|
||||
|
||||
for i in xrange(options.num_dirs):
|
||||
#
|
||||
# Create the Ruby objects associated with the directory controller
|
||||
#
|
||||
|
||||
mem_cntrl = RubyMemoryControl(version = i)
|
||||
|
||||
dir_size = MemorySize('0B')
|
||||
dir_size.value = mem_module_size
|
||||
|
||||
dir_cntrl = Directory_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
directory = \
|
||||
RubyDirectoryMemory(version = i,
|
||||
size = dir_size),
|
||||
memBuffer = mem_cntrl,
|
||||
l2_select_num_bits = l2_bits,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dir_cntrl%d = dir_cntrl" % i)
|
||||
dir_cntrl_nodes.append(dir_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
for i, dma_port in enumerate(dma_ports):
|
||||
#
|
||||
# Create the Ruby objects associated with the dma controller
|
||||
#
|
||||
dma_seq = DMASequencer(version = i,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
dma_cntrl = DMA_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
dma_sequencer = dma_seq,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
|
||||
dma_cntrl_nodes.append(dma_cntrl)
|
||||
cntrl_count += 1
|
||||
|
||||
all_cntrls = l1_cntrl_nodes + \
|
||||
l2_cntrl_nodes + \
|
||||
dir_cntrl_nodes + \
|
||||
dma_cntrl_nodes
|
||||
|
||||
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|
||||
222
simulators/gem5/configs/ruby/MOESI_hammer.py
Normal file
222
simulators/gem5/configs/ruby/MOESI_hammer.py
Normal file
@ -0,0 +1,222 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import math
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
|
||||
#
|
||||
# Note: the L1 Cache latency is only used by the sequencer on fast path hits
|
||||
#
|
||||
class L1Cache(RubyCache):
|
||||
latency = 2
|
||||
|
||||
#
|
||||
# Note: the L2 Cache latency is not currently used
|
||||
#
|
||||
class L2Cache(RubyCache):
|
||||
latency = 10
|
||||
|
||||
#
|
||||
# Probe filter is a cache, latency is not used
|
||||
#
|
||||
class ProbeFilter(RubyCache):
|
||||
latency = 1
|
||||
|
||||
def define_options(parser):
|
||||
parser.add_option("--allow-atomic-migration", action="store_true",
|
||||
help="allow migratory sharing for atomic only accessed blocks")
|
||||
parser.add_option("--pf-on", action="store_true",
|
||||
help="Hammer: enable Probe Filter")
|
||||
parser.add_option("--dir-on", action="store_true",
|
||||
help="Hammer: enable Full-bit Directory")
|
||||
|
||||
def create_system(options, system, piobus, dma_ports, ruby_system):
|
||||
|
||||
if buildEnv['PROTOCOL'] != 'MOESI_hammer':
|
||||
panic("This script requires the MOESI_hammer protocol to be built.")
|
||||
|
||||
cpu_sequencers = []
|
||||
|
||||
#
|
||||
# The ruby network creation expects the list of nodes in the system to be
|
||||
# consistent with the NetDest list. Therefore the l1 controller nodes must be
|
||||
# listed before the directory nodes and directory nodes before dma nodes, etc.
|
||||
#
|
||||
l1_cntrl_nodes = []
|
||||
dir_cntrl_nodes = []
|
||||
dma_cntrl_nodes = []
|
||||
|
||||
#
|
||||
# Must create the individual controllers before the network to ensure the
|
||||
# controller constructors are called before the network constructor
|
||||
#
|
||||
block_size_bits = int(math.log(options.cacheline_size, 2))
|
||||
|
||||
cntrl_count = 0
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
#
|
||||
l1i_cache = L1Cache(size = options.l1i_size,
|
||||
assoc = options.l1i_assoc,
|
||||
start_index_bit = block_size_bits,
|
||||
is_icache = True)
|
||||
l1d_cache = L1Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
l2_cache = L2Cache(size = options.l2_size,
|
||||
assoc = options.l2_assoc,
|
||||
start_index_bit = block_size_bits)
|
||||
|
||||
l1_cntrl = L1Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
L1IcacheMemory = l1i_cache,
|
||||
L1DcacheMemory = l1d_cache,
|
||||
L2cacheMemory = l2_cache,
|
||||
no_mig_atomic = not \
|
||||
options.allow_atomic_migration,
|
||||
send_evictions = (
|
||||
options.cpu_type == "detailed"),
|
||||
ruby_system = ruby_system)
|
||||
|
||||
cpu_seq = RubySequencer(version = i,
|
||||
icache = l1i_cache,
|
||||
dcache = l1d_cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
l1_cntrl.sequencer = cpu_seq
|
||||
|
||||
if piobus != None:
|
||||
cpu_seq.pio_port = piobus.slave
|
||||
|
||||
if options.recycle_latency:
|
||||
l1_cntrl.recycle_latency = options.recycle_latency
|
||||
|
||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||
#
|
||||
# Add controllers and sequencers to the appropriate lists
|
||||
#
|
||||
cpu_sequencers.append(cpu_seq)
|
||||
l1_cntrl_nodes.append(l1_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
mem_module_size = phys_mem_size / options.num_dirs
|
||||
|
||||
#
|
||||
# determine size and index bits for probe filter
|
||||
# By default, the probe filter size is configured to be twice the
|
||||
# size of the L2 cache.
|
||||
#
|
||||
pf_size = MemorySize(options.l2_size)
|
||||
pf_size.value = pf_size.value * 2
|
||||
dir_bits = int(math.log(options.num_dirs, 2))
|
||||
pf_bits = int(math.log(pf_size.value, 2))
|
||||
if options.numa_high_bit:
|
||||
if options.numa_high_bit > 0:
|
||||
# if numa high bit explicitly set, make sure it does not overlap
|
||||
# with the probe filter index
|
||||
assert(options.numa_high_bit - dir_bits > pf_bits)
|
||||
|
||||
# set the probe filter start bit to just above the block offset
|
||||
pf_start_bit = 6
|
||||
else:
|
||||
if dir_bits > 0:
|
||||
pf_start_bit = dir_bits + 5
|
||||
else:
|
||||
pf_start_bit = 6
|
||||
|
||||
for i in xrange(options.num_dirs):
|
||||
#
|
||||
# Create the Ruby objects associated with the directory controller
|
||||
#
|
||||
|
||||
mem_cntrl = RubyMemoryControl(version = i)
|
||||
|
||||
dir_size = MemorySize('0B')
|
||||
dir_size.value = mem_module_size
|
||||
|
||||
pf = ProbeFilter(size = pf_size, assoc = 4,
|
||||
start_index_bit = pf_start_bit)
|
||||
|
||||
dir_cntrl = Directory_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
directory = \
|
||||
RubyDirectoryMemory( \
|
||||
version = i,
|
||||
size = dir_size,
|
||||
use_map = options.use_map,
|
||||
map_levels = \
|
||||
options.map_levels,
|
||||
numa_high_bit = \
|
||||
options.numa_high_bit),
|
||||
probeFilter = pf,
|
||||
memBuffer = mem_cntrl,
|
||||
probe_filter_enabled = options.pf_on,
|
||||
full_bit_dir_enabled = options.dir_on,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
if options.recycle_latency:
|
||||
dir_cntrl.recycle_latency = options.recycle_latency
|
||||
|
||||
exec("system.dir_cntrl%d = dir_cntrl" % i)
|
||||
dir_cntrl_nodes.append(dir_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
for i, dma_port in enumerate(dma_ports):
|
||||
#
|
||||
# Create the Ruby objects associated with the dma controller
|
||||
#
|
||||
dma_seq = DMASequencer(version = i,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
dma_cntrl = DMA_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
dma_sequencer = dma_seq,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dma_cntrl%d = dma_cntrl" % i)
|
||||
exec("system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
|
||||
dma_cntrl_nodes.append(dma_cntrl)
|
||||
|
||||
if options.recycle_latency:
|
||||
dma_cntrl.recycle_latency = options.recycle_latency
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
|
||||
|
||||
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|
||||
138
simulators/gem5/configs/ruby/Network_test.py
Normal file
138
simulators/gem5/configs/ruby/Network_test.py
Normal file
@ -0,0 +1,138 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
from m5.util import addToPath
|
||||
|
||||
#
|
||||
# Note: the cache latency is only used by the sequencer on fast path hits
|
||||
#
|
||||
class Cache(RubyCache):
|
||||
latency = 3
|
||||
|
||||
def define_options(parser):
|
||||
return
|
||||
|
||||
def create_system(options, system, piobus, dma_ports, ruby_system):
|
||||
|
||||
if buildEnv['PROTOCOL'] != 'Network_test':
|
||||
panic("This script requires the Network_test protocol to be built.")
|
||||
|
||||
cpu_sequencers = []
|
||||
|
||||
#
|
||||
# The Garnet tester protocol does not support fs nor dma
|
||||
#
|
||||
assert(piobus == None)
|
||||
assert(dma_ports == [])
|
||||
|
||||
#
|
||||
# The ruby network creation expects the list of nodes in the system to be
|
||||
# consistent with the NetDest list. Therefore the l1 controller nodes must be
|
||||
# listed before the directory nodes and directory nodes before dma nodes, etc.
|
||||
#
|
||||
l1_cntrl_nodes = []
|
||||
dir_cntrl_nodes = []
|
||||
|
||||
#
|
||||
# Must create the individual controllers before the network to ensure the
|
||||
# controller constructors are called before the network constructor
|
||||
#
|
||||
|
||||
cntrl_count = 0
|
||||
|
||||
for i in xrange(options.num_cpus):
|
||||
#
|
||||
# First create the Ruby objects associated with this cpu
|
||||
# Only one cache exists for this protocol, so by default use the L1D
|
||||
# config parameters.
|
||||
#
|
||||
cache = Cache(size = options.l1d_size,
|
||||
assoc = options.l1d_assoc)
|
||||
|
||||
#
|
||||
# Only one unified L1 cache exists. Can cache instructions and data.
|
||||
#
|
||||
l1_cntrl = L1Cache_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
cacheMemory = cache,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
cpu_seq = RubySequencer(icache = cache,
|
||||
dcache = cache,
|
||||
using_network_tester = True,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
l1_cntrl.sequencer = cpu_seq
|
||||
|
||||
if piobus != None:
|
||||
cpu_seq.pio_port = piobus.slave
|
||||
|
||||
exec("system.l1_cntrl%d = l1_cntrl" % i)
|
||||
#
|
||||
# Add controllers and sequencers to the appropriate lists
|
||||
#
|
||||
cpu_sequencers.append(cpu_seq)
|
||||
l1_cntrl_nodes.append(l1_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
mem_module_size = phys_mem_size / options.num_dirs
|
||||
|
||||
for i in xrange(options.num_dirs):
|
||||
#
|
||||
# Create the Ruby objects associated with the directory controller
|
||||
#
|
||||
|
||||
mem_cntrl = RubyMemoryControl(version = i)
|
||||
|
||||
dir_size = MemorySize('0B')
|
||||
dir_size.value = mem_module_size
|
||||
|
||||
dir_cntrl = Directory_Controller(version = i,
|
||||
cntrl_id = cntrl_count,
|
||||
directory = \
|
||||
RubyDirectoryMemory(version = i,
|
||||
size = dir_size),
|
||||
memBuffer = mem_cntrl,
|
||||
ruby_system = ruby_system)
|
||||
|
||||
exec("system.dir_cntrl%d = dir_cntrl" % i)
|
||||
dir_cntrl_nodes.append(dir_cntrl)
|
||||
|
||||
cntrl_count += 1
|
||||
|
||||
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
|
||||
|
||||
return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
|
||||
189
simulators/gem5/configs/ruby/Ruby.py
Normal file
189
simulators/gem5/configs/ruby/Ruby.py
Normal file
@ -0,0 +1,189 @@
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2009 Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Brad Beckmann
|
||||
|
||||
import math
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
|
||||
def define_options(parser):
|
||||
# By default, ruby uses the simple timing cpu
|
||||
parser.set_defaults(cpu_type="timing")
|
||||
|
||||
# ruby network options
|
||||
parser.add_option("--topology", type="string", default="Crossbar",
|
||||
help="check src/mem/ruby/network/topologies for complete set")
|
||||
parser.add_option("--mesh-rows", type="int", default=1,
|
||||
help="the number of rows in the mesh topology")
|
||||
parser.add_option("--garnet-network", type="string", default=None,
|
||||
help="'fixed'|'flexible'")
|
||||
parser.add_option("--network-fault-model", action="store_true", default=False,
|
||||
help="enable network fault model: see src/mem/ruby/network/fault_model/")
|
||||
|
||||
# ruby mapping options
|
||||
parser.add_option("--numa-high-bit", type="int", default=0,
|
||||
help="high order address bit to use for numa mapping. " \
|
||||
"0 = highest bit, not specified = lowest bit")
|
||||
|
||||
# ruby sparse memory options
|
||||
parser.add_option("--use-map", action="store_true", default=False)
|
||||
parser.add_option("--map-levels", type="int", default=4)
|
||||
|
||||
parser.add_option("--recycle-latency", type="int", default=10,
|
||||
help="Recycle latency for ruby controller input buffers")
|
||||
|
||||
parser.add_option("--random_seed", type="int", default=1234,
|
||||
help="Used for seeding the random number generator")
|
||||
|
||||
parser.add_option("--ruby_stats", type="string", default="ruby.stats")
|
||||
|
||||
protocol = buildEnv['PROTOCOL']
|
||||
exec "import %s" % protocol
|
||||
eval("%s.define_options(parser)" % protocol)
|
||||
|
||||
def create_system(options, system, piobus = None, dma_ports = []):
|
||||
|
||||
system.ruby = RubySystem(clock = options.clock,
|
||||
stats_filename = options.ruby_stats,
|
||||
no_mem_vec = options.use_map)
|
||||
ruby = system.ruby
|
||||
|
||||
protocol = buildEnv['PROTOCOL']
|
||||
exec "import %s" % protocol
|
||||
try:
|
||||
(cpu_sequencers, dir_cntrls, all_cntrls) = \
|
||||
eval("%s.create_system(options, system, piobus, dma_ports, ruby)"
|
||||
% protocol)
|
||||
except:
|
||||
print "Error: could not create sytem for ruby protocol %s" % protocol
|
||||
raise
|
||||
|
||||
# Create a port proxy for connecting the system port. This is
|
||||
# independent of the protocol and kept in the protocol-agnostic
|
||||
# part (i.e. here).
|
||||
sys_port_proxy = RubyPortProxy(ruby_system = ruby)
|
||||
# Give the system port proxy a SimObject parent without creating a
|
||||
# full-fledged controller
|
||||
system.sys_port_proxy = sys_port_proxy
|
||||
|
||||
# Connect the system port for loading of binaries etc
|
||||
system.system_port = system.sys_port_proxy.slave
|
||||
|
||||
|
||||
#
|
||||
# Set the network classes based on the command line options
|
||||
#
|
||||
if options.garnet_network == "fixed":
|
||||
class NetworkClass(GarnetNetwork_d): pass
|
||||
class IntLinkClass(GarnetIntLink_d): pass
|
||||
class ExtLinkClass(GarnetExtLink_d): pass
|
||||
class RouterClass(GarnetRouter_d): pass
|
||||
elif options.garnet_network == "flexible":
|
||||
class NetworkClass(GarnetNetwork): pass
|
||||
class IntLinkClass(GarnetIntLink): pass
|
||||
class ExtLinkClass(GarnetExtLink): pass
|
||||
class RouterClass(GarnetRouter): pass
|
||||
else:
|
||||
class NetworkClass(SimpleNetwork): pass
|
||||
class IntLinkClass(SimpleIntLink): pass
|
||||
class ExtLinkClass(SimpleExtLink): pass
|
||||
class RouterClass(BasicRouter): pass
|
||||
|
||||
#
|
||||
# Important: the topology must be created before the network and after the
|
||||
# controllers.
|
||||
#
|
||||
exec "import %s" % options.topology
|
||||
try:
|
||||
net_topology = eval("%s.makeTopology(all_cntrls, options, \
|
||||
IntLinkClass, ExtLinkClass, \
|
||||
RouterClass)" \
|
||||
% options.topology)
|
||||
except:
|
||||
print "Error: could not create topology %s" % options.topology
|
||||
raise
|
||||
|
||||
if options.network_fault_model:
|
||||
assert(options.garnet_network == "fixed")
|
||||
fault_model = FaultModel()
|
||||
network = NetworkClass(ruby_system = ruby, topology = net_topology,\
|
||||
enable_fault_model=True, fault_model = fault_model)
|
||||
else:
|
||||
network = NetworkClass(ruby_system = ruby, topology = net_topology)
|
||||
|
||||
#
|
||||
# Loop through the directory controlers.
|
||||
# Determine the total memory size of the ruby system and verify it is equal
|
||||
# to physmem. However, if Ruby memory is using sparse memory in SE
|
||||
# mode, then the system should not back-up the memory state with
|
||||
# the Memory Vector and thus the memory size bytes should stay at 0.
|
||||
# Also set the numa bits to the appropriate values.
|
||||
#
|
||||
total_mem_size = MemorySize('0B')
|
||||
|
||||
dir_bits = int(math.log(options.num_dirs, 2))
|
||||
|
||||
if options.numa_high_bit:
|
||||
numa_bit = options.numa_high_bit
|
||||
else:
|
||||
# if not specified, use the lowest bits above the block offest
|
||||
if dir_bits > 0:
|
||||
# add 5 because bits 0-5 are the block offset
|
||||
numa_bit = dir_bits + 5
|
||||
else:
|
||||
numa_bit = 6
|
||||
|
||||
for dir_cntrl in dir_cntrls:
|
||||
total_mem_size.value += dir_cntrl.directory.size.value
|
||||
dir_cntrl.directory.numa_high_bit = numa_bit
|
||||
|
||||
phys_mem_size = 0
|
||||
for mem in system.memories.unproxy(system):
|
||||
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
|
||||
assert(total_mem_size.value == phys_mem_size)
|
||||
|
||||
ruby_profiler = RubyProfiler(ruby_system = ruby,
|
||||
num_of_sequencers = len(cpu_sequencers))
|
||||
ruby.network = network
|
||||
ruby.profiler = ruby_profiler
|
||||
ruby.mem_size = total_mem_size
|
||||
ruby._cpu_ruby_ports = cpu_sequencers
|
||||
ruby.random_seed = options.random_seed
|
||||
304
simulators/gem5/configs/splash2/cluster.py
Normal file
304
simulators/gem5/configs/splash2/cluster.py
Normal file
@ -0,0 +1,304 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
|
||||
# Simple test script
|
||||
#
|
||||
# "m5 test.py"
|
||||
|
||||
import os
|
||||
import optparse
|
||||
import sys
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
|
||||
m5.util.addToPath('../common')
|
||||
|
||||
# --------------------
|
||||
# Define Command Line Options
|
||||
# ====================
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
|
||||
parser.add_option("-d", "--detailed", action="store_true")
|
||||
parser.add_option("-t", "--timing", action="store_true")
|
||||
parser.add_option("-m", "--maxtick", type="int")
|
||||
parser.add_option("-c", "--numclusters",
|
||||
help="Number of clusters", type="int")
|
||||
parser.add_option("-n", "--numcpus",
|
||||
help="Number of cpus in total", type="int")
|
||||
parser.add_option("-f", "--frequency",
|
||||
default = "1GHz",
|
||||
help="Frequency of each CPU")
|
||||
parser.add_option("--l1size",
|
||||
default = "32kB")
|
||||
parser.add_option("--l1latency",
|
||||
default = 1)
|
||||
parser.add_option("--l2size",
|
||||
default = "256kB")
|
||||
parser.add_option("--l2latency",
|
||||
default = 10)
|
||||
parser.add_option("--rootdir",
|
||||
help="ROot directory of Splash2",
|
||||
default="/dist/splash2/codes/")
|
||||
parser.add_option("-b", "--benchmark",
|
||||
help="Splash 2 benchmark to run")
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
# --------------------
|
||||
# Define Splash2 Benchmarks
|
||||
# ====================
|
||||
class Cholesky(LiveProcess):
|
||||
executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
|
||||
cmd = 'CHOLESKY -p' + str(options.numcpus) + ' '\
|
||||
+ options.rootdir + '/kernels/cholesky/inputs/tk23.O'
|
||||
|
||||
class FFT(LiveProcess):
|
||||
executable = options.rootdir + 'kernels/fft/FFT'
|
||||
cmd = 'FFT -p' + str(options.numcpus) + ' -m18'
|
||||
|
||||
class LU_contig(LiveProcess):
|
||||
executable = options.rootdir + 'kernels/lu/contiguous_blocks/LU'
|
||||
cmd = 'LU -p' + str(options.numcpus)
|
||||
|
||||
class LU_noncontig(LiveProcess):
|
||||
executable = options.rootdir + 'kernels/lu/non_contiguous_blocks/LU'
|
||||
cmd = 'LU -p' + str(options.numcpus)
|
||||
|
||||
class Radix(LiveProcess):
|
||||
executable = options.rootdir + 'kernels/radix/RADIX'
|
||||
cmd = 'RADIX -n524288 -p' + str(options.numcpus)
|
||||
|
||||
class Barnes(LiveProcess):
|
||||
executable = options.rootdir + 'apps/barnes/BARNES'
|
||||
cmd = 'BARNES'
|
||||
input = options.rootdir + 'apps/barnes/input.p' + str(options.numcpus)
|
||||
|
||||
class FMM(LiveProcess):
|
||||
executable = options.rootdir + 'apps/fmm/FMM'
|
||||
cmd = 'FMM'
|
||||
input = options.rootdir + 'apps/fmm/inputs/input.2048.p' + str(options.numcpus)
|
||||
|
||||
class Ocean_contig(LiveProcess):
|
||||
executable = options.rootdir + 'apps/ocean/contiguous_partitions/OCEAN'
|
||||
cmd = 'OCEAN -p' + str(options.numcpus)
|
||||
|
||||
class Ocean_noncontig(LiveProcess):
|
||||
executable = options.rootdir + 'apps/ocean/non_contiguous_partitions/OCEAN'
|
||||
cmd = 'OCEAN -p' + str(options.numcpus)
|
||||
|
||||
class Raytrace(LiveProcess):
|
||||
executable = options.rootdir + 'apps/raytrace/RAYTRACE'
|
||||
cmd = 'RAYTRACE -p' + str(options.numcpus) + ' ' \
|
||||
+ options.rootdir + 'apps/raytrace/inputs/teapot.env'
|
||||
|
||||
class Water_nsquared(LiveProcess):
|
||||
executable = options.rootdir + 'apps/water-nsquared/WATER-NSQUARED'
|
||||
cmd = 'WATER-NSQUARED'
|
||||
input = options.rootdir + 'apps/water-nsquared/input.p' + str(options.numcpus)
|
||||
|
||||
class Water_spatial(LiveProcess):
|
||||
executable = options.rootdir + 'apps/water-spatial/WATER-SPATIAL'
|
||||
cmd = 'WATER-SPATIAL'
|
||||
input = options.rootdir + 'apps/water-spatial/input.p' + str(options.numcpus)
|
||||
|
||||
|
||||
# --------------------
|
||||
# Base L1 Cache Definition
|
||||
# ====================
|
||||
|
||||
class L1(BaseCache):
|
||||
latency = options.l1latency
|
||||
block_size = 64
|
||||
mshrs = 12
|
||||
tgts_per_mshr = 8
|
||||
|
||||
# ----------------------
|
||||
# Base L2 Cache Definition
|
||||
# ----------------------
|
||||
|
||||
class L2(BaseCache):
|
||||
block_size = 64
|
||||
latency = options.l2latency
|
||||
mshrs = 92
|
||||
tgts_per_mshr = 16
|
||||
write_buffers = 8
|
||||
|
||||
# ----------------------
|
||||
# Define the clusters with their cpus
|
||||
# ----------------------
|
||||
class Cluster:
|
||||
pass
|
||||
|
||||
cpusPerCluster = options.numcpus/options.numclusters
|
||||
|
||||
busFrequency = Frequency(options.frequency)
|
||||
busFrequency *= cpusPerCluster
|
||||
|
||||
all_cpus = []
|
||||
all_l1s = []
|
||||
all_l1buses = []
|
||||
if options.timing:
|
||||
clusters = [ Cluster() for i in xrange(options.numclusters)]
|
||||
for j in xrange(options.numclusters):
|
||||
clusters[j].id = j
|
||||
for cluster in clusters:
|
||||
cluster.clusterbus = CoherentBus(clock=busFrequency)
|
||||
all_l1buses += [cluster.clusterbus]
|
||||
cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
|
||||
clock=options.frequency)
|
||||
for i in xrange(cpusPerCluster)]
|
||||
all_cpus += cluster.cpus
|
||||
cluster.l1 = L1(size=options.l1size, assoc = 4)
|
||||
all_l1s += [cluster.l1]
|
||||
elif options.detailed:
|
||||
clusters = [ Cluster() for i in xrange(options.numclusters)]
|
||||
for j in xrange(options.numclusters):
|
||||
clusters[j].id = j
|
||||
for cluster in clusters:
|
||||
cluster.clusterbus = CoherentBus(clock=busFrequency)
|
||||
all_l1buses += [cluster.clusterbus]
|
||||
cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
|
||||
clock=options.frequency)
|
||||
for i in xrange(cpusPerCluster)]
|
||||
all_cpus += cluster.cpus
|
||||
cluster.l1 = L1(size=options.l1size, assoc = 4)
|
||||
all_l1s += [cluster.l1]
|
||||
else:
|
||||
clusters = [ Cluster() for i in xrange(options.numclusters)]
|
||||
for j in xrange(options.numclusters):
|
||||
clusters[j].id = j
|
||||
for cluster in clusters:
|
||||
cluster.clusterbus = CoherentBus(clock=busFrequency)
|
||||
all_l1buses += [cluster.clusterbus]
|
||||
cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
|
||||
clock=options.frequency)
|
||||
for i in xrange(cpusPerCluster)]
|
||||
all_cpus += cluster.cpus
|
||||
cluster.l1 = L1(size=options.l1size, assoc = 4)
|
||||
all_l1s += [cluster.l1]
|
||||
|
||||
# ----------------------
|
||||
# Create a system, and add system wide objects
|
||||
# ----------------------
|
||||
system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
|
||||
physmem = SimpleMemory(),
|
||||
membus = CoherentBus(clock = busFrequency))
|
||||
|
||||
system.toL2bus = CoherentBus(clock = busFrequency)
|
||||
system.l2 = L2(size = options.l2size, assoc = 8)
|
||||
|
||||
# ----------------------
|
||||
# Connect the L2 cache and memory together
|
||||
# ----------------------
|
||||
|
||||
system.physmem.port = system.membus.master
|
||||
system.l2.cpu_side = system.toL2bus.slave
|
||||
system.l2.mem_side = system.membus.master
|
||||
|
||||
# ----------------------
|
||||
# Connect the L2 cache and clusters together
|
||||
# ----------------------
|
||||
for cluster in clusters:
|
||||
cluster.l1.cpu_side = cluster.clusterbus.master
|
||||
cluster.l1.mem_side = system.toL2bus.slave
|
||||
for cpu in cluster.cpus:
|
||||
cpu.icache_port = cluster.clusterbus.slave
|
||||
cpu.dcache_port = cluster.clusterbus.slave
|
||||
|
||||
# ----------------------
|
||||
# Define the root
|
||||
# ----------------------
|
||||
|
||||
root = Root(full_system = False, system = system)
|
||||
|
||||
# --------------------
|
||||
# Pick the correct Splash2 Benchmarks
|
||||
# ====================
|
||||
if options.benchmark == 'Cholesky':
|
||||
root.workload = Cholesky()
|
||||
elif options.benchmark == 'FFT':
|
||||
root.workload = FFT()
|
||||
elif options.benchmark == 'LUContig':
|
||||
root.workload = LU_contig()
|
||||
elif options.benchmark == 'LUNoncontig':
|
||||
root.workload = LU_noncontig()
|
||||
elif options.benchmark == 'Radix':
|
||||
root.workload = Radix()
|
||||
elif options.benchmark == 'Barnes':
|
||||
root.workload = Barnes()
|
||||
elif options.benchmark == 'FMM':
|
||||
root.workload = FMM()
|
||||
elif options.benchmark == 'OceanContig':
|
||||
root.workload = Ocean_contig()
|
||||
elif options.benchmark == 'OceanNoncontig':
|
||||
root.workload = Ocean_noncontig()
|
||||
elif options.benchmark == 'Raytrace':
|
||||
root.workload = Raytrace()
|
||||
elif options.benchmark == 'WaterNSquared':
|
||||
root.workload = Water_nsquared()
|
||||
elif options.benchmark == 'WaterSpatial':
|
||||
root.workload = Water_spatial()
|
||||
else:
|
||||
m5.util.panic("""
|
||||
The --benchmark environment variable was set to something improper.
|
||||
Use Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig,
|
||||
OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial
|
||||
""")
|
||||
|
||||
# --------------------
|
||||
# Assign the workload to the cpus
|
||||
# ====================
|
||||
|
||||
for cluster in clusters:
|
||||
for cpu in cluster.cpus:
|
||||
cpu.workload = root.workload
|
||||
|
||||
# ----------------------
|
||||
# Run the simulation
|
||||
# ----------------------
|
||||
|
||||
if options.timing or options.detailed:
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
if options.maxtick:
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
else:
|
||||
exit_event = m5.simulate(m5.MaxTick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
|
||||
288
simulators/gem5/configs/splash2/run.py
Normal file
288
simulators/gem5/configs/splash2/run.py
Normal file
@ -0,0 +1,288 @@
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ron Dreslinski
|
||||
|
||||
# Splash2 Run Script
|
||||
#
|
||||
|
||||
import os
|
||||
import optparse
|
||||
import sys
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
|
||||
m5.util.addToPath('../common')
|
||||
|
||||
# --------------------
|
||||
# Define Command Line Options
|
||||
# ====================
|
||||
|
||||
parser = optparse.OptionParser()
|
||||
|
||||
parser.add_option("-d", "--detailed", action="store_true")
|
||||
parser.add_option("-t", "--timing", action="store_true")
|
||||
parser.add_option("-m", "--maxtick", type="int")
|
||||
parser.add_option("-n", "--numcpus",
|
||||
help="Number of cpus in total", type="int")
|
||||
parser.add_option("-f", "--frequency",
|
||||
default = "1GHz",
|
||||
help="Frequency of each CPU")
|
||||
parser.add_option("--l1size",
|
||||
default = "32kB")
|
||||
parser.add_option("--l1latency",
|
||||
default = "1ns")
|
||||
parser.add_option("--l2size",
|
||||
default = "256kB")
|
||||
parser.add_option("--l2latency",
|
||||
default = "10ns")
|
||||
parser.add_option("--rootdir",
|
||||
help="Root directory of Splash2",
|
||||
default="/dist/splash2/codes")
|
||||
parser.add_option("-b", "--benchmark",
|
||||
help="Splash 2 benchmark to run")
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
if args:
|
||||
print "Error: script doesn't take any positional arguments"
|
||||
sys.exit(1)
|
||||
|
||||
if not options.numcpus:
|
||||
print "Specify the number of cpus with -n"
|
||||
sys.exit(1)
|
||||
|
||||
# --------------------
|
||||
# Define Splash2 Benchmarks
|
||||
# ====================
|
||||
class Cholesky(LiveProcess):
|
||||
cwd = options.rootdir + '/kernels/cholesky'
|
||||
executable = options.rootdir + '/kernels/cholesky/CHOLESKY'
|
||||
cmd = ['CHOLESKY', '-p' + str(options.numcpus),
|
||||
options.rootdir + '/kernels/cholesky/inputs/tk23.O']
|
||||
|
||||
class FFT(LiveProcess):
|
||||
cwd = options.rootdir + '/kernels/fft'
|
||||
executable = options.rootdir + '/kernels/fft/FFT'
|
||||
cmd = ['FFT', '-p', str(options.numcpus), '-m18']
|
||||
|
||||
class LU_contig(LiveProcess):
|
||||
executable = options.rootdir + '/kernels/lu/contiguous_blocks/LU'
|
||||
cmd = ['LU', '-p', str(options.numcpus)]
|
||||
cwd = options.rootdir + '/kernels/lu/contiguous_blocks'
|
||||
|
||||
class LU_noncontig(LiveProcess):
|
||||
executable = options.rootdir + '/kernels/lu/non_contiguous_blocks/LU'
|
||||
cmd = ['LU', '-p', str(options.numcpus)]
|
||||
cwd = options.rootdir + '/kernels/lu/non_contiguous_blocks'
|
||||
|
||||
class Radix(LiveProcess):
|
||||
executable = options.rootdir + '/kernels/radix/RADIX'
|
||||
cmd = ['RADIX', '-n524288', '-p', str(options.numcpus)]
|
||||
cwd = options.rootdir + '/kernels/radix'
|
||||
|
||||
class Barnes(LiveProcess):
|
||||
executable = options.rootdir + '/apps/barnes/BARNES'
|
||||
cmd = ['BARNES']
|
||||
input = options.rootdir + '/apps/barnes/input.p' + str(options.numcpus)
|
||||
cwd = options.rootdir + '/apps/barnes'
|
||||
|
||||
class FMM(LiveProcess):
|
||||
executable = options.rootdir + '/apps/fmm/FMM'
|
||||
cmd = ['FMM']
|
||||
if str(options.numcpus) == '1':
|
||||
input = options.rootdir + '/apps/fmm/inputs/input.2048'
|
||||
else:
|
||||
input = options.rootdir + '/apps/fmm/inputs/input.2048.p' + str(options.numcpus)
|
||||
cwd = options.rootdir + '/apps/fmm'
|
||||
|
||||
class Ocean_contig(LiveProcess):
|
||||
executable = options.rootdir + '/apps/ocean/contiguous_partitions/OCEAN'
|
||||
cmd = ['OCEAN', '-p', str(options.numcpus)]
|
||||
cwd = options.rootdir + '/apps/ocean/contiguous_partitions'
|
||||
|
||||
class Ocean_noncontig(LiveProcess):
|
||||
executable = options.rootdir + '/apps/ocean/non_contiguous_partitions/OCEAN'
|
||||
cmd = ['OCEAN', '-p', str(options.numcpus)]
|
||||
cwd = options.rootdir + '/apps/ocean/non_contiguous_partitions'
|
||||
|
||||
class Raytrace(LiveProcess):
|
||||
executable = options.rootdir + '/apps/raytrace/RAYTRACE'
|
||||
cmd = ['RAYTRACE', '-p' + str(options.numcpus),
|
||||
options.rootdir + '/apps/raytrace/inputs/teapot.env']
|
||||
cwd = options.rootdir + '/apps/raytrace'
|
||||
|
||||
class Water_nsquared(LiveProcess):
|
||||
executable = options.rootdir + '/apps/water-nsquared/WATER-NSQUARED'
|
||||
cmd = ['WATER-NSQUARED']
|
||||
if options.numcpus==1:
|
||||
input = options.rootdir + '/apps/water-nsquared/input'
|
||||
else:
|
||||
input = options.rootdir + '/apps/water-nsquared/input.p' + str(options.numcpus)
|
||||
cwd = options.rootdir + '/apps/water-nsquared'
|
||||
|
||||
class Water_spatial(LiveProcess):
|
||||
executable = options.rootdir + '/apps/water-spatial/WATER-SPATIAL'
|
||||
cmd = ['WATER-SPATIAL']
|
||||
if options.numcpus==1:
|
||||
input = options.rootdir + '/apps/water-spatial/input'
|
||||
else:
|
||||
input = options.rootdir + '/apps/water-spatial/input.p' + str(options.numcpus)
|
||||
cwd = options.rootdir + '/apps/water-spatial'
|
||||
|
||||
# --------------------
|
||||
# Base L1 Cache Definition
|
||||
# ====================
|
||||
|
||||
class L1(BaseCache):
|
||||
latency = options.l1latency
|
||||
block_size = 64
|
||||
mshrs = 12
|
||||
tgts_per_mshr = 8
|
||||
|
||||
# ----------------------
|
||||
# Base L2 Cache Definition
|
||||
# ----------------------
|
||||
|
||||
class L2(BaseCache):
|
||||
block_size = 64
|
||||
latency = options.l2latency
|
||||
mshrs = 92
|
||||
tgts_per_mshr = 16
|
||||
write_buffers = 8
|
||||
|
||||
# ----------------------
|
||||
# Define the cpus
|
||||
# ----------------------
|
||||
|
||||
busFrequency = Frequency(options.frequency)
|
||||
|
||||
if options.timing:
|
||||
cpus = [TimingSimpleCPU(cpu_id = i,
|
||||
clock=options.frequency)
|
||||
for i in xrange(options.numcpus)]
|
||||
elif options.detailed:
|
||||
cpus = [DerivO3CPU(cpu_id = i,
|
||||
clock=options.frequency)
|
||||
for i in xrange(options.numcpus)]
|
||||
else:
|
||||
cpus = [AtomicSimpleCPU(cpu_id = i,
|
||||
clock=options.frequency)
|
||||
for i in xrange(options.numcpus)]
|
||||
|
||||
# ----------------------
|
||||
# Create a system, and add system wide objects
|
||||
# ----------------------
|
||||
system = System(cpu = cpus, physmem = SimpleMemory(),
|
||||
membus = CoherentBus(clock = busFrequency))
|
||||
|
||||
system.toL2bus = CoherentBus(clock = busFrequency)
|
||||
system.l2 = L2(size = options.l2size, assoc = 8)
|
||||
|
||||
# ----------------------
|
||||
# Connect the L2 cache and memory together
|
||||
# ----------------------
|
||||
|
||||
system.physmem.port = system.membus.master
|
||||
system.l2.cpu_side = system.toL2bus.master
|
||||
system.l2.mem_side = system.membus.slave
|
||||
system.system_port = system.membus.slave
|
||||
|
||||
# ----------------------
|
||||
# Connect the L2 cache and clusters together
|
||||
# ----------------------
|
||||
for cpu in cpus:
|
||||
cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
|
||||
L1(size = options.l1size, assoc = 4))
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
cpu.connectAllPorts(system.toL2bus, system.membus)
|
||||
|
||||
|
||||
# ----------------------
|
||||
# Define the root
|
||||
# ----------------------
|
||||
|
||||
root = Root(full_system = False, system = system)
|
||||
|
||||
# --------------------
|
||||
# Pick the correct Splash2 Benchmarks
|
||||
# ====================
|
||||
if options.benchmark == 'Cholesky':
|
||||
root.workload = Cholesky()
|
||||
elif options.benchmark == 'FFT':
|
||||
root.workload = FFT()
|
||||
elif options.benchmark == 'LUContig':
|
||||
root.workload = LU_contig()
|
||||
elif options.benchmark == 'LUNoncontig':
|
||||
root.workload = LU_noncontig()
|
||||
elif options.benchmark == 'Radix':
|
||||
root.workload = Radix()
|
||||
elif options.benchmark == 'Barnes':
|
||||
root.workload = Barnes()
|
||||
elif options.benchmark == 'FMM':
|
||||
root.workload = FMM()
|
||||
elif options.benchmark == 'OceanContig':
|
||||
root.workload = Ocean_contig()
|
||||
elif options.benchmark == 'OceanNoncontig':
|
||||
root.workload = Ocean_noncontig()
|
||||
elif options.benchmark == 'Raytrace':
|
||||
root.workload = Raytrace()
|
||||
elif options.benchmark == 'WaterNSquared':
|
||||
root.workload = Water_nsquared()
|
||||
elif options.benchmark == 'WaterSpatial':
|
||||
root.workload = Water_spatial()
|
||||
else:
|
||||
print >> sys.stderr, """The --benchmark environment variable was set to something improper.
|
||||
Use Cholesky, FFT, LUContig, LUNoncontig, Radix, Barnes, FMM, OceanContig,
|
||||
OceanNoncontig, Raytrace, WaterNSquared, or WaterSpatial"""
|
||||
sys.exit(1)
|
||||
|
||||
# --------------------
|
||||
# Assign the workload to the cpus
|
||||
# ====================
|
||||
|
||||
for cpu in cpus:
|
||||
cpu.workload = root.workload
|
||||
|
||||
# ----------------------
|
||||
# Run the simulation
|
||||
# ----------------------
|
||||
|
||||
if options.timing or options.detailed:
|
||||
root.system.mem_mode = 'timing'
|
||||
|
||||
# instantiate configuration
|
||||
m5.instantiate()
|
||||
|
||||
# simulate until program terminates
|
||||
if options.maxtick:
|
||||
exit_event = m5.simulate(options.maxtick)
|
||||
else:
|
||||
exit_event = m5.simulate(m5.MaxTick)
|
||||
|
||||
print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
|
||||
|
||||
Reference in New Issue
Block a user