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Adding gem5 source to svn.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2012-10-24 19:18:57 +00:00
parent f7ff71bd46
commit b41eec3f65
3222 changed files with 658579 additions and 1 deletions
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4
simulators/gem5/build_opts/ALPHA Normal file
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TARGET_ISA = 'alpha'
SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MI_example'

3
simulators/gem5/build_opts/ALPHA_MESI_CMP_directory Normal file
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SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MESI_CMP_directory'

3
simulators/gem5/build_opts/ALPHA_MOESI_CMP_directory Normal file
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SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MOESI_CMP_directory'

3
simulators/gem5/build_opts/ALPHA_MOESI_CMP_token Normal file
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SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MOESI_CMP_token'

3
simulators/gem5/build_opts/ALPHA_MOESI_hammer Normal file
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SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MOESI_hammer'

3
simulators/gem5/build_opts/ALPHA_Network_test Normal file
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SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'Network_test'

3
simulators/gem5/build_opts/ARM Normal file
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TARGET_ISA = 'arm'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

3
simulators/gem5/build_opts/MIPS Normal file
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TARGET_ISA = 'mips'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MI_example'

2
simulators/gem5/build_opts/NOISA Normal file
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TARGET_ISA = 'no'
CPU_MODELS = 'no'

3
simulators/gem5/build_opts/POWER Normal file
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TARGET_ISA = 'power'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

3
simulators/gem5/build_opts/SPARC Normal file
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TARGET_ISA = 'sparc'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
PROTOCOL = 'MI_example'

3
simulators/gem5/build_opts/X86 Normal file
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TARGET_ISA = 'x86'
CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'
PROTOCOL = 'MI_example'

3
simulators/gem5/build_opts/X86_MESI_CMP_directory Normal file
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@ -0,0 +1,3 @@
TARGET_ISA = 'x86'
CPU_MODELS = 'TimingSimpleCPU,O3CPU'
PROTOCOL = 'MESI_CMP_directory'