Architecture changes (only gem5 implementation right now):

- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/gem5/Gem5ArmCPU.hpp

@@ -0,0 +1,32 @@
+#ifndef __GEM5_ARM_CPU_HPP__
+	#define __GEM5_ARM_CPU_HPP__
+
+#include "../arm/arch.hpp"
+
+#include "sim/system.hh"
+
+namespace fail {
+
+class Gem5ArmCPU : public ArmArchitecture, public ArmCPUState
+{
+public:
+	Gem5ArmCPU(unsigned int id, System* system) : m_Id(id), m_System(system) {}
+	regdata_t getRegisterContent(Register* reg);
+	void setRegisterContent(Register* reg, regdata_t value);
+
+	address_t getInstructionPointer();
+	address_t getStackPointer();
+	address_t getLinkRegister();
+
+	unsigned int getId() { return m_Id; }
+
+private:
+	unsigned int m_Id;
+	System* m_System;
+};
+
+typedef Gem5ArmCPU ConcreteCPU;
+
+} // end-of-namespace: fail
+
+#endif // __GEM5_ARM_CPU_HPP__