Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the CPU classes. - For the client, there is the ConcreteCPU class that encapsulates the access to the CPU state (including registers) and architecture details. The correspondig objects for the CPUs inside the simulator can be accessed through the SimulatorController.getCPU() function. - Listener got a new ConcreteCPU* member to filter for which CPU the events should fire. The default NULL is used as wildcard for all aviable CPUs. The events respectively got a ConcreteCPU* member to indicate which CPU really fired the event. - For the server, there is CPUArchitecture to access the architecture details. git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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friemel
@ -7,8 +7,6 @@ namespace fail {
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// External reference declared in SALInst.hpp
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ConcreteSimulatorController simulator;
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// FIXME: Bochs specific? If not, at least get rid of this global variable.
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int interrupt_to_fire = -1;
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bool SimulatorController::addListener(BaseListener* li)
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{
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@ -52,15 +50,16 @@ void SimulatorController::initExperiments()
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/* empty. */
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}
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void SimulatorController::onBreakpoint(address_t instrPtr, address_t address_space)
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void SimulatorController::onBreakpoint(ConcreteCPU* cpu, address_t instrPtr, address_t address_space)
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{
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// Check for active breakpoint-events:
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ListenerManager::iterator it = m_LstList.begin();
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BPEvent tmp(instrPtr, address_space);
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BPEvent tmp(instrPtr, address_space, cpu);
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while (it != m_LstList.end()) {
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BaseListener* pLi = *it;
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BPListener* pBreakpt = dynamic_cast<BPListener*>(pLi);
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if (pBreakpt != NULL && pBreakpt->isMatching(&tmp)) {
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pBreakpt->setTriggerCPU(cpu);
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pBreakpt->setTriggerInstructionPointer(instrPtr);
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it = m_LstList.makeActive(it);
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// "it" has already been set to the next element (by calling
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@ -72,14 +71,14 @@ void SimulatorController::onBreakpoint(address_t instrPtr, address_t address_spa
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m_LstList.triggerActiveListeners();
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}
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void SimulatorController::onMemoryAccess(address_t addr, size_t len,
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void SimulatorController::onMemoryAccess(ConcreteCPU* cpu, address_t addr, size_t len,
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bool is_write, address_t instrPtr)
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{
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MemAccessEvent::access_type_t accesstype =
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is_write ? MemAccessEvent::MEM_WRITE
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: MemAccessEvent::MEM_READ;
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MemAccessEvent tmp(addr, len, instrPtr, accesstype);
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MemAccessEvent tmp(addr, len, instrPtr, accesstype, cpu);
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ListenerManager::iterator it = m_LstList.begin();
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while (it != m_LstList.end()) { // check for active listeners
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BaseListener* pev = *it;
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@ -93,15 +92,16 @@ void SimulatorController::onMemoryAccess(address_t addr, size_t len,
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ev->setTriggerWidth(len);
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ev->setTriggerInstructionPointer(instrPtr);
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ev->setTriggerAccessType(accesstype);
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ev->setTriggerCPU(cpu);
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it = m_LstList.makeActive(it);
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}
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m_LstList.triggerActiveListeners();
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}
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void SimulatorController::onInterrupt(unsigned interruptNum, bool nmi)
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void SimulatorController::onInterrupt(ConcreteCPU* cpu, unsigned interruptNum, bool nmi)
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{
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ListenerManager::iterator it = m_LstList.begin();
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InterruptEvent tmp(nmi, interruptNum);
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InterruptEvent tmp(nmi, interruptNum, cpu);
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while (it != m_LstList.end()) { // check for active listeners
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BaseListener* pev = *it;
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InterruptListener* pie = dynamic_cast<InterruptListener*>(pev);
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@ -111,53 +111,15 @@ void SimulatorController::onInterrupt(unsigned interruptNum, bool nmi)
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}
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pie->setTriggerNumber(interruptNum);
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pie->setNMI(nmi);
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pie->setTriggerCPU(cpu);
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it = m_LstList.makeActive(it);
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}
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m_LstList.triggerActiveListeners();
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}
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bool SimulatorController::isSuppressedInterrupt(unsigned interruptNum)
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void SimulatorController::onTrap(ConcreteCPU* cpu, unsigned trapNum)
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{
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for (size_t i = 0; i < m_SuppressedInterrupts.size(); i++)
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if ((m_SuppressedInterrupts[i] == interruptNum ||
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m_SuppressedInterrupts[i] == ANY_INTERRUPT) &&
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interruptNum != (unsigned)interrupt_to_fire + 32) {
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if ((int)interruptNum == interrupt_to_fire + 32) {
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interrupt_to_fire = -1;
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return true;
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}
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return true;
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}
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return false;
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}
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bool SimulatorController::addSuppressedInterrupt(unsigned interruptNum)
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{
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// Check if already existing:
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if (isSuppressedInterrupt(interruptNum+32))
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return false; // already added: nothing to do here
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if (interruptNum == ANY_INTERRUPT)
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m_SuppressedInterrupts.push_back(interruptNum);
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else
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m_SuppressedInterrupts.push_back(interruptNum+32);
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return true;
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}
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bool SimulatorController::removeSuppressedInterrupt(unsigned interruptNum)
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{
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for (size_t i = 0; i < m_SuppressedInterrupts.size(); i++) {
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if (m_SuppressedInterrupts[i] == interruptNum+32 ||
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m_SuppressedInterrupts[i] == ANY_INTERRUPT)
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m_SuppressedInterrupts.erase(m_SuppressedInterrupts.begin() + i);
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return true;
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}
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return false;
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}
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void SimulatorController::onTrap(unsigned trapNum)
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{
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TroubleEvent tmp(trapNum);
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TroubleEvent tmp(trapNum, cpu);
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ListenerManager::iterator it = m_LstList.begin();
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while (it != m_LstList.end()) { // check for active listeners
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BaseListener* pev = *it;
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@ -167,6 +129,7 @@ void SimulatorController::onTrap(unsigned trapNum)
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continue; // skip listener activation
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}
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pte->setTriggerNumber(trapNum);
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pte->setTriggerCPU(cpu);
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it = m_LstList.makeActive(it);
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}
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m_LstList.triggerActiveListeners();
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@ -189,7 +152,7 @@ void SimulatorController::onGuestSystem(char data, unsigned port)
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m_LstList.triggerActiveListeners();
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}
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void SimulatorController::onJump(bool flagTriggered, unsigned opcode)
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void SimulatorController::onJump(ConcreteCPU* cpu, bool flagTriggered, unsigned opcode)
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{
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ListenerManager::iterator it = m_LstList.begin();
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while (it != m_LstList.end()) { // check for active listeners
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@ -197,6 +160,7 @@ void SimulatorController::onJump(bool flagTriggered, unsigned opcode)
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if (pje != NULL) {
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pje->setOpcode(opcode);
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pje->setFlagTriggered(flagTriggered);
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pje->setTriggerCPU(cpu);
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it = m_LstList.makeActive(it);
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continue; // dito.
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}
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@ -205,6 +169,19 @@ void SimulatorController::onJump(bool flagTriggered, unsigned opcode)
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m_LstList.triggerActiveListeners();
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}
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bool SimulatorController::addCPU(ConcreteCPU* cpu)
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{
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assert(cpu != NULL && "FATAL ERROR: Argument (cpu) cannot be NULL!");
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m_CPUs.push_back(cpu);
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return true;
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}
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ConcreteCPU& SimulatorController::getCPU(size_t i) const
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{
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assert(i < m_CPUs.size() && "FATAL ERROR: Invalid index provided!");
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return *m_CPUs[i];
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}
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void SimulatorController::addFlow(ExperimentFlow* flow)
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{
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// Store the (flow,corohandle)-tuple internally and create its coroutine:
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