Architecture changes (only gem5 implementation right now):

- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/ConcreteCPU.hpp

@@ -0,0 +1,20 @@
+#ifndef __CONCRETE_CPU_HPP__
+	#define __CONCRETE_CPU_HPP__
+
+#if defined BUILD_BOCHS
+  #include "bochs/BochsCPU.hpp"
+#elif defined BUILD_GEM5
+  #if defined BUILD_ARM
+    #include "gem5/Gem5ArmCPU.hpp"
+  #endif
+#elif defined BUILD_OVP
+  #include "ovp/OVPConfig.hpp"
+#elif defined BUILD_QEMU
+  #include "qemu/QEMUConfig.hpp"
+#elif defined BUILD_T32
+  #include "t32/T32Config.hpp"
+#else
+  #error SAL Config Target not defined
+#endif
+
+#endif // __CONCRETE_CPU_HPP__