Architecture changes (only gem5 implementation right now):

- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/CPU.hpp

@@ -0,0 +1,69 @@
+#ifndef __CPU_HPP__
+	#define __CPU_HPP__
+
+#include <cstring>
+#include <vector>
+
+#include "Register.hpp"
+
+namespace fail {
+
+// TODO: Interrupt information?
+
+/**
+ * \class CPUArchitecture
+ * This is the base class for CPU architectures that can be used to merge informations and
+ * functionallity that every backend with the same target architecture will share. The classes
+ * directly derived from this are especially meant to be usable in campaigns, so they shouldn't
+ * contain any backend specific code.
+ */
+class CPUArchitecture
+{
+public:
+	/**
+	 * Retrieves the total number of registers over all homogeneous sets.
+	 * @return the total register count
+	 */
+	size_t registerCount() const { return m_Registers.size(); }
+	/**
+	 * Retrieves the number of managed homogeneous register sets.
+	 * @return the number of sets
+	 */
+	size_t registerSubsetCount() const { return m_RegisterSubsets.size(); }
+	/**
+	 * Adds a new register to this set. The register object needs to be
+	 * typed (see Register::getType).
+	 * @param reg a pointer to the register object to be added
+	 * @see getType()
+	 */
+	void addRegister(Register* reg);
+	/**
+	 * Retrieves the \a i-th register.
+	 * @return a pointer to the \a i-th register; if \a i is invalid, an
+	 *         assertion is thrown
+	 */
+	Register* getRegister(size_t i) const;
+	/**
+	 * Gets the \a i-th register set.
+	 * @param i the index of the set to be returned
+	 * @return a reference to the uniform register set
+	 * @see registerSubsetCount()
+	 */
+	UniformRegisterSet& getRegisterSet(size_t i) const;
+	/**
+	 * Returns the set with register type \a t. The set can be used to
+	 * loop over all registers of type \a t.
+	 * @param t the type to check for
+	 * @return a pointer to the retrieved register set (if found), NULL
+	 *         otherwise
+	 */
+	UniformRegisterSet* getRegisterSetOfType(RegisterType t) const;
+
+protected:
+	std::vector< Register* > m_Registers;
+	std::vector< UniformRegisterSet* > m_RegisterSubsets;
+};
+
+} // end-of-namespace: fail
+
+#endif // __CPU_HPP__