christoph/fail
1
Fork 0
Code Actions Packages Releases Activity

Revisited register implementation in gem5

Browse Source 
Change-Id: I31fd80d374c945adaf35b47958d6437a8e2d48c3
This commit is contained in:
Adrian Böckenkamp
2013-04-24 14:16:25 +02:00
parent 896d6cc4c1
commit a43da33fd0
3 changed files with 19 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/core/sal/arm/ArmArchitecture.cc
View File

@ -9,15 +9,17 @@ ArmArchitecture::ArmArchitecture()
// TODO: Add missing registers // TODO: Add missing registers
// 16x 32-Bit GP Registers // 16x 32-Bit GP Registers
for (int i = 0; i < 16; i++) { for (int i = 0; i < 16; i++) {
Register *reg = new Register(i, RT_GP, 32); if (i != RI_IP) { // IP will be added separately (see below)
// Build and set the register name: Register *reg = new Register(i, RT_GP, 32);
std::stringstream sstr; // Build and set the register name:
sstr << "R" << i+1; std::stringstream sstr;
reg->setName(sstr.str().c_str()); sstr << "R" << i+1;
m_addRegister(reg); reg->setName(sstr.str().c_str());
m_addRegister(reg);
}
} }
// Instruction Pointer // Instruction Pointer:
Register *reg = new Register(RI_IP, RT_IP, 32); Register *reg = new Register(RI_IP, RT_IP, 32);
reg->setName("IP"); reg->setName("IP");
m_addRegister(reg); m_addRegister(reg);

4
src/core/sal/arm/ArmArchitecture.hpp
View File

@ -67,7 +67,9 @@ enum GPRegIndex {
RI_R14_FIQ RI_R14_FIQ
}; };
// TODO: Enum for misc registers // TODO: Enum for misc registers, see (e.g.)
// simulators/gem5/src/arch/arm/miscregs.hh and
// simulators/gem5/src/arch/arm/intregs.hh
} // end-of-namespace: fail } // end-of-namespace: fail

18
src/core/sal/gem5/Gem5Wrapper.cc
View File

@ -11,12 +11,8 @@ namespace fail {
regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx) regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx)
{ {
switch (type) { switch (type) {
case RT_GP: case RT_GP: // pass on...
if (idx == 15) { case RT_FP: return sys->getThreadContext(id)->readIntReg(idx);
return sys->getThreadContext(id)->pcState().pc();
}
return sys->getThreadContext(id)->readIntReg(idx);
case RT_FP: return sys->getThreadContext(id)->readFloatReg(idx); // FIXME: correct?! (FP <-> Float?!)
case RT_ST: return sys->getThreadContext(id)->readMiscReg(idx); case RT_ST: return sys->getThreadContext(id)->readMiscReg(idx);
case RT_IP: return sys->getThreadContext(id)->pcState().pc(); case RT_IP: return sys->getThreadContext(id)->pcState().pc();
} }
@ -29,13 +25,13 @@ void SetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t
regdata_t value) regdata_t value)
{ {
switch (type) { switch (type) {
case RT_GP: sys->getThreadContext(id)->setIntReg(idx, value); break; case RT_GP: // pass on...
case RT_FP: sys->getThreadContext(id)->setFloatReg(idx, value); break; // FIXME: correct?! (FP <-> Float?!) case RT_FP: sys->getThreadContext(id)->setIntReg(idx, value); return;
case RT_ST: sys->getThreadContext(id)->setMiscReg(idx, value); break; case RT_ST: sys->getThreadContext(id)->setMiscReg(idx, value); return;
case RT_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); break; case RT_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); return;
} }
// This shouldn't be reached if a valid register is passed // This shouldn't be reached if a valid register is passed
assert(false && "FATAL ERROR: invalid register type (should never be reached)!"); assert(false && "FATAL ERROR: Invalid register type (should never be reached)!");
} }
void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest) void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest)