openocd: arm register mapping
Mapping register id (ArmArchitecture) to openocd register id. Change-Id: Id951ce1606e1720e7bc2fd7d6686cff8c1d5c9b4
This commit is contained in:
@ -557,7 +557,7 @@ void oocdw_reboot()
|
|||||||
|
|
||||||
if (reboot_success) {
|
if (reboot_success) {
|
||||||
// Jump over safety loop (set PC)
|
// Jump over safety loop (set PC)
|
||||||
oocdw_write_reg(15, ARM_REGS_CORE, SAFETYLOOP_END + 0x4);
|
oocdw_write_reg(15, SAFETYLOOP_END + 0x4);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -587,11 +587,13 @@ static struct reg *get_reg_by_number(unsigned int num)
|
|||||||
return reg;
|
return reg;
|
||||||
}
|
}
|
||||||
|
|
||||||
void oocdw_read_reg(uint32_t reg_num, enum arm_reg_group rg, uint32_t *data)
|
void oocdw_read_reg(uint32_t reg_num, uint32_t *data)
|
||||||
{
|
{
|
||||||
assert((target_a9->state == TARGET_HALTED) && "Target not halted");
|
assert((target_a9->state == TARGET_HALTED) && "Target not halted");
|
||||||
|
|
||||||
if (reg_num == fail::RI_DFAR) {
|
switch (reg_num) {
|
||||||
|
case fail::RI_DFAR:
|
||||||
|
{
|
||||||
struct armv7a_common *armv7a = target_to_armv7a(target_a9);
|
struct armv7a_common *armv7a = target_to_armv7a(target_a9);
|
||||||
struct arm_dpm *dpm = armv7a->arm.dpm;
|
struct arm_dpm *dpm = armv7a->arm.dpm;
|
||||||
int retval;
|
int retval;
|
||||||
@ -610,22 +612,100 @@ void oocdw_read_reg(uint32_t reg_num, enum arm_reg_group rg, uint32_t *data)
|
|||||||
|
|
||||||
dpm->finish(dpm);
|
dpm->finish(dpm);
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
|
case fail::RI_R0:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R1:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R2:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R3:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R4:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R5:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R6:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R7:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R8:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R9:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R10:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R11:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R12:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R13:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R14:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R15:
|
||||||
|
{
|
||||||
|
struct reg *reg = get_reg_by_number(reg_num);
|
||||||
|
|
||||||
struct reg *reg = get_reg_by_number(reg_num);
|
if (reg->valid == 0) {
|
||||||
|
reg->type->get(reg);
|
||||||
|
}
|
||||||
|
|
||||||
if (reg->valid == 0)
|
*data = *((uint32_t*)(reg->value));
|
||||||
reg->type->get(reg);
|
}
|
||||||
|
break;
|
||||||
*data = *((uint32_t*)(reg->value));
|
default:
|
||||||
|
LOG << "ERROR: Register with id " << reg_num << " unknown." << endl;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void oocdw_write_reg(uint32_t reg_num, enum arm_reg_group rg, uint32_t data)
|
void oocdw_write_reg(uint32_t reg_num, uint32_t data)
|
||||||
{
|
{
|
||||||
assert((target_a9->state == TARGET_HALTED) && "Target not halted");
|
assert((target_a9->state == TARGET_HALTED) && "Target not halted");
|
||||||
|
|
||||||
struct reg *reg = get_reg_by_number(reg_num);
|
switch (reg_num) {
|
||||||
|
case fail::RI_R0:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R1:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R2:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R3:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R4:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R5:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R6:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R7:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R8:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R9:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R10:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R11:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R12:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R13:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R14:
|
||||||
|
/* fall through */
|
||||||
|
case fail::RI_R15:
|
||||||
|
{
|
||||||
|
struct reg *reg = get_reg_by_number(reg_num);
|
||||||
|
|
||||||
reg->type->set(reg, (uint8_t*)(&data));
|
reg->type->set(reg, (uint8_t*)(&data));
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
LOG << "ERROR: Register with id " << reg_num << " unknown." << endl;
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void oocdw_finish(int exCode)
|
void oocdw_finish(int exCode)
|
||||||
|
|||||||
@ -7,11 +7,6 @@
|
|||||||
#define OOCD_CONF_FILE_PATH "@OOCD_CONF_FILE_PATH@"
|
#define OOCD_CONF_FILE_PATH "@OOCD_CONF_FILE_PATH@"
|
||||||
#define OOCD_CONF_FILES_PATH "@OOCD_CONF_FILES_PATH@"
|
#define OOCD_CONF_FILES_PATH "@OOCD_CONF_FILES_PATH@"
|
||||||
|
|
||||||
enum arm_reg_group {
|
|
||||||
ARM_REGS_CORE,
|
|
||||||
ARM_REGS_COPROCESSOR,
|
|
||||||
};
|
|
||||||
|
|
||||||
enum halt_type {
|
enum halt_type {
|
||||||
HALT_TYPE_BP,
|
HALT_TYPE_BP,
|
||||||
HALT_TYPE_WP_READWRITE,
|
HALT_TYPE_WP_READWRITE,
|
||||||
@ -33,7 +28,7 @@ struct halt_condition {
|
|||||||
* @param rg Definition of register group of register defined by \a reg_num
|
* @param rg Definition of register group of register defined by \a reg_num
|
||||||
* @param data pointer to data as return value
|
* @param data pointer to data as return value
|
||||||
*/
|
*/
|
||||||
void oocdw_read_reg(uint32_t reg_num, enum arm_reg_group rg, uint32_t *data);
|
void oocdw_read_reg(uint32_t reg_num, uint32_t *data);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Write register value
|
* Write register value
|
||||||
@ -42,7 +37,7 @@ void oocdw_read_reg(uint32_t reg_num, enum arm_reg_group rg, uint32_t *data);
|
|||||||
* @param rg Definition of register group of register defined by \a reg_num
|
* @param rg Definition of register group of register defined by \a reg_num
|
||||||
* @param data data to be written
|
* @param data data to be written
|
||||||
*/
|
*/
|
||||||
void oocdw_write_reg(uint32_t reg_num, enum arm_reg_group rg, uint32_t data);
|
void oocdw_write_reg(uint32_t reg_num, uint32_t data);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set a halt condition
|
* Set a halt condition
|
||||||
|
|||||||
@ -8,16 +8,14 @@ regdata_t PandaArmCPU::getRegisterContent(const Register* reg) const
|
|||||||
{
|
{
|
||||||
regdata_t data;
|
regdata_t data;
|
||||||
|
|
||||||
// ToDo: ID-translation
|
oocdw_read_reg(reg->getId(), &data);
|
||||||
oocdw_read_reg(reg->getId(), ARM_REGS_CORE, &data);
|
|
||||||
|
|
||||||
return data;
|
return data;
|
||||||
}
|
}
|
||||||
|
|
||||||
void PandaArmCPU::setRegisterContent(const Register* reg, regdata_t value)
|
void PandaArmCPU::setRegisterContent(const Register* reg, regdata_t value)
|
||||||
{
|
{
|
||||||
// ToDo: ID-translation
|
oocdw_write_reg(reg->getId(), value);
|
||||||
oocdw_write_reg(reg->getId(), ARM_REGS_CORE, value);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
} // end-of-namespace: fail
|
} // end-of-namespace: fail
|
||||||
|
|||||||
@ -57,6 +57,8 @@ public:
|
|||||||
* @return the current link register address
|
* @return the current link register address
|
||||||
*/
|
*/
|
||||||
address_t getLinkRegister() const { return getRegisterContent(getRegister(RI_LR)); }
|
address_t getLinkRegister() const { return getRegisterContent(getRegister(RI_LR)); }
|
||||||
|
|
||||||
|
address_t getDfarRegister() const { return getRegisterContent(getRegister(RI_DFAR)); }
|
||||||
/**
|
/**
|
||||||
* Returns the ID of the current CPU.
|
* Returns the ID of the current CPU.
|
||||||
* @return the unique ID of \c this CPU object
|
* @return the unique ID of \c this CPU object
|
||||||
|
|||||||
Reference in New Issue
Block a user