T32 Simulator: Basic Instruction set sim for ARMM3

The T32 can simulate bare instruction sets without periphery.
For the Cortex-M3 we have complete NVIC model including Systick Timer.
Currently a simple CiAO can run on the simulator.

TODO:
 - Let memlogger log all memory accesses.
 - Interact with FailT32 for a complete simulation/FI

debuggers/t32/sim/memlogger/CMakeLists.txt

@@ -0,0 +1,10 @@
+# NVIC simulation model for the T32
+set(SRCS
+  memlogger.c
+  ../include/simul.c
+)
+
+add_library(memlogger SHARED ${SRCS})
+GET_TARGET_PROPERTY(__T32_MEMLOGGER_LIB memlogger LOCATION)
+SET(T32_MEMLOGGER_LIB "${__T32_MEMLOGGER_LIB}" CACHE INTERNAL "")
+

debuggers/t32/sim/memlogger/memlogger.c

@@ -0,0 +1,78 @@
+
+#include "simul.h"
+#include <string.h>
+/**************************************************************************
+
+	Local port structure
+
+**************************************************************************/
+
+typedef struct
+{
+    int bustype;
+    int data;
+}
+MemLog_t;
+
+
+
+static int SIMULAPI readCB(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
+{
+
+  // simulWord address = cbs->x.bus.address;
+   MemLog_t * memlog = (MemLog_t*)private;
+   cbs->x.bus.data = memlog->data;
+   //int width = cbs->x.bus.width;
+    SIMUL_Printf(processor, "MEM Read *0x%x - 0x%x\n", cbs->x.bus.address, memlog->data);
+   return SIMUL_MEMORY_OK;
+}
+
+
+static int SIMULAPI writeCB(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
+{
+   simulWord data = cbs->x.bus.data;
+   //simulWord address = cbs->x.bus.address;
+   MemLog_t * memlog = (MemLog_t*)private;
+   memlog->data = cbs->x.bus.data;
+   //int width = cbs->x.bus.width;
+    SIMUL_Printf(processor, "MEM Write *0x%x - 0x%x\n", cbs->x.bus.address, data);
+   return SIMUL_MEMORY_OK;
+}
+
+
+
+static int SIMULAPI PortReset(simulProcessor processor, simulCallbackStruct * cbs, simulPtr private)
+{
+    return SIMUL_RESET_OK;
+}
+
+
+/**************************************************************************
+
+	Entry point of the Model
+
+**************************************************************************/
+
+int SIMULAPI SIMUL_Init(simulProcessor processor, simulCallbackStruct * cbs)
+{
+    MemLog_t       *pmemlog;
+
+    strcpy(cbs->x.init.modelname, __DATE__ " MemLogger");
+
+    pmemlog = (MemLog_t *) SIMUL_Alloc(processor, sizeof(MemLog_t));
+
+//   if (cbs->x.init.argc != 3) {
+//	SIMUL_Warning(processor, "parameters: <address> <portnumber>");
+//	return SIMUL_INIT_FAIL;
+//    }
+    pmemlog->bustype = cbs->x.init.argpbustype[1];
+
+    simulWord from, to;
+    from = 0x20002074;
+    to   = 0x20002077;
+    SIMUL_RegisterResetCallback(processor, PortReset, (simulPtr) pmemlog);
+
+    SIMUL_RegisterBusWriteCallback(processor, writeCB, (simulPtr) pmemlog, pmemlog->bustype, &from, &to);
+    SIMUL_RegisterBusReadCallback(processor, readCB, (simulPtr) pmemlog, pmemlog->bustype, &from, &to);
+    return SIMUL_INIT_OK;
+}