T32 Simulator: Basic Instruction set sim for ARMM3
The T32 can simulate bare instruction sets without periphery. For the Cortex-M3 we have complete NVIC model including Systick Timer. Currently a simple CiAO can run on the simulator. TODO: - Let memlogger log all memory accesses. - Interact with FailT32 for a complete simulation/FI
This commit is contained in:
Martin Hoffmann
873
debuggers/t32/sim/armm3/nvic/nvic_system_control_block.c
Normal file
873
debuggers/t32/sim/armm3/nvic/nvic_system_control_block.c
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@ -0,0 +1,873 @@
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#include "nvic.h"
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/*************** Commands from ARM Simulator ***************/
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int CMD_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord reg;
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cbs->x.bus.clocks = 1;
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if (cbs->x.bus.cycletype==SIMUL_MEMORY_HIDDEN)
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{
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return BusWrite(&cbs->x.bus, &IntCtrl->regs.cmd);
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}
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else
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{
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reg = 0;
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return BusWrite(&cbs->x.bus, ®);
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}
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}
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int CMD_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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cbs->x.bus.clocks = 1;
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if (cbs->x.bus.cycletype==SIMUL_MEMORY_HIDDEN)
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{
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simulWord32 cmd;
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BusRead(&cbs->x.bus, &cmd);
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switch ((cmd>>24) & 0xFF)
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{
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case CMD_IS_PRESENT:
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{
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int i;
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IntCtrl->regs.cmd = 0;
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for (i=0;i<24;i++)
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{
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if ((1<<i) & cmd)
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{
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IntCtrl->regs.cmd |= 1 << (24-i);
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}
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}
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}
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break;
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case CMD_SET_INTERRUPT_ACTIVE:
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{
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/* command for setting interrupt to active state */
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int isrnum = cmd & 0x1FF;
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switch (isrnum)
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{
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case 0:
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Interrupt(processor,IntCtrl,0);
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break;
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case IRQNUM_RESET:
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case IRQNUM_NMI:
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case IRQNUM_HARDFAULT:
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case IRQNUM_MEMFAULT:
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case IRQNUM_BUSFAULT:
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case IRQNUM_USAGEFAULT:
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case IRQNUM_SVCALL:
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case IRQNUM_DEBUG:
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case IRQNUM_PENDSV:
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case IRQNUM_SYSTICK:
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IntCtrl->CurrentIrqNum = isrnum;
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ChangeActive(isrnum,1);
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ChangePending(isrnum,0);
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Interrupt(processor,IntCtrl,0);
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break;
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default:
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if (isrnum > 15 && isrnum < 256)
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{
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IntCtrl->CurrentIrqNum = isrnum;
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ChangeActive(isrnum,1);
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ChangePending(isrnum,0);
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Interrupt(processor,IntCtrl,0);
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}
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break;
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}
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}
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break;
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case CMD_SET_INTERRUPT_INACTIVE:
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{
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/* command for setting interrupt inactive */
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int isrnum = cmd & 0x1FF;
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switch (isrnum)
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{
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case IRQNUM_RESET:
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case IRQNUM_NMI:
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case IRQNUM_HARDFAULT:
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case IRQNUM_MEMFAULT:
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case IRQNUM_BUSFAULT:
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case IRQNUM_USAGEFAULT:
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case IRQNUM_SVCALL:
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case IRQNUM_DEBUG:
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case IRQNUM_PENDSV:
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case IRQNUM_SYSTICK:
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IntCtrl->CurrentIrqNum = 0;
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ChangeActive(isrnum,0);
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Interrupt(processor,IntCtrl,0);
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break;
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default:
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if (isrnum > 15 && isrnum < 256)
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{
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IntCtrl->CurrentIrqNum = 0;
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ChangeActive(isrnum,0);
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Interrupt(processor,IntCtrl,0);
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}
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break;
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}
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}
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break;
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case CMD_GET_EXCEPTION_PRIORITY:
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{
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/* command for getting priority of exception */
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int isrnum = cmd & 0x1FF;
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if (isrnum < 256)
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IntCtrl->regs.cmd = IntCtrl->IrqPriority[isrnum];
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else
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IntCtrl->regs.cmd = 0;
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}
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break;
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case CMD_GET_HIGHEST_PRIORITY:
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{
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/* command for computing highest priority */
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int highestpri = 256;
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int groupshift = (IntCtrl->regs.aircr >> 8) & 7; /* Application Interrupt and Reset Control Register - PRIGROUP */
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int groupvalue = 2 << groupshift;
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int i;
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for (i=2;i<256;i++)
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{
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if (IntCtrl->IrqActive[i])
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{
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if (IntCtrl->IrqPriority[i] < highestpri)
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{
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int subgroupvalue;
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highestpri = IntCtrl->IrqPriority[i];
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subgroupvalue = highestpri % groupvalue;
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highestpri = highestpri - subgroupvalue;
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}
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}
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}
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IntCtrl->regs.cmd = highestpri;
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}
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break;
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case CMD_GET_ACTIVE_EXCEPTION_COUNT:
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{
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/* get active exception count */
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int i,count=0;
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for (i=0;i<256;i++)
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{
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if (IntCtrl->IrqActive[i]) count++;
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}
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IntCtrl->regs.cmd = count;
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}
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break;
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case CMD_IS_EXCEPTION_ACTIVE:
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{
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/* is exception active? */
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int isrnum = cmd & 0x1FF;
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if (isrnum < 256)
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IntCtrl->regs.cmd = IntCtrl->IrqActive[isrnum];
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else
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IntCtrl->regs.cmd = 0;
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}
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break;
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case CMD_ESCALATE_TO_HARD_FAULT:
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{
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/* escalate to HardFault */
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int isrnum = cmd & 0x1FF;
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if (isrnum < 256)
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{
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IntCtrl->IrqPending[isrnum] = 0;
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IntCtrl->IrqPending[IRQNUM_HARDFAULT] = 1;
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IntCtrl->regs.hfsr |= REG_HFSR_FORCED;
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Interrupt(processor,IntCtrl,0);
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}
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}
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break;
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case CMD_CHANGE_ACTIVE_EXCEPTION:
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{
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/* change active exception */
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int active = cmd & 0x1FF;
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if ((active > 2) && (active < 256))
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{
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IntCtrl->CurrentIrqNum = active;
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IntCtrl->IrqActive[active] = 1;
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}
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}
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break;
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}
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}
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return SIMUL_MEMORY_OK;
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}
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/*************** Interrupt Control State Register ***************/
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int ICSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int i;
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simulWord32 NMIPENDSET;
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simulWord32 PENDSVSET;
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simulWord32 PENDSTSET;
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simulWord32 ISRPENDING;
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simulWord32 VECTPENDING;
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simulWord32 RETTOBASE;
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simulWord32 VECTACTIVE;
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simulWord32 reg = 0;
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int highestPriorityPending = 256;
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int groupshift = (IntCtrl->regs.aircr >> 8) & 7; /* Application Interrupt and Reset Control Register - PRIGROUP */
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int groupvalue = 2 << groupshift;
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cbs->x.bus.clocks = 1;
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NMIPENDSET = !!IntCtrl->IrqPending[IRQNUM_NMI];
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PENDSVSET = !!IntCtrl->IrqPending[IRQNUM_PENDSV];
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PENDSTSET = !!IntCtrl->IrqPending[IRQNUM_SYSTICK];
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ISRPENDING = 0;
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for (i=16;i<256;i++)
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{
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if (IntCtrl->IrqPending[i])
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{
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ISRPENDING = 1;
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break;
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}
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}
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RETTOBASE = 1;
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for (i=0;i<256;i++)
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{
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if (RETTOBASE && IntCtrl->IrqActive[i])
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{
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if (i != IntCtrl->CurrentIrqNum)
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{
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RETTOBASE = 0;
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break;
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}
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}
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}
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VECTPENDING = 0;
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for (i=2;i<256;i++)
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{
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if (IntCtrl->IrqPending[i])
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{
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if (IntCtrl->IrqPriority[i] < highestPriorityPending)
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{
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int subgroupvalue;
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highestPriorityPending = IntCtrl->IrqPriority[i];
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subgroupvalue = highestPriorityPending % groupvalue;
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highestPriorityPending = highestPriorityPending - subgroupvalue;
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VECTPENDING = i;
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}
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}
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}
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VECTACTIVE = IntCtrl->CurrentIrqNum & 0x1FF;
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reg = (NMIPENDSET << 31) | (PENDSVSET << 28) | (PENDSTSET << 26) | (ISRPENDING << 22) | (VECTPENDING << 12) | (RETTOBASE << 11) | (VECTACTIVE << 0);
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return BusWrite(&cbs->x.bus, ®);
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}
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int ICSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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int wakeUpEvent = 0;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus, ®);
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if (reg & REG_ICSR_NMIPENDSET)
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{
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ChangePending(IRQNUM_NMI,1);
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Interrupt(processor,IntCtrl,wakeUpEvent);
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}
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if (reg & REG_ICSR_PENDSVSET)
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{
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ChangePending(IRQNUM_PENDSV,1);
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Interrupt(processor,IntCtrl,wakeUpEvent);
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}
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if (reg & REG_ICSR_PENDSVCLR)
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{
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ChangePending(IRQNUM_PENDSV,0);
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Interrupt(processor,IntCtrl,wakeUpEvent);
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}
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if (reg & REG_ICSR_PENDSTSET)
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{
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ChangePending(IRQNUM_SYSTICK,1);
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Interrupt(processor,IntCtrl,wakeUpEvent);
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}
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else if (reg & REG_ICSR_PENDSTCLR)
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{
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ChangePending(IRQNUM_SYSTICK,0);
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Interrupt(processor,IntCtrl,wakeUpEvent);
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}
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return SIMUL_MEMORY_OK;
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}
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/*************** Vector Table Offset Register ***************/
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int VTOR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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cbs->x.bus.clocks = 1;
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return BusWrite(&cbs->x.bus, &IntCtrl->regs.vtor);
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}
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int VTOR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.vtor;
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BusRead(&cbs->x.bus, ®);
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IntCtrl->regs.vtor = reg & 0x3FFFFF80;
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return SIMUL_MEMORY_OK;
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}
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/*************** Application Interrupt/Reset Control Register ***************/
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int AIRCR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = (IntCtrl->regs.aircr & REG_AIRCR_MASK) | 0xFA050000;
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return BusWrite(&cbs->x.bus, ®);
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}
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int AIRCR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = IntCtrl->regs.aircr;
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BusRead(&cbs->x.bus, ®);
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if ((reg & 0xFFFF0000) == 0x05FA0000)
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{
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IntCtrl->regs.aircr = (IntCtrl->regs.aircr & ~REG_AIRCR_PRIGROUP) | (reg & REG_AIRCR_PRIGROUP);
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IntCtrl->regs.aircr = (IntCtrl->regs.aircr & ~REG_AIRCR_SYSRESETREQ) | (reg & REG_AIRCR_SYSRESETREQ);
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if (reg & REG_AIRCR_SYSRESETREQ)
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{
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RequestReset(processor);
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}
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if (reg & REG_AIRCR_VECTCLRACTIVE)
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{
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//not imlemented
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//ClearActiveState();
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}
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if (reg & REG_AIRCR_VECTRESET)
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{
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RequestReset(processor);
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}
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}
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return SIMUL_MEMORY_OK;
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}
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/*************** System Control Register ***************/
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int SCR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = (IntCtrl->regs.scr & 0x00000016);
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return BusWrite(&cbs->x.bus, ®);
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}
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int SCR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg = IntCtrl->regs.scr;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus, ®);
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IntCtrl->regs.scr = reg & REG_SCR_MASK;
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return SIMUL_MEMORY_OK;
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}
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/*************** Configuration Control Register ***************/
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int CCR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg;
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cbs->x.bus.clocks = 1;
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reg = (IntCtrl->regs.ccr & REG_CCR_MASK);
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return BusWrite(&cbs->x.bus, ®);
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}
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int CCR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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simulWord32 reg = IntCtrl->regs.ccr;
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cbs->x.bus.clocks = 1;
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BusRead(&cbs->x.bus, ®);
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IntCtrl->regs.ccr = reg & REG_CCR_MASK;
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if (IntCtrl->regs.ccr & REG_CCR_USERSETMPEND)
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{
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//This bit functionality cannot be implemented - NVIC model doesn't have access to CONTROL register
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}
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return SIMUL_MEMORY_OK;
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}
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|
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/*************** System Handlers x Priority Register ***************/
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int SHPR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
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{
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IntController *IntCtrl = (IntController*) _private;
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int idx = (cbs->x.bus.address - IntCtrl->baseaddress - SHPR_OFFSET) >> 2;
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simulWord32 reg = 0;
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cbs->x.bus.clocks = 1;
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switch (idx)
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{
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case 0: /* PRI_4 -- PRI_7 */
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reg = ((IntCtrl->IrqPriority[IRQNUM_MEMFAULT] & 0xFF) << 0) | ((IntCtrl->IrqPriority[IRQNUM_BUSFAULT] & 0xFF) << 8) | ((IntCtrl->IrqPriority[IRQNUM_USAGEFAULT] & 0xFF) << 16);
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break;
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case 1: /* PRI_8 -- PRI_11 */
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reg = ((IntCtrl->IrqPriority[IRQNUM_SVCALL] & 0xFF) << 24);
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break;
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||||
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||||
case 2: /* PRI_12 -- PRI_15 */
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reg = ((IntCtrl->IrqPriority[IRQNUM_DEBUG] & 0xFF) << 0) | ((IntCtrl->IrqPriority[IRQNUM_PENDSV] & 0xFF) << 16) | ((IntCtrl->IrqPriority[IRQNUM_SYSTICK] & 0xFF) << 24);
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||||
break;
|
||||
|
||||
default:
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||||
reg = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int SHPR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
int idx = (cbs->x.bus.address - IntCtrl->baseaddress - SHPR_OFFSET) >> 2;
|
||||
simulWord32 reg = 0;
|
||||
// simulWord32 regBackup;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
switch (idx)
|
||||
{
|
||||
case 0: /* PRI_4 -- PRI_7 */
|
||||
reg = ((IntCtrl->IrqPriority[IRQNUM_MEMFAULT] & 0xFF) << 0) | ((IntCtrl->IrqPriority[IRQNUM_BUSFAULT] & 0xFF) << 8) | ((IntCtrl->IrqPriority[IRQNUM_USAGEFAULT] & 0xFF) << 16);
|
||||
break;
|
||||
|
||||
case 1: /* PRI_8 -- PRI_11 */
|
||||
reg = ((IntCtrl->IrqPriority[IRQNUM_SVCALL] & 0xFF) << 24);
|
||||
break;
|
||||
|
||||
case 2: /* PRI_12 -- PRI_15 */
|
||||
reg = ((IntCtrl->IrqPriority[IRQNUM_DEBUG] & 0xFF) << 0) | ((IntCtrl->IrqPriority[IRQNUM_PENDSV] & 0xFF) << 16) | ((IntCtrl->IrqPriority[IRQNUM_SYSTICK] & 0xFF) << 24);
|
||||
break;
|
||||
|
||||
default:
|
||||
reg = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
// regBackup = reg;
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
switch (idx)
|
||||
{
|
||||
case 0: /* PRI_4 -- PRI_7 */
|
||||
IntCtrl->IrqPriority[IRQNUM_MEMFAULT] = (reg >> 0) & 0xFF;
|
||||
IntCtrl->IrqPriority[IRQNUM_BUSFAULT] = (reg >> 8) & 0xFF;
|
||||
IntCtrl->IrqPriority[IRQNUM_USAGEFAULT] = (reg >> 16) & 0xFF;
|
||||
break;
|
||||
|
||||
case 1: /* PRI_8 -- PRI_11 */
|
||||
IntCtrl->IrqPriority[IRQNUM_SVCALL] = (reg >> 24) & 0xFF;
|
||||
break;
|
||||
|
||||
case 2: /* PRI_12 -- PRI_15 */
|
||||
IntCtrl->IrqPriority[IRQNUM_DEBUG] = (reg >> 0) & 0xFF;
|
||||
IntCtrl->IrqPriority[IRQNUM_PENDSV] = (reg >> 16) & 0xFF;
|
||||
IntCtrl->IrqPriority[IRQNUM_SYSTICK] = (reg >> 24) & 0xFF;
|
||||
break;
|
||||
|
||||
default:
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** System Handler Control and State Register ***************/
|
||||
|
||||
int SHCSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
|
||||
simulWord32 USGFAULTENA, BUSFAULTENA, MEMFAULTENA;
|
||||
simulWord32 SVCALLPENDED, BUSFAULTPENDED, MEMFAULTPENDED, USGFAULTPENDED;
|
||||
simulWord32 SYSTICKACT, PENDSVACT, MONITORACT, SVCALLACT, USGFAULTACT, BUSFAULTACT, MEMFAULTACT;
|
||||
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
USGFAULTENA = IntCtrl->IrqEnable[IRQNUM_USAGEFAULT];
|
||||
BUSFAULTENA = IntCtrl->IrqEnable[IRQNUM_BUSFAULT];
|
||||
MEMFAULTENA = IntCtrl->IrqEnable[IRQNUM_MEMFAULT];
|
||||
|
||||
SVCALLPENDED = IntCtrl->IrqPending[IRQNUM_SVCALL];
|
||||
BUSFAULTPENDED = IntCtrl->IrqPending[IRQNUM_BUSFAULT];
|
||||
MEMFAULTPENDED = IntCtrl->IrqPending[IRQNUM_MEMFAULT];
|
||||
USGFAULTPENDED = IntCtrl->IrqPending[IRQNUM_USAGEFAULT];
|
||||
|
||||
SYSTICKACT = IntCtrl->IrqActive[IRQNUM_SYSTICK];
|
||||
PENDSVACT = IntCtrl->IrqActive[IRQNUM_PENDSV];
|
||||
MONITORACT = IntCtrl->IrqActive[IRQNUM_DEBUG];
|
||||
SVCALLACT = IntCtrl->IrqActive[IRQNUM_SVCALL];
|
||||
USGFAULTACT = IntCtrl->IrqActive[IRQNUM_USAGEFAULT];
|
||||
BUSFAULTACT = IntCtrl->IrqActive[IRQNUM_BUSFAULT];
|
||||
MEMFAULTACT = IntCtrl->IrqActive[IRQNUM_MEMFAULT];
|
||||
|
||||
reg =
|
||||
((USGFAULTENA)?(REG_SHCSR_USGFAULTENA):(0)) |
|
||||
((BUSFAULTENA)?(REG_SHCSR_BUSFAULTENA):(0)) |
|
||||
((MEMFAULTENA)?(REG_SHCSR_MEMFAULTENA):(0)) |
|
||||
|
||||
((SVCALLPENDED)?(REG_SHCSR_SVCALLPENDED):(0)) |
|
||||
((BUSFAULTPENDED)?(REG_SHCSR_BUSFAULTPENDED):(0)) |
|
||||
((MEMFAULTPENDED)?(REG_SHCSR_MEMFAULTPENDED):(0)) |
|
||||
((USGFAULTPENDED)?(REG_SHCSR_USGFAULTPENDED):(0)) |
|
||||
|
||||
((SYSTICKACT)?(REG_SHCSR_SYSTICKACT):(0)) |
|
||||
((PENDSVACT)?(REG_SHCSR_PENDSVACT):(0)) |
|
||||
((MONITORACT)?(REG_SHCSR_MONITORACT):(0)) |
|
||||
((SVCALLACT)?(REG_SHCSR_SVCALLACT):(0)) |
|
||||
((USGFAULTACT)?(REG_SHCSR_USGFAULTACT):(0)) |
|
||||
((BUSFAULTACT)?(REG_SHCSR_BUSFAULTACT):(0)) |
|
||||
((MEMFAULTACT)?(REG_SHCSR_MEMFAULTACT):(0));
|
||||
;
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int SHCSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
int wakeUpEvent = 0;
|
||||
|
||||
simulWord32 USGFAULTENA, BUSFAULTENA, MEMFAULTENA;
|
||||
simulWord32 SVCALLPENDED, BUSFAULTPENDED, MEMFAULTPENDED, USGFAULTPENDED;
|
||||
simulWord32 SYSTICKACT, PENDSVACT, MONITORACT, SVCALLACT, USGFAULTACT, BUSFAULTACT, MEMFAULTACT;
|
||||
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
USGFAULTENA = IntCtrl->IrqEnable[IRQNUM_USAGEFAULT];
|
||||
BUSFAULTENA = IntCtrl->IrqEnable[IRQNUM_BUSFAULT];
|
||||
MEMFAULTENA = IntCtrl->IrqEnable[IRQNUM_MEMFAULT];
|
||||
|
||||
SVCALLPENDED = IntCtrl->IrqPending[IRQNUM_SVCALL];
|
||||
BUSFAULTPENDED = IntCtrl->IrqPending[IRQNUM_BUSFAULT];
|
||||
MEMFAULTPENDED = IntCtrl->IrqPending[IRQNUM_MEMFAULT];
|
||||
USGFAULTPENDED = IntCtrl->IrqPending[IRQNUM_USAGEFAULT];
|
||||
|
||||
SYSTICKACT = IntCtrl->IrqActive[IRQNUM_SYSTICK];
|
||||
PENDSVACT = IntCtrl->IrqActive[IRQNUM_PENDSV];
|
||||
MONITORACT = IntCtrl->IrqActive[IRQNUM_DEBUG];
|
||||
SVCALLACT = IntCtrl->IrqActive[IRQNUM_SVCALL];
|
||||
USGFAULTACT = IntCtrl->IrqActive[IRQNUM_USAGEFAULT];
|
||||
BUSFAULTACT = IntCtrl->IrqActive[IRQNUM_BUSFAULT];
|
||||
MEMFAULTACT = IntCtrl->IrqActive[IRQNUM_MEMFAULT];
|
||||
|
||||
reg =
|
||||
((USGFAULTENA)?(REG_SHCSR_USGFAULTENA):(0)) |
|
||||
((BUSFAULTENA)?(REG_SHCSR_BUSFAULTENA):(0)) |
|
||||
((MEMFAULTENA)?(REG_SHCSR_MEMFAULTENA):(0)) |
|
||||
|
||||
((SVCALLPENDED)?(REG_SHCSR_SVCALLPENDED):(0)) |
|
||||
((BUSFAULTPENDED)?(REG_SHCSR_BUSFAULTPENDED):(0)) |
|
||||
((MEMFAULTPENDED)?(REG_SHCSR_MEMFAULTPENDED):(0)) |
|
||||
((USGFAULTPENDED)?(REG_SHCSR_USGFAULTPENDED):(0)) |
|
||||
|
||||
((SYSTICKACT)?(REG_SHCSR_SYSTICKACT):(0)) |
|
||||
((PENDSVACT)?(REG_SHCSR_PENDSVACT):(0)) |
|
||||
((MONITORACT)?(REG_SHCSR_MONITORACT):(0)) |
|
||||
((SVCALLACT)?(REG_SHCSR_SVCALLACT):(0)) |
|
||||
((USGFAULTACT)?(REG_SHCSR_USGFAULTACT):(0)) |
|
||||
((BUSFAULTACT)?(REG_SHCSR_BUSFAULTACT):(0)) |
|
||||
((MEMFAULTACT)?(REG_SHCSR_MEMFAULTACT):(0));
|
||||
;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
ChangeEnable(IRQNUM_USAGEFAULT,reg & REG_SHCSR_USGFAULTENA);
|
||||
ChangeEnable(IRQNUM_BUSFAULT,reg & REG_SHCSR_BUSFAULTENA);
|
||||
ChangeEnable(IRQNUM_MEMFAULT,reg & REG_SHCSR_MEMFAULTENA);
|
||||
|
||||
ChangePending(IRQNUM_SVCALL, reg & REG_SHCSR_SVCALLPENDED);
|
||||
ChangePending(IRQNUM_BUSFAULT, reg & REG_SHCSR_BUSFAULTPENDED);
|
||||
ChangePending(IRQNUM_MEMFAULT, reg & REG_SHCSR_MEMFAULTPENDED);
|
||||
ChangePending(IRQNUM_USAGEFAULT,reg & REG_SHCSR_USGFAULTPENDED);
|
||||
|
||||
ChangeActive(IRQNUM_SYSTICK,reg & REG_SHCSR_SYSTICKACT);
|
||||
ChangeActive(IRQNUM_PENDSV,reg & REG_SHCSR_PENDSVACT);
|
||||
ChangeActive(IRQNUM_DEBUG,reg & REG_SHCSR_MONITORACT);
|
||||
ChangeActive(IRQNUM_SVCALL,reg & REG_SHCSR_SVCALLACT);
|
||||
ChangeActive(IRQNUM_USAGEFAULT,reg & REG_SHCSR_USGFAULTACT);
|
||||
ChangeActive(IRQNUM_BUSFAULT,reg & REG_SHCSR_BUSFAULTACT);
|
||||
ChangeActive(IRQNUM_MEMFAULT,reg & REG_SHCSR_MEMFAULTACT);
|
||||
|
||||
Interrupt(processor,IntCtrl,wakeUpEvent);
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Configurable Fault Status Register ***************/
|
||||
|
||||
int CFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
reg = IntCtrl->regs.cfsr & REG_CFSR_MASK;
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int CFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.cfsr &= ~(reg & REG_CFSR_MASK);
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Hard Fault Status Register ***************/
|
||||
|
||||
int HFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
reg = IntCtrl->regs.hfsr & REG_HFSR_MASK;
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int HFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.hfsr &= ~(reg & REG_HFSR_MASK);
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Debug Fault Status Register ***************/
|
||||
|
||||
int DFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
reg = IntCtrl->regs.dfsr & REG_DFSR_MASK;
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int DFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.dfsr &= ~(reg & REG_DFSR_MASK);
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Memory Manage Address Register ***************/
|
||||
|
||||
int MMAR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
cbs->x.bus.clocks = 1;
|
||||
return BusWrite(&cbs->x.bus, &IntCtrl->regs.mmar);
|
||||
}
|
||||
|
||||
int MMAR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = IntCtrl->regs.mmar;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.mmar = reg;
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Bus Fault Address Register ***************/
|
||||
|
||||
int BFAR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
cbs->x.bus.clocks = 1;
|
||||
return BusWrite(&cbs->x.bus, &IntCtrl->regs.bfar);
|
||||
}
|
||||
|
||||
int BFAR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = IntCtrl->regs.bfar;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.bfar = reg;
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Auxiliary Fault Status Register ***************/
|
||||
|
||||
int AFSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = IntCtrl->regs.afsr;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int AFSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.afsr &= ~(reg & REG_AFSR_MASK);
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
|
||||
/*************** Debug Halting Control and Status Register ***************/
|
||||
|
||||
int DHCSR_Read(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = IntCtrl->regs.dhcsr;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
return BusWrite(&cbs->x.bus, ®);
|
||||
}
|
||||
|
||||
int DHCSR_Write(simulProcessor processor, simulCallbackStruct * cbs, simulPtr _private)
|
||||
{
|
||||
IntController *IntCtrl = (IntController*) _private;
|
||||
simulWord32 reg = 0;
|
||||
|
||||
cbs->x.bus.clocks = 1;
|
||||
|
||||
BusRead(&cbs->x.bus, ®);
|
||||
|
||||
IntCtrl->regs.dhcsr = reg;
|
||||
|
||||
return SIMUL_MEMORY_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user