diff --git a/src/core/sal/arm/ArmArchitecture.cc b/src/core/sal/arm/ArmArchitecture.cc
index cf2475df..4121ef8a 100644
--- a/src/core/sal/arm/ArmArchitecture.cc
+++ b/src/core/sal/arm/ArmArchitecture.cc
@@ -9,15 +9,17 @@ ArmArchitecture::ArmArchitecture()
 	// TODO: Add missing registers
 	// 16x 32-Bit GP Registers
 	for (int i = 0; i < 16; i++) {
-		Register *reg = new Register(i, RT_GP, 32);
-		// Build and set the register name:
-		std::stringstream sstr;
-		sstr << "R" << i+1;
-		reg->setName(sstr.str().c_str());
-		m_addRegister(reg);
+		if (i != RI_IP) { // IP will be added separately (see below)
+			Register *reg = new Register(i, RT_GP, 32);
+			// Build and set the register name:
+			std::stringstream sstr;
+			sstr << "R" << i+1;
+			reg->setName(sstr.str().c_str());
+			m_addRegister(reg);
+		}
 	}
 
-	// Instruction Pointer
+	// Instruction Pointer:
 	Register *reg = new Register(RI_IP, RT_IP, 32);
 	reg->setName("IP");
 	m_addRegister(reg);
diff --git a/src/core/sal/arm/ArmArchitecture.hpp b/src/core/sal/arm/ArmArchitecture.hpp
index 45c07a30..5ea821fe 100644
--- a/src/core/sal/arm/ArmArchitecture.hpp
+++ b/src/core/sal/arm/ArmArchitecture.hpp
@@ -67,7 +67,9 @@ enum GPRegIndex {
 	RI_R14_FIQ
 };
 
-// TODO: Enum for misc registers
+// TODO: Enum for misc registers, see (e.g.)
+//       simulators/gem5/src/arch/arm/miscregs.hh and
+//       simulators/gem5/src/arch/arm/intregs.hh
 
 } // end-of-namespace: fail
 
diff --git a/src/core/sal/gem5/Gem5Wrapper.cc b/src/core/sal/gem5/Gem5Wrapper.cc
index 65a8aaaf..149c4822 100644
--- a/src/core/sal/gem5/Gem5Wrapper.cc
+++ b/src/core/sal/gem5/Gem5Wrapper.cc
@@ -11,12 +11,8 @@ namespace fail {
 regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx)
 {
 	switch (type) {
-	case RT_GP:
-		if (idx == 15) {
-			return sys->getThreadContext(id)->pcState().pc();
-		}
-		return sys->getThreadContext(id)->readIntReg(idx);
-	case RT_FP: return sys->getThreadContext(id)->readFloatReg(idx); // FIXME: correct?! (FP <-> Float?!)
+	case RT_GP: // pass on...
+	case RT_FP:	return sys->getThreadContext(id)->readIntReg(idx);
 	case RT_ST: return sys->getThreadContext(id)->readMiscReg(idx);
 	case RT_IP: return sys->getThreadContext(id)->pcState().pc();
 	}
@@ -29,13 +25,13 @@ void SetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t
                         regdata_t value)
 {
 	switch (type) {
-	case RT_GP: sys->getThreadContext(id)->setIntReg(idx, value); break;
-	case RT_FP: sys->getThreadContext(id)->setFloatReg(idx, value); break; // FIXME: correct?! (FP <-> Float?!)
-	case RT_ST: sys->getThreadContext(id)->setMiscReg(idx, value); break;
-	case RT_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); break;
+	case RT_GP: // pass on...
+	case RT_FP: sys->getThreadContext(id)->setIntReg(idx, value); return;
+	case RT_ST: sys->getThreadContext(id)->setMiscReg(idx, value); return;
+	case RT_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); return;
 	}
 	// This shouldn't be reached if a valid register is passed
-	assert(false && "FATAL ERROR: invalid register type (should never be reached)!");
+	assert(false && "FATAL ERROR: Invalid register type (should never be reached)!");
 }
 
 void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest)