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Use common register names in experiment code.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1255 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2012-05-18 12:11:22 +00:00
parent 76e3f53fec
commit 8973a8d40a
4 changed files with 20 additions and 33 deletions
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10
core/experiments/hscsimple/experiment.cc
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@ -28,7 +28,7 @@ bool hscsimpleExperiment::run()
sal::simulator.addEventAndWait(&mainbp);
log << "breakpoint reached, saving" << endl;
sal::simulator.save("hello.state");
#elif 1
#elif 0
// STEP 2
log << "restoring ..." << endl;
sal::simulator.restore("hello.state");
@ -38,12 +38,8 @@ bool hscsimpleExperiment::run()
fi::BPEvent breakpoint(0x3c9e); // square(x) ret instruction
sal::simulator.addEventAndWait(&breakpoint);
log << "injecting hellish fault" << endl;
#if BX_SUPPORT_X86_64
int reg = sal::RID_RAX;
#else
int reg = sal::RID_EAX;
#endif
sal::simulator.getRegisterManager().getRegister(reg)->setData(666);
// RID_CAX is the RAX register in 64 bit mode and EAX in 32 bit mode:
sal::simulator.getRegisterManager().getRegister(sal::RID_CAX)->setData(666);
log << "waiting for last main() instruction" << endl;
breakpoint.setWatchInstructionPointer(0x3c92);
sal::simulator.addEventAndWait(&breakpoint);