debuggers: import openocd-0.7.0

Initial check-in of openocd-0.7.0 as it can be downloaded from
http://sourceforge.net/projects/openocd/files/openocd/0.7.0/

Any modifications will follow.

Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55

debuggers/openocd/tcl/target/samsung_s3c2450.cfg

@@ -0,0 +1,48 @@
+# Target configuration for the Samsung 2450 system on chip
+# Processor       : ARM926ejs (wb) rev 0 (v4l)
+# Info:   JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F
+
+
+# FIX!!! what to use here?
+#
+# RCLK?
+#
+# adapter_khz 0
+#
+# Really low clock during reset?
+#
+# adapter_khz 1
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME s3c2450
+}
+
+if { [info exists ENDIAN] } {
+  set _ENDIAN $ENDIAN
+} else {
+ # this defaults to a bigendian
+  set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+  set _CPUTAPID $CPUTAPID
+} else {
+  set _CPUTAPID 0x07926f0f
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# FIX!!!!! should this really use srst_pulls_trst?
+# With srst_pulls_trst "reset halt" will not reset into the
+# halted mode, but rather "reset run" and then halt the target.
+#
+# However, without "srst_pulls_trst", then "reset halt" produces weird
+# errors:
+# WARNING: unknown debug reason: 0x0
+reset_config trst_and_srst