debuggers: import openocd-0.7.0

Initial check-in of openocd-0.7.0 as it can be downloaded from
http://sourceforge.net/projects/openocd/files/openocd/0.7.0/

Any modifications will follow.

Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55

debuggers/openocd/tcl/target/imx31.cfg

@@ -0,0 +1,68 @@
+# imx31 config
+#
+
+reset_config trst_and_srst srst_gates_jtag
+
+adapter_nsrst_delay 5
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx31
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x2190101d
+}
+
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
+} else {
+   set _ETBTAPID 0x2b900f0f
+}
+
+#========================================
+
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
+
+# The "SDMA" - <S>mart <DMA> controller debug tap
+# Based on some IO pins - this can be disabled & removed
+# See diagram: 6-14
+#   SIGNAL NAME:
+#    SJC_MOD - controls multiplexer - disables ARM1136
+#    SDMA_BYPASS - disables SDMA    -
+#
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
+
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb