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debuggers: import openocd-0.7.0

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Initial check-in of openocd-0.7.0 as it can be downloaded from
http://sourceforge.net/projects/openocd/files/openocd/0.7.0/

Any modifications will follow.

Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55
This commit is contained in:
Lars Rademacher
2013-10-21 00:50:02 +02:00
parent 85fffe007e
commit 83d72a091e
1148 changed files with 571445 additions and 0 deletions
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211
debuggers/openocd/tcl/target/amdm37x.cfg Normal file
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#
# Copyright (C) 2010-2011 by Karl Kurbjun
# Copyright (C) 2009-2011 by Øyvind Harboe
# Copyright (C) 2009 by David Brownell
# Copyright (C) 2009 by Magnus Lundin
#
# TI AM/DM37x
# http://www.ti.com/litv/pdf/sprugn4b
#
# This script is based on the AM3517 initialization. It should be considered
# preliminary since it needs more complete testing and only the basic
# operations work.
#
###############################################################################
# User modifiable parameters
###############################################################################
# This script uses the variable CHIPTYPE to determine whether this is an AM35x
# or DM37x target. If CHIPTYPE is not set it will error out.
if { [info exists CHIPTYPE] } {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME $CHIPTYPE
}
switch $CHIPTYPE {
dm37x {
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
}
am35x {
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
set _JRC_TAPID "-expected-id 0x0b7ae02f"
}
default {
error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
}
}
} else {
error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
}
# Run the adapter at the fastest acceptable speed with the slowest possible
# core clock.
adapter_khz 10
###############################################################################
# JTAG setup
# The OpenOCD commands are described in the TAP Declaration section
# http://openocd.berlios.de/doc/html/TAP-Declaration.html
###############################################################################
# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More
# can be read about this module in sprugn4b under chapter 27: "Debug and
# Emulation". The module is used to route the JTAG chain to the various
# subsystems in the chip.
source [find target/icepick.cfg]
# The TAP order should be described from the TDO connection in OpenOCD to the
# TDI pin. The OpenOCD FAQ describes this in more detail:
# http://openocd.berlios.de/doc/html/FAQ.html
# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:
#
# Device | TAP number
# ---------|------------
# DAP | 3
# Sequencer| 2 Note: The sequencer is an ARM968
# DSP | 1
# D2D | 0
#
# Right now the only secondary tap enabled is the DAP so the rest are left
# undescribed.
######
# Start of Chain Description
# The Secondary TAPs all have enable functions defined for use with the ICEpick
# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
# the TAP numbers for ICEpick do not change.
#
# TODO: A disable function should also be added.
######
# Secondary TAP: DAP is closest to the TDO output
# The TAP enable event also needs to be described
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# These taps are only present in the DM37x series.
if { $CHIPTYPE == "dm37x" } {
# Secondary TAP: Sequencer (ARM968) it is not in the chain by default
# The ICEpick can be used to enable it in the chain.
jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
jtag configure $_CHIPNAME.arm2 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 2"
# Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
# The ICEpick can be used to enable it in the chain.
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
jtag configure $_CHIPNAME.dsp -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
}
# Secondary TAP: D2D it is not in the chain by default (-disable)
# The ICEpick can be used to enable it in the chain.
# This IRLEN is probably incorrect - not sure where the documentation is.
jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
jtag configure $_CHIPNAME.d2d -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick - it is closest to TDI so last in the chain
eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
######
# End of Chain Description
######
######
# Start JTAG TAP events
######
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# Enable the DAP TAP
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
######
# End JTAG TAP events
######
###############################################################################
# Target Setup:
# This section is described in the OpenOCD documentation under CPU Configuration
# http://openocd.berlios.de/doc/html/CPU-Configuration.html
###############################################################################
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
######
# Start Target Reset Event Setup:
######
# Set the JTAG clock down to 10 kHz to be sure that it will work with the
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
# Describe the reset assert process for openocd - this is asserted with the
# ICEPick
$_TARGETNAME configure -event "reset-assert" {
global _CHIPNAME
# assert warm system reset through ICEPick
icepick_c_wreset $_CHIPNAME.jrc
}
# After the reset is asserted we need to re-initialize debugging and speed up
# the JTAG clock.
$_TARGETNAME configure -event reset-assert-post {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
adapter_khz 1000
}
$_TARGETNAME configure -event gdb-attach {
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
echo "Halting target"
halt
}
######
# End Target Reset Event Setup:
######
###############################################################################
# Target Functions
# Add any functions needed for the target here
###############################################################################
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc amdm37x_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# access to the signal appears to be implementation specific. TI does not
# describe this register much except a quick line that states DBGEM (sic) is
# at this address and this bit.
$target mww phys 0x5401d030 0x00002000
}