debuggers: import openocd-0.7.0
Initial check-in of openocd-0.7.0 as it can be downloaded from http://sourceforge.net/projects/openocd/files/openocd/0.7.0/ Any modifications will follow. Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55
This commit is contained in:
Lars Rademacher
53
debuggers/openocd/tcl/target/aduc702x.cfg
Normal file
53
debuggers/openocd/tcl/target/aduc702x.cfg
Normal file
@ -0,0 +1,53 @@
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
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set _CHIPNAME aduc702x
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
# This config file was defaulting to big endian..
|
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set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
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||||
set _CPUTAPID $CPUTAPID
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} else {
|
||||
set _CPUTAPID 0x3f0f0f0f
|
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}
|
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|
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adapter_nsrst_delay 200
|
||||
jtag_ntrst_delay 200
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||||
|
||||
## JTAG scan chain
|
||||
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
|
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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|
||||
##
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||||
## Target configuration
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##
|
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
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|
||||
# allocate the entire SRAM as working area
|
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$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
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## flash configuration
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# only target number is needed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
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## If you use the watchdog, the following code makes sure that the board
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||||
## doesn't reboot when halted via JTAG. Yes, on the older generation
|
||||
## AdUC702x, timer3 continues running even when the CPU is halted.
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proc watchdog_service {} {
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global watchdog_hdl
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mww 0xffff036c 0
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# echo "watchdog!!"
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set watchdog_hdl [after 500 watchdog_service]
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}
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||||
$_TARGETNAME configure -event reset-halt-post { watchdog_service }
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$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }
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76
debuggers/openocd/tcl/target/am335x.cfg
Normal file
76
debuggers/openocd/tcl/target/am335x.cfg
Normal file
@ -0,0 +1,76 @@
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME am335x
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}
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|
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# This chip contains an IcePick-D JTAG router. The IcePick-C configuration is almost
|
||||
# compatible, but it doesn't work. For now, we will just embed the IcePick-D
|
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# routines here.
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proc icepick_d_tapenable {jrc port} {
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# select router
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irscan $jrc 7 -endstate IRPAUSE
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drscan $jrc 8 0x89 -endstate DRPAUSE
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||||
# set ip control
|
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irscan $jrc 2 -endstate IRPAUSE
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drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
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|
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# for icepick_D
|
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irscan $jrc 2 -endstate IRPAUSE
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drscan $jrc 32 0xe0002008 -endstate DRPAUSE
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|
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irscan $jrc 0x3F -endstate RUN/IDLE
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runtest 10
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}
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#
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# M3 DAP
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#
|
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if { [info exists M3_DAP_TAPID] } {
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set _M3_DAP_TAPID $M3_DAP_TAPID
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} else {
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set _M3_DAP_TAPID 0x4b6b902f
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}
|
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jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
|
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jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
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|
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#
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# Main DAP
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#
|
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if { [info exists DAP_TAPID] } {
|
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set _DAP_TAPID $DAP_TAPID
|
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} else {
|
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set _DAP_TAPID 0x4b6b902f
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
|
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jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
|
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|
||||
#
|
||||
# ICEpick-D (JTAG route controller)
|
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#
|
||||
if { [info exists JRC_TAPID] } {
|
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set _JRC_TAPID $JRC_TAPID
|
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} else {
|
||||
set _JRC_TAPID 0x0b94402f
|
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}
|
||||
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
|
||||
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
|
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# some TCK tycles are required to activate the DEBUG power domain
|
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
|
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|
||||
#
|
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# Cortex A8 target
|
||||
#
|
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set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
|
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|
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# SRAM: 64K at 0x4030.0000; use the first 16K
|
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$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
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||||
|
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$_TARGETNAME configure -event gdb-attach {
|
||||
cortex_a dbginit
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halt
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||||
}
|
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|
||||
211
debuggers/openocd/tcl/target/amdm37x.cfg
Normal file
211
debuggers/openocd/tcl/target/amdm37x.cfg
Normal file
@ -0,0 +1,211 @@
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#
|
||||
# Copyright (C) 2010-2011 by Karl Kurbjun
|
||||
# Copyright (C) 2009-2011 by Øyvind Harboe
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# Copyright (C) 2009 by David Brownell
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# Copyright (C) 2009 by Magnus Lundin
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#
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# TI AM/DM37x
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||||
# http://www.ti.com/litv/pdf/sprugn4b
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||||
#
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# This script is based on the AM3517 initialization. It should be considered
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# preliminary since it needs more complete testing and only the basic
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||||
# operations work.
|
||||
#
|
||||
|
||||
###############################################################################
|
||||
# User modifiable parameters
|
||||
###############################################################################
|
||||
|
||||
# This script uses the variable CHIPTYPE to determine whether this is an AM35x
|
||||
# or DM37x target. If CHIPTYPE is not set it will error out.
|
||||
if { [info exists CHIPTYPE] } {
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME $CHIPTYPE
|
||||
}
|
||||
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||||
switch $CHIPTYPE {
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dm37x {
|
||||
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
|
||||
set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
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}
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am35x {
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
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||||
set _JRC_TAPID "-expected-id 0x0b7ae02f"
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}
|
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default {
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error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
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}
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}
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} else {
|
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error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
|
||||
}
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# Run the adapter at the fastest acceptable speed with the slowest possible
|
||||
# core clock.
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adapter_khz 10
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||||
###############################################################################
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# JTAG setup
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||||
# The OpenOCD commands are described in the TAP Declaration section
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# http://openocd.berlios.de/doc/html/TAP-Declaration.html
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###############################################################################
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||||
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||||
# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More
|
||||
# can be read about this module in sprugn4b under chapter 27: "Debug and
|
||||
# Emulation". The module is used to route the JTAG chain to the various
|
||||
# subsystems in the chip.
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||||
source [find target/icepick.cfg]
|
||||
|
||||
# The TAP order should be described from the TDO connection in OpenOCD to the
|
||||
# TDI pin. The OpenOCD FAQ describes this in more detail:
|
||||
# http://openocd.berlios.de/doc/html/FAQ.html
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||||
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||||
# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:
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||||
#
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||||
# Device | TAP number
|
||||
# ---------|------------
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||||
# DAP | 3
|
||||
# Sequencer| 2 Note: The sequencer is an ARM968
|
||||
# DSP | 1
|
||||
# D2D | 0
|
||||
#
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||||
# Right now the only secondary tap enabled is the DAP so the rest are left
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||||
# undescribed.
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||||
|
||||
######
|
||||
# Start of Chain Description
|
||||
# The Secondary TAPs all have enable functions defined for use with the ICEpick
|
||||
# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
|
||||
# the TAP numbers for ICEpick do not change.
|
||||
#
|
||||
# TODO: A disable function should also be added.
|
||||
######
|
||||
|
||||
# Secondary TAP: DAP is closest to the TDO output
|
||||
# The TAP enable event also needs to be described
|
||||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
|
||||
jtag configure $_CHIPNAME.dap -event tap-enable \
|
||||
"icepick_c_tapenable $_CHIPNAME.jrc 3"
|
||||
|
||||
# These taps are only present in the DM37x series.
|
||||
if { $CHIPTYPE == "dm37x" } {
|
||||
# Secondary TAP: Sequencer (ARM968) it is not in the chain by default
|
||||
# The ICEpick can be used to enable it in the chain.
|
||||
jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
|
||||
jtag configure $_CHIPNAME.arm2 -event tap-enable \
|
||||
"icepick_c_tapenable $_CHIPNAME.jrc 2"
|
||||
|
||||
# Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
|
||||
# The ICEpick can be used to enable it in the chain.
|
||||
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
|
||||
jtag configure $_CHIPNAME.dsp -event tap-enable \
|
||||
"icepick_c_tapenable $_CHIPNAME.jrc 1"
|
||||
}
|
||||
|
||||
# Secondary TAP: D2D it is not in the chain by default (-disable)
|
||||
# The ICEpick can be used to enable it in the chain.
|
||||
# This IRLEN is probably incorrect - not sure where the documentation is.
|
||||
jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
|
||||
jtag configure $_CHIPNAME.d2d -event tap-enable \
|
||||
"icepick_c_tapenable $_CHIPNAME.jrc 0"
|
||||
|
||||
# Primary TAP: ICEpick - it is closest to TDI so last in the chain
|
||||
eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
|
||||
|
||||
######
|
||||
# End of Chain Description
|
||||
######
|
||||
|
||||
######
|
||||
# Start JTAG TAP events
|
||||
######
|
||||
|
||||
# some TCK tycles are required to activate the DEBUG power domain
|
||||
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
|
||||
|
||||
# Enable the DAP TAP
|
||||
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
|
||||
|
||||
######
|
||||
# End JTAG TAP events
|
||||
######
|
||||
|
||||
###############################################################################
|
||||
# Target Setup:
|
||||
# This section is described in the OpenOCD documentation under CPU Configuration
|
||||
# http://openocd.berlios.de/doc/html/CPU-Configuration.html
|
||||
###############################################################################
|
||||
|
||||
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
|
||||
|
||||
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
|
||||
# 16K to be used as a scratchpad for OpenOCD.
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
|
||||
|
||||
######
|
||||
# Start Target Reset Event Setup:
|
||||
######
|
||||
|
||||
# Set the JTAG clock down to 10 kHz to be sure that it will work with the
|
||||
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
|
||||
# *after* PLL and clock tree setup.
|
||||
|
||||
$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
|
||||
|
||||
# Describe the reset assert process for openocd - this is asserted with the
|
||||
# ICEPick
|
||||
$_TARGETNAME configure -event "reset-assert" {
|
||||
|
||||
global _CHIPNAME
|
||||
|
||||
# assert warm system reset through ICEPick
|
||||
icepick_c_wreset $_CHIPNAME.jrc
|
||||
}
|
||||
|
||||
# After the reset is asserted we need to re-initialize debugging and speed up
|
||||
# the JTAG clock.
|
||||
|
||||
$_TARGETNAME configure -event reset-assert-post {
|
||||
|
||||
global _TARGETNAME
|
||||
amdm37x_dbginit $_TARGETNAME
|
||||
adapter_khz 1000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event gdb-attach {
|
||||
|
||||
global _TARGETNAME
|
||||
amdm37x_dbginit $_TARGETNAME
|
||||
|
||||
echo "Halting target"
|
||||
halt
|
||||
}
|
||||
|
||||
######
|
||||
# End Target Reset Event Setup:
|
||||
######
|
||||
|
||||
###############################################################################
|
||||
# Target Functions
|
||||
# Add any functions needed for the target here
|
||||
###############################################################################
|
||||
|
||||
# Run this to enable invasive debugging. This is run automatically in the
|
||||
# reset sequence.
|
||||
proc amdm37x_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a dbginit
|
||||
|
||||
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
|
||||
# access to the signal appears to be implementation specific. TI does not
|
||||
# describe this register much except a quick line that states DBGEM (sic) is
|
||||
# at this address and this bit.
|
||||
$target mww phys 0x5401d030 0x00002000
|
||||
}
|
||||
|
||||
57
debuggers/openocd/tcl/target/ar71xx.cfg
Normal file
57
debuggers/openocd/tcl/target/ar71xx.cfg
Normal file
@ -0,0 +1,57 @@
|
||||
# Atheros AR71xx MIPS 24Kc SoC.
|
||||
# tested on PB44 refererence board
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
reset_config trst_and_srst
|
||||
|
||||
set CHIPNAME ar71xx
|
||||
|
||||
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
|
||||
|
||||
set TARGETNAME $CHIPNAME.cpu
|
||||
target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
|
||||
|
||||
$TARGETNAME configure -event reset-halt-post {
|
||||
#setup PLL to lowest common denominator 300/300/150 setting
|
||||
mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0
|
||||
mww 0xb8050000 0x800f40a3 ;# send to PLL
|
||||
|
||||
#next command will reset for PLL changes to take effect
|
||||
mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC)
|
||||
}
|
||||
|
||||
$TARGETNAME configure -event reset-init {
|
||||
#complete pll initialization
|
||||
mww 0xb8050000 0x800f0080 ;# set sw_update bit
|
||||
mww 0xb8050008 0 ;# clear reset_switch bit
|
||||
mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass
|
||||
mww 0xb8050008 1 ;# set clock_switch bit
|
||||
sleep 1 ;# wait for lock
|
||||
|
||||
# Setup DDR config and flash mapping
|
||||
mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0)
|
||||
mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8)
|
||||
|
||||
mww 0xb8000010 8 ;# force precharge all banks
|
||||
mww 0xb8000010 1 ;# force EMRS update cycle
|
||||
mww 0xb800000c 0 ;# clr ext. mode register
|
||||
mww 0xb8000010 2 ;# force auto refresh all banks
|
||||
mww 0xb8000010 8 ;# force precharge all banks
|
||||
mww 0xb8000008 0x31 ;# set DDR mode value CAS=3
|
||||
mww 0xb8000010 1 ;# force EMRS update cycle
|
||||
mww 0xb8000014 0x461b ;# DDR refresh value
|
||||
mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff)
|
||||
mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7)
|
||||
mww 0xb8000020 0
|
||||
mww 0xb8000024 0
|
||||
mww 0xb8000028 0
|
||||
}
|
||||
|
||||
# setup working area somewhere in RAM
|
||||
$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
|
||||
|
||||
# serial SPI capable flash
|
||||
# flash bank <driver> <base> <size> <chip_width> <bus_width>
|
||||
|
||||
16
debuggers/openocd/tcl/target/at32ap7000.cfg
Normal file
16
debuggers/openocd/tcl/target/at32ap7000.cfg
Normal file
@ -0,0 +1,16 @@
|
||||
# Atmel AT32AP7000
|
||||
#
|
||||
# This is the only core in the now-inactive high end AVR32 product line,
|
||||
# with MMU, Java Acceleration, and "pixel coprocessor". The AP7 line
|
||||
# is for "Application Processors" (AP) with 7-stage pipelines.
|
||||
#
|
||||
# Most current AVR32 parts are in the UC3 flash based microcontroller (UC)
|
||||
# product line with 3-stage pipelines and without those extras.
|
||||
#
|
||||
# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces
|
||||
# through their JTAG interfaces.
|
||||
|
||||
jtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f
|
||||
|
||||
# REVISIT declare an avr32 target ... needs OpenOCD infrastructure
|
||||
# for both Nexus (generic) and AVR32 (Atmel-specific).
|
||||
29
debuggers/openocd/tcl/target/at91r40008.cfg
Normal file
29
debuggers/openocd/tcl/target/at91r40008.cfg
Normal file
@ -0,0 +1,29 @@
|
||||
# AT91R40008 target configuration file
|
||||
|
||||
# TRST is tied to SRST on the AT91X40 family.
|
||||
reset_config srst_only srst_pulls_trst
|
||||
|
||||
|
||||
if {[info exists CHIPNAME]} {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME at91r40008
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# Setup the JTAG scan chain.
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x1f0f0f0f
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
|
||||
$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
|
||||
47
debuggers/openocd/tcl/target/at91rm9200.cfg
Normal file
47
debuggers/openocd/tcl/target/at91rm9200.cfg
Normal file
@ -0,0 +1,47 @@
|
||||
# Atmel AT91rm9200
|
||||
# http://atmel.com/products/at91/
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME at91rm9200
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x05b0203f
|
||||
}
|
||||
|
||||
# Never allow the following!
|
||||
if { $_CPUTAPID == 0x15b0203f } {
|
||||
echo "-------------------------------------------------------"
|
||||
echo "- ERROR: -"
|
||||
echo "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -"
|
||||
echo "- ERROR: The chip/board has a JTAG select pin/jumper -"
|
||||
echo "- ERROR: -"
|
||||
echo "- ERROR: In one position (0x05b0203f) it selects the -"
|
||||
echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
|
||||
echo "- ERROR: it selects boundry-scan not the ARM -"
|
||||
echo "- ERROR: -"
|
||||
echo "-------------------------------------------------------"
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# Create the GDB Target.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# AT91RM9200 has a 16K block of sram @ 0x0020.0000
|
||||
$_TARGETNAME configure -work-area-phys 0x00200000 \
|
||||
-work-area-size 0x4000 -work-area-backup 1
|
||||
|
||||
# This chip has a DCC ... use it
|
||||
arm7_9 dcc_downloads enable
|
||||
72
debuggers/openocd/tcl/target/at91sam3XXX.cfg
Normal file
72
debuggers/openocd/tcl/target/at91sam3XXX.cfg
Normal file
@ -0,0 +1,72 @@
|
||||
# script for ATMEL sam3, a CORTEX-M3 chip
|
||||
#
|
||||
# at91sam3u4e
|
||||
# at91sam3u2e
|
||||
# at91sam3u1e
|
||||
# at91sam3u4c
|
||||
# at91sam3u2c
|
||||
# at91sam3u1c
|
||||
#
|
||||
# at91sam3s4c
|
||||
# at91sam3s4b
|
||||
# at91sam3s4a
|
||||
# at91sam3s2c
|
||||
# at91sam3s2b
|
||||
# at91sam3s2a
|
||||
# at91sam3s1c
|
||||
# at91sam3s1b
|
||||
# at91sam3s1a
|
||||
#
|
||||
# at91sam3A4C
|
||||
# at91sam3A8C
|
||||
# at91sam3X4C
|
||||
# at91sam3X4E
|
||||
# at91sam3X8C
|
||||
# at91sam3X8E
|
||||
# at91sam3X8H
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME sam3
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
|
||||
#
|
||||
# Since we may be running of an RC oscilator, we crank down the speed a
|
||||
# bit more to be on the safe side. Perhaps superstition, but if are
|
||||
# running off a crystal, we can run closer to the limit. Note
|
||||
# that there can be a pretty wide band where things are more or less stable.
|
||||
|
||||
adapter_khz 500
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# 16K is plenty, the smallest chip has this much
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
halt
|
||||
}
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
9
debuggers/openocd/tcl/target/at91sam3ax_4x.cfg
Normal file
9
debuggers/openocd/tcl/target/at91sam3ax_4x.cfg
Normal file
@ -0,0 +1,9 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3ax_xx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash0
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
# This is a 256K chip - it has the 2nd bank
|
||||
set _FLASHNAME $_CHIPNAME.flash1
|
||||
flash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME
|
||||
11
debuggers/openocd/tcl/target/at91sam3ax_8x.cfg
Normal file
11
debuggers/openocd/tcl/target/at91sam3ax_8x.cfg
Normal file
@ -0,0 +1,11 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3ax_xx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash0
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
# This is a 512K chip - it has the 2nd bank
|
||||
set _FLASHNAME $_CHIPNAME.flash1
|
||||
flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
11
debuggers/openocd/tcl/target/at91sam3ax_xx.cfg
Normal file
11
debuggers/openocd/tcl/target/at91sam3ax_xx.cfg
Normal file
@ -0,0 +1,11 @@
|
||||
# script for ATMEL sam3, a CORTEX-M3 chip
|
||||
#
|
||||
# at91sam3A4C
|
||||
# at91sam3A8C
|
||||
# at91sam3X4C
|
||||
# at91sam3X4E
|
||||
# at91sam3X8C
|
||||
# at91sam3X8E
|
||||
# at91sam3X8H
|
||||
source [find target/at91sam3XXX.cfg]
|
||||
|
||||
29
debuggers/openocd/tcl/target/at91sam3nXX.cfg
Normal file
29
debuggers/openocd/tcl/target/at91sam3nXX.cfg
Normal file
@ -0,0 +1,29 @@
|
||||
|
||||
#
|
||||
# Configuration for Atmel's SAM3N series
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME at91sam3n
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
|
||||
16
debuggers/openocd/tcl/target/at91sam3sXX.cfg
Normal file
16
debuggers/openocd/tcl/target/at91sam3sXX.cfg
Normal file
@ -0,0 +1,16 @@
|
||||
# script for ATMEL sam3, a CORTEX-M3 chip
|
||||
#
|
||||
# at91sam3s4c
|
||||
# at91sam3s4b
|
||||
# at91sam3s4a
|
||||
# at91sam3s2c
|
||||
# at91sam3s2b
|
||||
# at91sam3s2a
|
||||
# at91sam3s1c
|
||||
# at91sam3s1b
|
||||
# at91sam3s1a
|
||||
|
||||
source [find target/at91sam3XXX.cfg]
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME
|
||||
8
debuggers/openocd/tcl/target/at91sam3u1c.cfg
Normal file
8
debuggers/openocd/tcl/target/at91sam3u1c.cfg
Normal file
@ -0,0 +1,8 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3uxx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
8
debuggers/openocd/tcl/target/at91sam3u1e.cfg
Normal file
8
debuggers/openocd/tcl/target/at91sam3u1e.cfg
Normal file
@ -0,0 +1,8 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3uxx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
8
debuggers/openocd/tcl/target/at91sam3u2c.cfg
Normal file
8
debuggers/openocd/tcl/target/at91sam3u2c.cfg
Normal file
@ -0,0 +1,8 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3uxx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
8
debuggers/openocd/tcl/target/at91sam3u2e.cfg
Normal file
8
debuggers/openocd/tcl/target/at91sam3u2e.cfg
Normal file
@ -0,0 +1,8 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3uxx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
11
debuggers/openocd/tcl/target/at91sam3u4c.cfg
Normal file
11
debuggers/openocd/tcl/target/at91sam3u4c.cfg
Normal file
@ -0,0 +1,11 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3uxx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash0
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
# This is a 256K chip, it has the 2nd bank
|
||||
set _FLASHNAME $_CHIPNAME.flash1
|
||||
flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
11
debuggers/openocd/tcl/target/at91sam3u4e.cfg
Normal file
11
debuggers/openocd/tcl/target/at91sam3u4e.cfg
Normal file
@ -0,0 +1,11 @@
|
||||
# common stuff
|
||||
source [find target/at91sam3uxx.cfg]
|
||||
|
||||
# size is automatically "calculated" by probing
|
||||
set _FLASHNAME $_CHIPNAME.flash0
|
||||
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
|
||||
# This is a 256K chip - it has the 2nd bank
|
||||
set _FLASHNAME $_CHIPNAME.flash1
|
||||
flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
|
||||
|
||||
|
||||
11
debuggers/openocd/tcl/target/at91sam3uxx.cfg
Normal file
11
debuggers/openocd/tcl/target/at91sam3uxx.cfg
Normal file
@ -0,0 +1,11 @@
|
||||
# script for ATMEL sam3, a CORTEX-M3 chip
|
||||
#
|
||||
# at91sam3u4e
|
||||
# at91sam3u2e
|
||||
# at91sam3u1e
|
||||
# at91sam3u4c
|
||||
# at91sam3u2c
|
||||
# at91sam3u1c
|
||||
|
||||
source [find target/at91sam3XXX.cfg]
|
||||
|
||||
49
debuggers/openocd/tcl/target/at91sam4XXX.cfg
Normal file
49
debuggers/openocd/tcl/target/at91sam4XXX.cfg
Normal file
@ -0,0 +1,49 @@
|
||||
# script for ATMEL sam4, a CORTEX-M4 chip
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME sam4
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
|
||||
#
|
||||
# Since we may be running of an RC oscilator, we crank down the speed a
|
||||
# bit more to be on the safe side. Perhaps superstition, but if are
|
||||
# running off a crystal, we can run closer to the limit. Note
|
||||
# that there can be a pretty wide band where things are more or less stable.
|
||||
|
||||
adapter_khz 500
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# 16K is plenty, the smallest chip has this much
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
halt
|
||||
}
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
8
debuggers/openocd/tcl/target/at91sam4sXX.cfg
Normal file
8
debuggers/openocd/tcl/target/at91sam4sXX.cfg
Normal file
@ -0,0 +1,8 @@
|
||||
# script for ATMEL sam4, a CORTEX-M4 chip
|
||||
#
|
||||
|
||||
|
||||
source [find target/at91sam4XXX.cfg]
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
|
||||
10
debuggers/openocd/tcl/target/at91sam4sd32x.cfg
Normal file
10
debuggers/openocd/tcl/target/at91sam4sd32x.cfg
Normal file
@ -0,0 +1,10 @@
|
||||
# script for ATMEL sam4sd32, a CORTEX-M4 chip
|
||||
#
|
||||
|
||||
|
||||
source [find target/at91sam4XXX.cfg]
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash0
|
||||
flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
|
||||
set _FLASHNAME $_CHIPNAME.flash1
|
||||
flash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME
|
||||
39
debuggers/openocd/tcl/target/at91sam7se512.cfg
Normal file
39
debuggers/openocd/tcl/target/at91sam7se512.cfg
Normal file
@ -0,0 +1,39 @@
|
||||
# ATMEL sam7se512
|
||||
# Example: the "Elektor Internet Radio" - EIR
|
||||
# http://www.ethernut.de/en/hardware/eir/index.html
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME sam7se512
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
# Force an error until we get a good number.
|
||||
set _CPUTAPID 0xffffffff
|
||||
}
|
||||
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
reset_config srst_only srst_pulls_trst
|
||||
|
||||
#jtag scan chain
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# The target
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
|
||||
|
||||
53
debuggers/openocd/tcl/target/at91sam7sx.cfg
Normal file
53
debuggers/openocd/tcl/target/at91sam7sx.cfg
Normal file
@ -0,0 +1,53 @@
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
reset_config srst_only srst_pulls_trst
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME at91sam7s
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x3f0f0f0f
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
soft_reset_halt
|
||||
# RSTC_CR : Reset peripherals
|
||||
mww 0xfffffd00 0xa5000004
|
||||
# disable watchdog
|
||||
mww 0xfffffd44 0x00008000
|
||||
# enable user reset
|
||||
mww 0xfffffd08 0xa5000001
|
||||
# CKGR_MOR : enable the main oscillator
|
||||
mww 0xfffffc20 0x00000601
|
||||
sleep 10
|
||||
# CKGR_PLLR: 96.1097 MHz
|
||||
mww 0xfffffc2c 0x00481c0e
|
||||
sleep 10
|
||||
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
|
||||
mww 0xfffffc30 0x00000007
|
||||
sleep 10
|
||||
# MC_FMR: flash mode (FWS=1,FMCN=73)
|
||||
mww 0xffffff60 0x00490100
|
||||
sleep 100
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
|
||||
50
debuggers/openocd/tcl/target/at91sam7x256.cfg
Normal file
50
debuggers/openocd/tcl/target/at91sam7x256.cfg
Normal file
@ -0,0 +1,50 @@
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
reset_config srst_only srst_pulls_trst
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME sam7x256
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x3f0f0f0f
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# disable watchdog
|
||||
mww 0xfffffd44 0x00008000
|
||||
# enable user reset
|
||||
mww 0xfffffd08 0xa5000001
|
||||
# CKGR_MOR : enable the main oscillator
|
||||
mww 0xfffffc20 0x00000601
|
||||
sleep 10
|
||||
# CKGR_PLLR: 96.1097 MHz
|
||||
mww 0xfffffc2c 0x00481c0e
|
||||
sleep 10
|
||||
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
|
||||
mww 0xfffffc30 0x00000007
|
||||
sleep 10
|
||||
# MC_FMR: flash mode (FWS=1,FMCN=60)
|
||||
mww 0xffffff60 0x003c0100
|
||||
sleep 100
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
|
||||
51
debuggers/openocd/tcl/target/at91sam7x512.cfg
Normal file
51
debuggers/openocd/tcl/target/at91sam7x512.cfg
Normal file
@ -0,0 +1,51 @@
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
reset_config srst_only srst_pulls_trst
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME sam7x512
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x3f0f0f0f
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# disable watchdog
|
||||
mww 0xfffffd44 0x00008000
|
||||
# enable user reset
|
||||
mww 0xfffffd08 0xa5000001
|
||||
# CKGR_MOR : enable the main oscillator
|
||||
mww 0xfffffc20 0x00000601
|
||||
sleep 10
|
||||
# CKGR_PLLR: 96.1097 MHz
|
||||
mww 0xfffffc2c 0x00481c0e
|
||||
sleep 10
|
||||
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
|
||||
mww 0xfffffc30 0x00000007
|
||||
sleep 10
|
||||
# MC_FMR: flash mode (FWS=1,FMCN=60)
|
||||
mww 0xffffff60 0x003c0100
|
||||
sleep 100
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
|
||||
flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432
|
||||
37
debuggers/openocd/tcl/target/at91sam9.cfg
Normal file
37
debuggers/openocd/tcl/target/at91sam9.cfg
Normal file
@ -0,0 +1,37 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9
|
||||
######################################
|
||||
|
||||
if { [info exists AT91_CHIPNAME] } {
|
||||
set _CHIPNAME $AT91_CHIPNAME
|
||||
} else {
|
||||
error "you must specify a chip name"
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x0792603f
|
||||
}
|
||||
|
||||
reset_config trst_and_srst separate trst_push_pull srst_open_drain
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
adapter_nsrst_delay 300
|
||||
jtag_ntrst_delay 200
|
||||
|
||||
jtag_rclk 3
|
||||
|
||||
######################
|
||||
# Target configuration
|
||||
######################
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
|
||||
19
debuggers/openocd/tcl/target/at91sam9260.cfg
Normal file
19
debuggers/openocd/tcl/target/at91sam9260.cfg
Normal file
@ -0,0 +1,19 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9260
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9260
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
|
||||
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
|
||||
# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
|
||||
# Both areas are 4 kB long.
|
||||
|
||||
#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
|
||||
@ -0,0 +1,89 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9260
|
||||
######################################
|
||||
|
||||
source [find target/at91sam9261.cfg]
|
||||
|
||||
reset_config trst_and_srst
|
||||
|
||||
jtag_rclk 4
|
||||
|
||||
adapter_nsrst_delay 200
|
||||
jtag_ntrst_delay 200
|
||||
|
||||
scan_chain
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# at reset chip runs at 32khz
|
||||
jtag_rclk 8
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init {at91sam_init}
|
||||
|
||||
# Flash configuration
|
||||
#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
|
||||
|
||||
# Faster memory downloads. This is disabled automatically during
|
||||
# reset init since all reset init sequences are too short for
|
||||
# fast memory access
|
||||
arm7_9 dcc_downloads enable
|
||||
arm7_9 fast_memory_access enable
|
||||
|
||||
proc at91sam_init { } {
|
||||
mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
|
||||
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
|
||||
|
||||
mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
|
||||
sleep 20 ;# wait 20 ms
|
||||
mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
|
||||
sleep 10 ;# wait 10 ms
|
||||
mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
|
||||
sleep 20 ;# wait 20 ms
|
||||
mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
|
||||
sleep 10 ;# wait 10 ms
|
||||
mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
|
||||
sleep 10 ;# wait 10 ms
|
||||
|
||||
# Now run at anything fast... ie: 10mhz!
|
||||
jtag_rclk 10000 ;# Increase JTAG Speed to 6 MHz
|
||||
|
||||
mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
|
||||
mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
|
||||
mww 0xffffec08 0x00160016 ;# SMC_CYCLE0
|
||||
mww 0xffffec0c 0x00161003 ;# SMC_MODE0
|
||||
|
||||
mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
|
||||
mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
|
||||
|
||||
mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
|
||||
|
||||
mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
|
||||
#mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
|
||||
|
||||
mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us
|
||||
}
|
||||
14
debuggers/openocd/tcl/target/at91sam9261.cfg
Normal file
14
debuggers/openocd/tcl/target/at91sam9261.cfg
Normal file
@ -0,0 +1,14 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9261
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9261
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
# Internal sram1 memory
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1
|
||||
20
debuggers/openocd/tcl/target/at91sam9263.cfg
Normal file
20
debuggers/openocd/tcl/target/at91sam9263.cfg
Normal file
@ -0,0 +1,20 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9263
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9263
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
|
||||
# AT91SAM9263 has two SRAM areas,
|
||||
# one starting at 0x00300000 of 80KiB
|
||||
# and the other starting at 0x00500000 of 16KiB.
|
||||
|
||||
# Internal sram1 memory
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1
|
||||
#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1
|
||||
16
debuggers/openocd/tcl/target/at91sam9g10.cfg
Normal file
16
debuggers/openocd/tcl/target/at91sam9g10.cfg
Normal file
@ -0,0 +1,16 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9G10
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9g10
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
|
||||
# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
|
||||
22
debuggers/openocd/tcl/target/at91sam9g20.cfg
Normal file
22
debuggers/openocd/tcl/target/at91sam9g20.cfg
Normal file
@ -0,0 +1,22 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9G20
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9g20
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
|
||||
|
||||
jtag_rclk 5
|
||||
|
||||
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
|
||||
# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
|
||||
# Both areas are 16 kB long.
|
||||
|
||||
#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
|
||||
16
debuggers/openocd/tcl/target/at91sam9g45.cfg
Normal file
16
debuggers/openocd/tcl/target/at91sam9g45.cfg
Normal file
@ -0,0 +1,16 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9G45
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9g45
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
|
||||
# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB.
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1
|
||||
14
debuggers/openocd/tcl/target/at91sam9rl.cfg
Normal file
14
debuggers/openocd/tcl/target/at91sam9rl.cfg
Normal file
@ -0,0 +1,14 @@
|
||||
######################################
|
||||
# Target: Atmel AT91SAM9RL
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set AT91_CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set AT91_CHIPNAME at91sam9rl
|
||||
}
|
||||
|
||||
source [find target/at91sam9.cfg]
|
||||
|
||||
# Internal sram1 memory
|
||||
$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1
|
||||
40
debuggers/openocd/tcl/target/atmega128.cfg
Normal file
40
debuggers/openocd/tcl/target/atmega128.cfg
Normal file
@ -0,0 +1,40 @@
|
||||
# for avr
|
||||
|
||||
set _CHIPNAME avr
|
||||
set _ENDIAN little
|
||||
|
||||
# jtag speed
|
||||
adapter_khz 4500
|
||||
|
||||
reset_config srst_only
|
||||
adapter_nsrst_delay 100
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x8970203F
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
|
||||
|
||||
#to use it, script will be like:
|
||||
#init
|
||||
#adapter_khz 4500
|
||||
#reset init
|
||||
#verify_ircapture disable
|
||||
#
|
||||
#halt
|
||||
#wait halt
|
||||
#poll
|
||||
#avr mass_erase 0
|
||||
#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
|
||||
#reset run
|
||||
#shutdown
|
||||
17
debuggers/openocd/tcl/target/avr32.cfg
Normal file
17
debuggers/openocd/tcl/target/avr32.cfg
Normal file
@ -0,0 +1,17 @@
|
||||
set _CHIPNAME avr32
|
||||
set _ENDIAN big
|
||||
|
||||
set _CPUTAPID 0x21e8203f
|
||||
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
reset_config trst_and_srst separate
|
||||
|
||||
# jtag scan chain
|
||||
# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
|
||||
target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
42
debuggers/openocd/tcl/target/c100.cfg
Normal file
42
debuggers/openocd/tcl/target/c100.cfg
Normal file
@ -0,0 +1,42 @@
|
||||
# c100 config.
|
||||
# This is ARM1136 dual core
|
||||
# this script only configures one core (that is used to run Linux)
|
||||
|
||||
# assume no PLL lock, start slowly
|
||||
adapter_khz 100
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME c100
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x27b3645b
|
||||
}
|
||||
|
||||
if { [info exists DSPTAPID] } {
|
||||
set _DSPTAPID $DSPTAPID
|
||||
} else {
|
||||
set _DSPTAPID 0x27b3645b
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID
|
||||
|
||||
|
||||
# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# C100's ARAM 64k SRAM
|
||||
$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
|
||||
412
debuggers/openocd/tcl/target/c100config.tcl
Normal file
412
debuggers/openocd/tcl/target/c100config.tcl
Normal file
@ -0,0 +1,412 @@
|
||||
|
||||
# board(-config) specfic parameters file.
|
||||
|
||||
# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
|
||||
proc config {label} {
|
||||
return [dict get [configC100] $label ]
|
||||
}
|
||||
|
||||
# show the value for the param. with label
|
||||
proc showconfig {label} {
|
||||
echo [format "0x%x" [dict get [configC100] $label ]]
|
||||
}
|
||||
|
||||
# Telo board config
|
||||
# when there are more then one board config
|
||||
# use soft links to c100board-config.tcl
|
||||
# so that only the right board-config gets
|
||||
# included (just like include/configs/board-configs.h
|
||||
# in u-boot.
|
||||
proc configC100 {} {
|
||||
# xtal freq. 24MHz
|
||||
dict set configC100 CFG_REFCLKFREQ 24000000
|
||||
|
||||
# Amba Clk 165MHz
|
||||
dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000
|
||||
dict set configC100 w_amba 1
|
||||
dict set configC100 x_amba 1
|
||||
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
|
||||
dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
|
||||
|
||||
# Arm Clk 450MHz, must be a multiple of 25 MHz
|
||||
dict set configC100 CFG_ARM_CLOCK 450000000
|
||||
dict set configC100 w_arm 0
|
||||
dict set configC100 x_arm 1
|
||||
# y = arm_clk * (w+1)*(x+1)*2/xtal_clk
|
||||
dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
|
||||
|
||||
|
||||
}
|
||||
|
||||
# This should be called for reset init event handler
|
||||
proc setupTelo {} {
|
||||
|
||||
# setup GPIO used as control signals for C100
|
||||
setupGPIO
|
||||
# This will allow acces to lower 8MB or NOR
|
||||
lowGPIO5
|
||||
# setup NOR size,timing,etc.
|
||||
setupNOR
|
||||
# setup internals + PLL + DDR2
|
||||
initC100
|
||||
}
|
||||
|
||||
|
||||
proc setupNOR {} {
|
||||
echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
|
||||
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
|
||||
set EX_CSEN_REG [regs EX_CSEN_REG ]
|
||||
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
|
||||
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
|
||||
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
|
||||
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
|
||||
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
|
||||
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
|
||||
set EX_MFSM_REG [regs EX_MFSM_REG ]
|
||||
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
|
||||
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
|
||||
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
|
||||
|
||||
# enable Expansion Bus Clock + CS0 (NOR)
|
||||
mww $EX_CSEN_REG 0x3
|
||||
# set the address space for CS0=16MB
|
||||
mww $EX_CS0_SEG_REG 0x7ff
|
||||
# set the CS0 bus width to 16-bit
|
||||
mww $EX_CS0_CFG_REG 0x202
|
||||
# set timings to NOR
|
||||
mww $EX_CS0_TMG1_REG 0x03034006
|
||||
mww $EX_CS0_TMG2_REG 0x04040002
|
||||
#mww $EX_CS0_TMG3_REG
|
||||
# set EBUS clock 165/5=33MHz
|
||||
mww $EX_CLOCK_DIV_REG 0x5
|
||||
# everthing else is OK with default
|
||||
}
|
||||
|
||||
proc bootNOR {} {
|
||||
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
|
||||
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
|
||||
set DDR_RST [regs DDR_RST]
|
||||
|
||||
# put DDR controller in reset (so that it comes reset in u-boot)
|
||||
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
|
||||
# setup CS0 controller for NOR
|
||||
setupNOR
|
||||
# make sure we are accessing the lower part of NOR
|
||||
lowGPIO5
|
||||
# set PC to start of NOR (at boot 0x20000000 = 0x0)
|
||||
reg pc $EXP_CS0_BASEADDR
|
||||
# run
|
||||
resume
|
||||
}
|
||||
proc setupGPIO {} {
|
||||
echo "Setting up GPIO block for Telo"
|
||||
# This is current setup for Telo (see sch. for details):
|
||||
#GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
|
||||
#GPIO1 irq line for FXS-FXO
|
||||
#GPIO5 addr22 for NOR flash (access to upper 8MB)
|
||||
#GPIO17 reset for DECT module.
|
||||
#GPIO29 CS_n for NAND
|
||||
|
||||
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
|
||||
set GPIO_OE_REG [regs GPIO_OE_REG]
|
||||
|
||||
# set GPIO29=GPIO17=1, GPIO5=0
|
||||
mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
|
||||
# enable [as output] GPIO29,GPIO17,GPIO5
|
||||
mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5]
|
||||
}
|
||||
|
||||
proc highGPIO5 {} {
|
||||
echo "GPIO5 high"
|
||||
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
|
||||
# set GPIO5=1
|
||||
mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
|
||||
}
|
||||
|
||||
proc lowGPIO5 {} {
|
||||
echo "GPIO5 low"
|
||||
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
|
||||
# set GPIO5=0
|
||||
mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
|
||||
}
|
||||
|
||||
proc boardID {id} {
|
||||
# so far built:
|
||||
# 4'b1111
|
||||
dict set boardID 15 name "EVT1"
|
||||
dict set boardID 15 ddr2size 128M
|
||||
# dict set boardID 15 nandsize 1G
|
||||
# dict set boardID 15 norsize 16M
|
||||
# 4'b0000
|
||||
dict set boardID 0 name "EVT2"
|
||||
dict set boardID 0 ddr2size 128M
|
||||
# 4'b0001
|
||||
dict set boardID 1 name "EVT3"
|
||||
dict set boardID 1 ddr2size 256M
|
||||
# 4'b1110
|
||||
dict set boardID 14 name "EVT3_old"
|
||||
dict set boardID 14 ddr2size 128M
|
||||
# 4'b0010
|
||||
dict set boardID 2 name "EVT4"
|
||||
dict set boardID 2 ddr2size 256M
|
||||
|
||||
return $boardID
|
||||
}
|
||||
|
||||
|
||||
# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
|
||||
# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
|
||||
proc ooma_board_detect {} {
|
||||
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
|
||||
|
||||
# read the current value of the BOOTSRAP pins
|
||||
set tmp [mrw $GPIO_BOOTSTRAP_REG]
|
||||
echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
|
||||
# extract the GPBP bits
|
||||
set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
|
||||
|
||||
# display board ID
|
||||
echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
|
||||
# show it on serial console
|
||||
putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
|
||||
# return the ddr2 size, used to configure DDR2 on a given board.
|
||||
return [dict get [boardID $gpbt] $gpbt ddr2size]
|
||||
}
|
||||
|
||||
proc configureDDR2regs_256M {} {
|
||||
|
||||
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
|
||||
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
|
||||
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
|
||||
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
|
||||
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
|
||||
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
|
||||
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
|
||||
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
|
||||
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
|
||||
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
|
||||
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
|
||||
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
|
||||
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
|
||||
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
|
||||
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
|
||||
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
|
||||
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
|
||||
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
|
||||
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
|
||||
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
|
||||
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
|
||||
|
||||
set DENALI_CTL_02_VAL 0x0100000000010100
|
||||
set DENALI_CTL_11_VAL 0x433a32164a560a00
|
||||
|
||||
mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
|
||||
# 01_DATA mod [40]=1, enable BA2
|
||||
mw64bit $DENALI_CTL_01_DATA 0x0100010100000001
|
||||
mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
|
||||
mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
|
||||
mw64bit $DENALI_CTL_04_DATA 0x0000010100000001
|
||||
mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
|
||||
mw64bit $DENALI_CTL_06_DATA 0x060a020200020202
|
||||
mw64bit $DENALI_CTL_07_DATA 0x0000000300000206
|
||||
mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209
|
||||
mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a
|
||||
mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18
|
||||
# 11_DATA mod [39-32]=16,more refresh
|
||||
mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
|
||||
mw64bit $DENALI_CTL_12_DATA 0x0000000000000800
|
||||
mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
|
||||
mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
|
||||
mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000
|
||||
mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000
|
||||
mw64bit $DENALI_CTL_17_DATA 0x0000000000000000
|
||||
mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
|
||||
mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600
|
||||
mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8
|
||||
|
||||
set wr_dqs_shift 0x40
|
||||
# start DDRC
|
||||
mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
|
||||
# wait int_status[2] (DRAM init complete)
|
||||
echo -n "Waiting for DDR2 controller to init..."
|
||||
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
|
||||
while { [expr $tmp & 0x040000] == 0 } {
|
||||
sleep 1
|
||||
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
|
||||
}
|
||||
echo "done."
|
||||
|
||||
# do ddr2 training sequence
|
||||
# TBD (for now, if you need it, run trainDDR command)
|
||||
}
|
||||
|
||||
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
|
||||
# The values are computed based on Mindspeed and Nanya datasheets
|
||||
proc configureDDR2regs_128M {} {
|
||||
|
||||
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
|
||||
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
|
||||
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
|
||||
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
|
||||
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
|
||||
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
|
||||
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
|
||||
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
|
||||
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
|
||||
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
|
||||
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
|
||||
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
|
||||
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
|
||||
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
|
||||
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
|
||||
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
|
||||
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
|
||||
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
|
||||
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
|
||||
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
|
||||
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
|
||||
|
||||
|
||||
set DENALI_CTL_02_VAL 0x0100010000010100
|
||||
set DENALI_CTL_11_VAL 0x433A42124A650A37
|
||||
# set some default values
|
||||
mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
|
||||
mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
|
||||
mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
|
||||
mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
|
||||
mw64bit $DENALI_CTL_04_DATA 0x0201010100000201
|
||||
mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
|
||||
mw64bit $DENALI_CTL_06_DATA 0x050A020200020202
|
||||
mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205
|
||||
mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209
|
||||
mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00
|
||||
mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A
|
||||
mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
|
||||
mw64bit $DENALI_CTL_12_DATA 0x0000080000000800
|
||||
mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
|
||||
mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
|
||||
mw64bit $DENALI_CTL_15_DATA 0x0508000000000000
|
||||
mw64bit $DENALI_CTL_16_DATA 0x000020472D200000
|
||||
mw64bit $DENALI_CTL_17_DATA 0x0000000008000000
|
||||
mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
|
||||
mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604
|
||||
mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8
|
||||
|
||||
set wr_dqs_shift 0x40
|
||||
# start DDRC
|
||||
mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
|
||||
# wait int_status[2] (DRAM init complete)
|
||||
echo -n "Waiting for DDR2 controller to init..."
|
||||
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
|
||||
while { [expr $tmp & 0x040000] == 0 } {
|
||||
sleep 1
|
||||
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
|
||||
}
|
||||
# This is not necessary
|
||||
#mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
|
||||
echo "done."
|
||||
|
||||
# do ddr2 training sequence
|
||||
# TBD (for now, if you need it, run trainDDR command)
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc setupUART0 {} {
|
||||
# configure UART0 to 115200, 8N1
|
||||
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
|
||||
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
|
||||
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
|
||||
set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
|
||||
set UART0_LCR [regs UART0_LCR]
|
||||
set LCR_DLAB [regs LCR_DLAB]
|
||||
set UART0_DLL [regs UART0_DLL]
|
||||
set UART0_DLH [regs UART0_DLH]
|
||||
set UART0_IIR [regs UART0_IIR]
|
||||
set UART0_IER [regs UART0_IER]
|
||||
set LCR_ONE_STOP [regs LCR_ONE_STOP]
|
||||
set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
|
||||
set FCR_XMITRES [regs FCR_XMITRES]
|
||||
set FCR_RCVRRES [regs FCR_RCVRRES]
|
||||
set FCR_FIFOEN [regs FCR_FIFOEN]
|
||||
set IER_UUE [regs IER_UUE]
|
||||
|
||||
# unlock writing to IOCTRL register
|
||||
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
|
||||
# enable UART0
|
||||
mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
|
||||
# baudrate 115200
|
||||
# This should really be amba_clk/(16*115200) but amba_clk=165MHz
|
||||
set tmp 89
|
||||
# Enable Divisor Latch access
|
||||
mmw $UART0_LCR $LCR_DLAB 0x0
|
||||
# set the divisor to $tmp
|
||||
mww $UART0_DLL [expr $tmp & 0xff]
|
||||
mww $UART0_DLH [expr $tmp >> 8]
|
||||
# Disable Divisor Latch access
|
||||
mmw $UART0_LCR 0x0 $LCR_DLAB
|
||||
# set the UART to 8N1
|
||||
mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
|
||||
# reset FIFO
|
||||
mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
|
||||
# enable FFUART
|
||||
mww $UART0_IER $IER_UUE
|
||||
}
|
||||
|
||||
proc putcUART0 {char} {
|
||||
|
||||
set UART0_LSR [regs UART0_LSR]
|
||||
set UART0_THR [regs UART0_THR]
|
||||
set LSR_TEMT [regs LSR_TEMT]
|
||||
|
||||
# convert the 'char' to digit
|
||||
set tmp [ scan $char %c ]
|
||||
# /* wait for room in the tx FIFO on FFUART */
|
||||
while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
|
||||
mww $UART0_THR $tmp
|
||||
if { $char == "\n" } { putcUART0 \r }
|
||||
}
|
||||
|
||||
proc putsUART0 {str} {
|
||||
set index 0
|
||||
set len [string length $str]
|
||||
while { $index < $len } {
|
||||
putcUART0 [string index $str $index]
|
||||
set index [expr $index + 1]
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
proc trainDDR2 {} {
|
||||
set ARAM_BASEADDR [regs ARAM_BASEADDR]
|
||||
|
||||
# you must have run 'reset init' or u-boot
|
||||
# load the training code to ARAM
|
||||
load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
|
||||
# set PC to start of NOR (at boot 0x20000000 = 0x0)
|
||||
reg pc $ARAM_BASEADDR
|
||||
# run
|
||||
resume
|
||||
}
|
||||
|
||||
proc flashUBOOT {file} {
|
||||
# this will update uboot on NOR partition
|
||||
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
|
||||
|
||||
# setup CS0 controller for NOR
|
||||
setupNOR
|
||||
# make sure we are accessing the lower part of NOR
|
||||
lowGPIO5
|
||||
flash probe 0
|
||||
echo "Erasing sectors 0-3 for uboot"
|
||||
putsUART0 "Erasing sectors 0-3 for uboot\n"
|
||||
flash erase_sector 0 0 3
|
||||
echo "Programming u-boot"
|
||||
putsUART0 "Programming u-boot..."
|
||||
arm11 memwrite burst enable
|
||||
flash write_image $file $EXP_CS0_BASEADDR
|
||||
arm11 memwrite burst disable
|
||||
putsUART0 "done.\n"
|
||||
putsUART0 "Rebooting, please wait!\n"
|
||||
reboot
|
||||
}
|
||||
506
debuggers/openocd/tcl/target/c100helper.tcl
Normal file
506
debuggers/openocd/tcl/target/c100helper.tcl
Normal file
@ -0,0 +1,506 @@
|
||||
|
||||
proc helpC100 {} {
|
||||
echo "List of useful functions for C100 processor:"
|
||||
echo "1) reset init: will set up your Telo board"
|
||||
echo "2) setupNOR: will setup NOR access"
|
||||
echo "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
|
||||
echo "4) setupGPIO: will setup GPIOs for Telo board"
|
||||
echo "5) showGPIO: will show current GPIO config registers"
|
||||
echo "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
|
||||
echo "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
|
||||
echo "8) showAmbaClk: will show current config registers for Amba Bus Clock"
|
||||
echo "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
|
||||
echo "10) showArmClk: will show current config registers for Arm Bus Clock"
|
||||
echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
|
||||
echo "12) ooma_board_detect: will show which version of Telo you have"
|
||||
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
|
||||
echo "14) showDDR2: will show DDR2 config registers"
|
||||
echo "15) showWatchdog: will show current regster config for watchdog"
|
||||
echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
|
||||
echo "17) bootNOR: will boot Telo from NOR"
|
||||
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
|
||||
echo "19) putcUART0: will print a character on UART0"
|
||||
echo "20) putsUART0: will print a string on UART0"
|
||||
echo "21) trainDDR2: will run DDR2 training program"
|
||||
echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
|
||||
}
|
||||
|
||||
source [find mem_helper.tcl]
|
||||
|
||||
# read a 64-bit register (memory mapped)
|
||||
proc mr64bit {reg} {
|
||||
set value ""
|
||||
mem2array value 32 $reg 2
|
||||
return $value
|
||||
}
|
||||
|
||||
|
||||
# write a 64-bit register (memory mapped)
|
||||
proc mw64bit {reg value} {
|
||||
set high [expr $value >> 32]
|
||||
set low [expr $value & 0xffffffff]
|
||||
#echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
|
||||
mww $reg $low
|
||||
mww [expr $reg+4] $high
|
||||
}
|
||||
|
||||
|
||||
proc showNOR {} {
|
||||
echo "This is the current NOR setup"
|
||||
set EX_CSEN_REG [regs EX_CSEN_REG ]
|
||||
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
|
||||
set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
|
||||
set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
|
||||
set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
|
||||
set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
|
||||
set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
|
||||
set EX_MFSM_REG [regs EX_MFSM_REG ]
|
||||
set EX_CSFSM_REG [regs EX_CSFSM_REG ]
|
||||
set EX_WRFSM_REG [regs EX_WRFSM_REG ]
|
||||
set EX_RDFSM_REG [regs EX_RDFSM_REG ]
|
||||
|
||||
echo [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
|
||||
echo [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
|
||||
echo [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
|
||||
echo [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
|
||||
echo [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
|
||||
echo [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
|
||||
echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
|
||||
echo [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
|
||||
echo [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
|
||||
echo [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
|
||||
echo [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc showGPIO {} {
|
||||
echo "This is the current GPIO register setup"
|
||||
# GPIO outputs register
|
||||
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
|
||||
# GPIO Output Enable register
|
||||
set GPIO_OE_REG [regs GPIO_OE_REG]
|
||||
set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
|
||||
set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
|
||||
# GPIO input register
|
||||
set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
|
||||
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
|
||||
set MUX_CONF_REG [regs MUX_CONF_REG]
|
||||
set SYSCONF_REG [regs SYSCONF_REG]
|
||||
set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
|
||||
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
|
||||
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
|
||||
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
|
||||
set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
|
||||
|
||||
echo [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
|
||||
echo [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
|
||||
echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
|
||||
echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
|
||||
echo [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
|
||||
echo [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
|
||||
echo [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
|
||||
echo [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
|
||||
echo [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
|
||||
echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
|
||||
echo [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
|
||||
echo [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
|
||||
echo [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
|
||||
}
|
||||
|
||||
|
||||
|
||||
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
|
||||
proc showAmbaClk {} {
|
||||
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
|
||||
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
|
||||
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
|
||||
|
||||
echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
|
||||
mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
|
||||
# see if the PLL is in bypass mode
|
||||
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
|
||||
echo [format "PLL bypass bit: %d" $bypass]
|
||||
if {$bypass == 1} {
|
||||
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
|
||||
} else {
|
||||
# nope, extract x,y,w and compute the PLL output freq.
|
||||
set x [expr ($value(0) & 0x0001F0000) >> 16]
|
||||
echo [format "x: %d" $x]
|
||||
set y [expr ($value(0) & 0x00000007F)]
|
||||
echo [format "y: %d" $y]
|
||||
set w [expr ($value(0) & 0x000000300) >> 8]
|
||||
echo [format "w: %d" $w]
|
||||
echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
|
||||
# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
|
||||
proc setupAmbaClk {} {
|
||||
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
|
||||
set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
|
||||
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
|
||||
set ARM_AHB_BYP [regs ARM_AHB_BYP]
|
||||
set PLL_DISABLE [regs PLL_DISABLE]
|
||||
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
|
||||
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
|
||||
set DIV_BYPASS [regs DIV_BYPASS]
|
||||
set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
|
||||
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
|
||||
set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
|
||||
set w [config w_amba]
|
||||
set x [config x_amba]
|
||||
set y [config y_amba]
|
||||
|
||||
echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
|
||||
#echo [format "setupAmbaClk: w= %d" $w]
|
||||
#echo [format "setupAmbaClk: x= %d" $x]
|
||||
#echo [format "setupAmbaClk: y= %d" $y]
|
||||
# set PLL into BYPASS mode using MUX
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
|
||||
# do an internal PLL bypass
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
|
||||
# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
|
||||
# openocd smallest resolution is 1ms so, wait 1ms
|
||||
sleep 1
|
||||
# disable the PLL
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
|
||||
# wait 1ms
|
||||
sleep 1
|
||||
# enable the PLL
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
|
||||
sleep 1
|
||||
# set X, W and X
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
|
||||
# wait for PLL to lock
|
||||
echo "Wating for Amba PLL to lock"
|
||||
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
|
||||
# remove the internal PLL bypass
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
|
||||
# remove PLL from BYPASS mode using MUX
|
||||
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
|
||||
}
|
||||
|
||||
|
||||
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
|
||||
proc showArmClk {} {
|
||||
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
|
||||
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
|
||||
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
|
||||
|
||||
echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
|
||||
mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
|
||||
# see if the PLL is in bypass mode
|
||||
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
|
||||
echo [format "PLL bypass bit: %d" $bypass]
|
||||
if {$bypass == 1} {
|
||||
echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
|
||||
} else {
|
||||
# nope, extract x,y,w and compute the PLL output freq.
|
||||
set x [expr ($value(0) & 0x0001F0000) >> 16]
|
||||
echo [format "x: %d" $x]
|
||||
set y [expr ($value(0) & 0x00000007F)]
|
||||
echo [format "y: %d" $y]
|
||||
set w [expr ($value(0) & 0x000000300) >> 8]
|
||||
echo [format "w: %d" $w]
|
||||
echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
|
||||
}
|
||||
}
|
||||
|
||||
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
|
||||
# Arm Clock is used by two ARM1136 cores
|
||||
proc setupArmClk {} {
|
||||
set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
|
||||
set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
|
||||
set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
|
||||
set ARM_AHB_BYP [regs ARM_AHB_BYP]
|
||||
set PLL_DISABLE [regs PLL_DISABLE]
|
||||
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
|
||||
set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
|
||||
set DIV_BYPASS [regs DIV_BYPASS]
|
||||
set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
|
||||
set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
|
||||
set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
|
||||
set w [config w_arm]
|
||||
set x [config x_arm]
|
||||
set y [config y_arm]
|
||||
|
||||
echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
|
||||
#echo [format "setupArmClk: w= %d" $w]
|
||||
#echo [format "setupArmaClk: x= %d" $x]
|
||||
#echo [format "setupArmaClk: y= %d" $y]
|
||||
# set PLL into BYPASS mode using MUX
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
|
||||
# do an internal PLL bypass
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
|
||||
# wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
|
||||
# openocd smallest resolution is 1ms so, wait 1ms
|
||||
sleep 1
|
||||
# disable the PLL
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
|
||||
# wait 1ms
|
||||
sleep 1
|
||||
# enable the PLL
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
|
||||
sleep 1
|
||||
# set X, W and X
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
|
||||
# wait for PLL to lock
|
||||
echo "Wating for Amba PLL to lock"
|
||||
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
|
||||
# remove the internal PLL bypass
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
|
||||
# remove PLL from BYPASS mode using MUX
|
||||
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc setupPLL {} {
|
||||
echo "PLLs setup"
|
||||
setupAmbaClk
|
||||
setupArmClk
|
||||
}
|
||||
|
||||
# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
|
||||
proc setupDDR2 {} {
|
||||
echo "Configuring DDR2"
|
||||
|
||||
set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
|
||||
set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
|
||||
set MEMORY_CR [regs MEMORY_CR]
|
||||
set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
|
||||
set DDR_RST [regs DDR_RST]
|
||||
|
||||
# put DDR controller in reset (so that it is reset and correctly configured)
|
||||
# this is only necessary if DDR was previously confiured
|
||||
# and not reset.
|
||||
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
|
||||
|
||||
set M [expr 1024 * 1024]
|
||||
set DDR_SZ_1024M [expr 1024 * $M]
|
||||
set DDR_SZ_256M [expr 256 * $M]
|
||||
set DDR_SZ_128M [expr 128 * $M]
|
||||
set DDR_SZ_64M [expr 64 * $M]
|
||||
# ooma_board_detect returns DDR2 memory size
|
||||
set tmp [ooma_board_detect]
|
||||
if {$tmp == "128M"} {
|
||||
echo "DDR2 size 128MB"
|
||||
set ddr_size $DDR_SZ_128M
|
||||
} elseif {$tmp == "256M"} {
|
||||
echo "DDR2 size 256MB"
|
||||
set ddr_size $DDR_SZ_256M
|
||||
} else {
|
||||
echo "Don't know how to handle this DDR2 size?"
|
||||
}
|
||||
|
||||
# Memory setup register
|
||||
mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
|
||||
# disbale ROM remap
|
||||
mww $MEMORY_CR 0x0
|
||||
# Take DDR controller out of reset
|
||||
mmw $BLOCK_RESET_REG $DDR_RST 0x0
|
||||
# min. 20 ops delay
|
||||
sleep 1
|
||||
|
||||
# This will setup Denali DDR2 controller
|
||||
if {$tmp == "128M"} {
|
||||
configureDDR2regs_128M
|
||||
} elseif {$tmp == "256M"} {
|
||||
configureDDR2regs_256M
|
||||
} else {
|
||||
echo "Don't know how to configure DDR2 setup?"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc showDDR2 {} {
|
||||
|
||||
set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
|
||||
set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
|
||||
set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
|
||||
set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
|
||||
set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
|
||||
set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
|
||||
set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
|
||||
set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
|
||||
set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
|
||||
set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
|
||||
set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
|
||||
set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
|
||||
set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
|
||||
set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
|
||||
set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
|
||||
set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
|
||||
set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
|
||||
set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
|
||||
set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
|
||||
set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
|
||||
set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
|
||||
|
||||
set tmp [mr64bit $DENALI_CTL_00_DATA]
|
||||
echo [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_01_DATA]
|
||||
echo [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_02_DATA]
|
||||
echo [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_03_DATA]
|
||||
echo [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_04_DATA]
|
||||
echo [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_05_DATA]
|
||||
echo [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_06_DATA]
|
||||
echo [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_07_DATA]
|
||||
echo [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_08_DATA]
|
||||
echo [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_09_DATA]
|
||||
echo [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_10_DATA]
|
||||
echo [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_11_DATA]
|
||||
echo [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_12_DATA]
|
||||
echo [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_13_DATA]
|
||||
echo [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_14_DATA]
|
||||
echo [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_15_DATA]
|
||||
echo [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_16_DATA]
|
||||
echo [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_17_DATA]
|
||||
echo [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_18_DATA]
|
||||
echo [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_19_DATA]
|
||||
echo [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
|
||||
set tmp [mr64bit $DENALI_CTL_20_DATA]
|
||||
echo [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
|
||||
|
||||
}
|
||||
|
||||
proc initC100 {} {
|
||||
# this follows u-boot/cpu/arm1136/start.S
|
||||
set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
|
||||
set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
|
||||
set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
|
||||
set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
|
||||
set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
|
||||
set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
|
||||
set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
|
||||
set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
|
||||
set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
|
||||
set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
|
||||
set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
|
||||
set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
|
||||
set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
|
||||
set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
|
||||
set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
|
||||
|
||||
|
||||
# unlock writing to IOCTRL register
|
||||
mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
|
||||
# enable address lines A15-A21
|
||||
mmw $GPIO_IOCTRL_REG 0xf 0x0
|
||||
# set ARM into supervisor mode (SVC32)
|
||||
# disable IRQ, FIQ
|
||||
# Do I need this in JTAG mode?
|
||||
# it really should be done as 'and ~0x1f | 0xd3 but
|
||||
# openocd does not support this yet
|
||||
reg cpsr 0xd3
|
||||
# /*
|
||||
# * flush v4 I/D caches
|
||||
# */
|
||||
# mov r0, #0
|
||||
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
||||
arm mcr 15 0 7 7 0 0x0
|
||||
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
||||
arm mcr 15 0 8 7 0 0x0
|
||||
|
||||
# /*
|
||||
# * disable MMU stuff and caches
|
||||
# */
|
||||
# mrc p15, 0, r0, c1, c0, 0
|
||||
arm mrc 15 0 1 0 0
|
||||
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
||||
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
||||
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
||||
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||
# orr r0, r0, #0x00400000 @ set bit 22 (U)
|
||||
# mcr p15, 0, r0, c1, c0, 0
|
||||
arm mcr 15 0 1 0 0 0x401002
|
||||
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
|
||||
# APB init
|
||||
# // Setting APB Bus Wait states to 1, set post write
|
||||
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
|
||||
mww [expr $APB_ACCESS_WS_REG] 0x40
|
||||
# AHB init
|
||||
# // enable all 6 masters for ARAM
|
||||
mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
|
||||
# // enable all 6 masters for EBUS
|
||||
mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
|
||||
|
||||
# ARAM init
|
||||
# // disable pipeline mode in ARAM
|
||||
# I don't think this is documented anywhere?
|
||||
mww $INTC_ARM1_CONTROL_REG 0x1
|
||||
# configure clocks
|
||||
setupPLL
|
||||
# setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
|
||||
setupUART0
|
||||
# enable cache
|
||||
# ? (u-boot does nothing here)
|
||||
# DDR2 memory init
|
||||
setupDDR2
|
||||
putsUART0 "C100 initialization complete.\n"
|
||||
echo "C100 initialization complete."
|
||||
}
|
||||
|
||||
# show current state of watchdog timer
|
||||
proc showWatchdog {} {
|
||||
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
|
||||
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
|
||||
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
|
||||
|
||||
echo [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
|
||||
echo [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
|
||||
echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
|
||||
}
|
||||
|
||||
# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
|
||||
# this will trigger watchdog reset
|
||||
# the sw. reset does not work on C100
|
||||
# watchdog reset effectively works as hw. reset
|
||||
proc reboot {} {
|
||||
set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
|
||||
set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
|
||||
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
|
||||
|
||||
# allow the counter to count to high value before triggering
|
||||
# this is because regsiter writes are slow over JTAG and
|
||||
# I don't want to miss the high_bound==curr_count condition
|
||||
mww $TIMER_WDT_HIGH_BOUND 0xffffff
|
||||
mww $TIMER_WDT_CURRENT_COUNT 0x0
|
||||
echo "JTAG speed lowered to 100kHz"
|
||||
adapter_khz 100
|
||||
mww $TIMER_WDT_CONTROL 0x1
|
||||
# wait until the reset
|
||||
echo -n "Wating for watchdog to trigger..."
|
||||
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
|
||||
# echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
|
||||
# sleep 1
|
||||
#
|
||||
#}
|
||||
while {[c100.cpu curstate] != "running"} { sleep 1}
|
||||
echo "done."
|
||||
echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
|
||||
}
|
||||
493
debuggers/openocd/tcl/target/c100regs.tcl
Normal file
493
debuggers/openocd/tcl/target/c100regs.tcl
Normal file
@ -0,0 +1,493 @@
|
||||
# Note that I basically converted
|
||||
# u-boot/include/asm-arm/arch/comcerto_100.h
|
||||
# defines
|
||||
|
||||
# this is a work-around for 'global' not working under Linux
|
||||
# access registers by calling this routine.
|
||||
# For example:
|
||||
# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
|
||||
proc regs {reg} {
|
||||
return [dict get [regsC100] $reg ]
|
||||
}
|
||||
|
||||
proc showreg {reg} {
|
||||
echo [format "0x%x" [dict get [regsC100] $reg ]]
|
||||
}
|
||||
|
||||
proc regsC100 {} {
|
||||
#/* memcore */
|
||||
#/* device memory base addresses */
|
||||
#// device memory sizes
|
||||
#/* ARAM SIZE=64K */
|
||||
dict set regsC100 ARAM_SIZE 0x00010000
|
||||
dict set regsC100 ARAM_BASEADDR 0x0A000000
|
||||
|
||||
#/* Hardware Interface Units */
|
||||
dict set regsC100 APB_BASEADDR 0x10000000
|
||||
#/* APB_SIZE=16M address range */
|
||||
dict set regsC100 APB_SIZE 0x01000000
|
||||
|
||||
dict set regsC100 EXP_CS0_BASEADDR 0x20000000
|
||||
dict set regsC100 EXP_CS1_BASEADDR 0x24000000
|
||||
dict set regsC100 EXP_CS2_BASEADDR 0x28000000
|
||||
dict set regsC100 EXP_CS3_BASEADDR 0x2C000000
|
||||
dict set regsC100 EXP_CS4_BASEADDR 0x30000000
|
||||
|
||||
dict set regsC100 DDR_BASEADDR 0x80000000
|
||||
|
||||
dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000]
|
||||
dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000]
|
||||
dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000]
|
||||
dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000]
|
||||
dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000]
|
||||
dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000]
|
||||
dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000]
|
||||
dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000]
|
||||
dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000]
|
||||
dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000]
|
||||
dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000]
|
||||
dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000]
|
||||
dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000]
|
||||
dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
|
||||
dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
|
||||
dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000]
|
||||
dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000]
|
||||
dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000]
|
||||
dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000]
|
||||
dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000]
|
||||
dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000]
|
||||
dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000]
|
||||
dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000]
|
||||
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// AHB block //
|
||||
#////////////////////////////////////////////////////////////
|
||||
dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00]
|
||||
dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04]
|
||||
dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08]
|
||||
dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C]
|
||||
|
||||
dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00]
|
||||
dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04]
|
||||
dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08]
|
||||
dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C]
|
||||
|
||||
dict set regsC100 IDMA_MASTER 0
|
||||
dict set regsC100 TDMA_MASTER 1
|
||||
dict set regsC100 USBIPSEC_MASTER 2
|
||||
dict set regsC100 ARM0_MASTER 3
|
||||
dict set regsC100 ARM1_MASTER 4
|
||||
dict set regsC100 MDMA_MASTER 5
|
||||
|
||||
#define IDMA_PRIORITY(level) (level)
|
||||
#define TDM_PRIORITY(level) (level << 4)
|
||||
#define USBIPSEC_PRIORITY(level) (level << 8)
|
||||
#define ARM0_PRIORITY(level) (level << 12)
|
||||
#define ARM1_PRIORITY(level) (level << 16)
|
||||
#define MDMA_PRIORITY(level) (level << 20)
|
||||
|
||||
dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18]
|
||||
dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19]
|
||||
dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20]
|
||||
dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21]
|
||||
dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22]
|
||||
dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23]
|
||||
|
||||
dict set regsC100 MEMORY_BASE_ADDR 0x80000000
|
||||
dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10]
|
||||
dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14]
|
||||
dict set regsC100 ROM_REMAP_EN 0x1
|
||||
|
||||
#define HAL_asb_priority(level) \
|
||||
#*(volatile unsigned *)ASA_PRI_REG = level
|
||||
|
||||
#define HAL_aram_priority(level) \
|
||||
#*(volatile unsigned *)ASA_ARAM_PRI_REG = level
|
||||
|
||||
#define HAL_aram_arbitration(arbitration_mask) \
|
||||
#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
|
||||
|
||||
#define HAL_aram_defmaster(mask) \
|
||||
#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// INTC block //
|
||||
#////////////////////////////////////////////////////////////
|
||||
|
||||
dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18]
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// TIMER block //
|
||||
#////////////////////////////////////////////////////////////
|
||||
|
||||
dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00]
|
||||
dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04]
|
||||
dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08]
|
||||
dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C]
|
||||
|
||||
dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18]
|
||||
dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10]
|
||||
dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14]
|
||||
dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C]
|
||||
|
||||
dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20]
|
||||
dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24]
|
||||
dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28]
|
||||
dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C]
|
||||
|
||||
dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40]
|
||||
dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
|
||||
dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
|
||||
dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0]
|
||||
dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4]
|
||||
dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8]
|
||||
|
||||
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// EBUS block
|
||||
#////////////////////////////////////////////////////////////
|
||||
|
||||
dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00]
|
||||
dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04]
|
||||
dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08]
|
||||
dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C]
|
||||
dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10]
|
||||
dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14]
|
||||
dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18]
|
||||
dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C]
|
||||
dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20]
|
||||
dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24]
|
||||
dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28]
|
||||
dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C]
|
||||
dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30]
|
||||
dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34]
|
||||
dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38]
|
||||
dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C]
|
||||
dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40]
|
||||
dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44]
|
||||
dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48]
|
||||
dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C]
|
||||
dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50]
|
||||
dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54]
|
||||
dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58]
|
||||
dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C]
|
||||
dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60]
|
||||
dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64]
|
||||
dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68]
|
||||
dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C]
|
||||
|
||||
dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
|
||||
dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
|
||||
dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104]
|
||||
dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108]
|
||||
dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C]
|
||||
|
||||
|
||||
dict set regsC100 EX_CLK_EN 0x00000001
|
||||
dict set regsC100 EX_CSBOOT_EN 0x00000002
|
||||
dict set regsC100 EX_CS0_EN 0x00000002
|
||||
dict set regsC100 EX_CS1_EN 0x00000004
|
||||
dict set regsC100 EX_CS2_EN 0x00000008
|
||||
dict set regsC100 EX_CS3_EN 0x00000010
|
||||
dict set regsC100 EX_CS4_EN 0x00000020
|
||||
|
||||
dict set regsC100 EX_MEM_BUS_8 0x00000000
|
||||
dict set regsC100 EX_MEM_BUS_16 0x00000002
|
||||
dict set regsC100 EX_MEM_BUS_32 0x00000004
|
||||
dict set regsC100 EX_CS_HIGH 0x00000008
|
||||
dict set regsC100 EX_WE_HIGH 0x00000010
|
||||
dict set regsC100 EX_RE_HIGH 0x00000020
|
||||
dict set regsC100 EX_ALE_MODE 0x00000040
|
||||
dict set regsC100 EX_STRB_MODE 0x00000080
|
||||
dict set regsC100 EX_DM_MODE 0x00000100
|
||||
dict set regsC100 EX_NAND_MODE 0x00000200
|
||||
dict set regsC100 EX_RDY_EN 0x00000400
|
||||
dict set regsC100 EX_RDY_EDGE 0x00000800
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// GPIO block
|
||||
#////////////////////////////////////////////////////////////
|
||||
|
||||
# GPIO outputs register
|
||||
dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00]
|
||||
# GPIO Output Enable register
|
||||
dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04]
|
||||
dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08]
|
||||
dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C]
|
||||
# GPIO input register
|
||||
dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10]
|
||||
dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14]
|
||||
dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18]
|
||||
dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C]
|
||||
dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30]
|
||||
dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40]
|
||||
dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38]
|
||||
dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44]
|
||||
dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50]
|
||||
|
||||
dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001
|
||||
dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002
|
||||
dict set regsC100 GPIO_IOCTRL_A19A21 0x00000004
|
||||
dict set regsC100 GPIO_IOCTRL_TMREVT0 0x00000008
|
||||
dict set regsC100 GPIO_IOCTRL_TMREVT1 0x00000010
|
||||
dict set regsC100 GPIO_IOCTRL_GPBT3 0x00000020
|
||||
dict set regsC100 GPIO_IOCTRL_I2C 0x00000040
|
||||
dict set regsC100 GPIO_IOCTRL_UART0 0x00000080
|
||||
dict set regsC100 GPIO_IOCTRL_UART1 0x00000100
|
||||
dict set regsC100 GPIO_IOCTRL_SPI 0x00000200
|
||||
dict set regsC100 GPIO_IOCTRL_HBMODE 0x00000400
|
||||
|
||||
dict set regsC100 GPIO_IOCTRL_VAL 0x55555555
|
||||
|
||||
dict set regsC100 GPIO_0 0x01
|
||||
dict set regsC100 GPIO_1 0x02
|
||||
dict set regsC100 GPIO_2 0x04
|
||||
dict set regsC100 GPIO_3 0x08
|
||||
dict set regsC100 GPIO_4 0x10
|
||||
dict set regsC100 GPIO_5 0x20
|
||||
dict set regsC100 GPIO_6 0x40
|
||||
dict set regsC100 GPIO_7 0x80
|
||||
|
||||
dict set regsC100 GPIO_RISING_EDGE 1
|
||||
dict set regsC100 GPIO_FALLING_EDGE 2
|
||||
dict set regsC100 GPIO_BOTH_EDGES 3
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// UART
|
||||
#////////////////////////////////////////////////////////////
|
||||
|
||||
dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
|
||||
dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
|
||||
dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
|
||||
dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
|
||||
dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
|
||||
dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
|
||||
dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
|
||||
dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C]
|
||||
dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10]
|
||||
dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14]
|
||||
dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18]
|
||||
dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C]
|
||||
|
||||
dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
|
||||
dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
|
||||
dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
|
||||
dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
|
||||
dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
|
||||
dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
|
||||
dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
|
||||
dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C]
|
||||
dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10]
|
||||
dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14]
|
||||
dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18]
|
||||
dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C]
|
||||
|
||||
# /* default */
|
||||
dict set regsC100 LCR_CHAR_LEN_5 0x00
|
||||
dict set regsC100 LCR_CHAR_LEN_6 0x01
|
||||
dict set regsC100 LCR_CHAR_LEN_7 0x02
|
||||
dict set regsC100 LCR_CHAR_LEN_8 0x03
|
||||
#/* One stop bit! - default */
|
||||
dict set regsC100 LCR_ONE_STOP 0x00
|
||||
#/* Two stop bit! */
|
||||
dict set regsC100 LCR_TWO_STOP 0x04
|
||||
#/* Parity Enable */
|
||||
dict set regsC100 LCR_PEN 0x08
|
||||
dict set regsC100 LCR_PARITY_NONE 0x00
|
||||
#/* Even Parity Select */
|
||||
dict set regsC100 LCR_EPS 0x10
|
||||
#/* Enable Parity Stuff */
|
||||
dict set regsC100 LCR_PS 0x20
|
||||
#/* Start Break */
|
||||
dict set regsC100 LCR_SBRK 0x40
|
||||
#/* Parity Stuff Bit */
|
||||
dict set regsC100 LCR_PSB 0x80
|
||||
#/* UART 16550 Divisor Latch Assess */
|
||||
dict set regsC100 LCR_DLAB 0x80
|
||||
|
||||
#/* FIFO Error Status */
|
||||
dict set regsC100 LSR_FIFOE [expr 1 << 7]
|
||||
#/* Transmitter Empty */
|
||||
dict set regsC100 LSR_TEMT [expr 1 << 6]
|
||||
#/* Transmit Data Request */
|
||||
dict set regsC100 LSR_TDRQ [expr 1 << 5]
|
||||
#/* Break Interrupt */
|
||||
dict set regsC100 LSR_BI [expr 1 << 4]
|
||||
#/* Framing Error */
|
||||
dict set regsC100 LSR_FE [expr 1 << 3]
|
||||
#/* Parity Error */
|
||||
dict set regsC100 LSR_PE [expr 1 << 2]
|
||||
#/* Overrun Error */
|
||||
dict set regsC100 LSR_OE [expr 1 << 1]
|
||||
#/* Data Ready */
|
||||
dict set regsC100 LSR_DR [expr 1 << 0]
|
||||
|
||||
#/* DMA Requests Enable */
|
||||
dict set regsC100 IER_DMAE [expr 1 << 7]
|
||||
#/* UART Unit Enable */
|
||||
dict set regsC100 IER_UUE [expr 1 << 6]
|
||||
#/* NRZ coding Enable */
|
||||
dict set regsC100 IER_NRZE [expr 1 << 5]
|
||||
#/* Receiver Time Out Interrupt Enable */
|
||||
dict set regsC100 IER_RTIOE [expr 1 << 4]
|
||||
#/* Modem Interrupt Enable */
|
||||
dict set regsC100 IER_MIE [expr 1 << 3]
|
||||
#/* Receiver Line Status Interrupt Enable */
|
||||
dict set regsC100 IER_RLSE [expr 1 << 2]
|
||||
#/* Transmit Data request Interrupt Enable */
|
||||
dict set regsC100 IER_TIE [expr 1 << 1]
|
||||
#/* Receiver Data Available Interrupt Enable */
|
||||
dict set regsC100 IER_RAVIE [expr 1 << 0]
|
||||
|
||||
#/* FIFO Mode Enable Status */
|
||||
dict set regsC100 IIR_FIFOES1 [expr 1 << 7]
|
||||
#/* FIFO Mode Enable Status */
|
||||
dict set regsC100 IIR_FIFOES0 [expr 1 << 6]
|
||||
#/* Time Out Detected */
|
||||
dict set regsC100 IIR_TOD [expr 1 << 3]
|
||||
#/* Interrupt Source Encoded */
|
||||
dict set regsC100 IIR_IID2 [expr 1 << 2]
|
||||
#/* Interrupt Source Encoded */
|
||||
dict set regsC100 IIR_IID1 [expr 1 << 1]
|
||||
#/* Interrupt Pending (active low) */
|
||||
dict set regsC100 IIR_IP [expr 1 << 0]
|
||||
|
||||
#/* UART 16550 FIFO Control Register */
|
||||
dict set regsC100 FCR_FIFOEN 0x01
|
||||
dict set regsC100 FCR_RCVRRES 0x02
|
||||
dict set regsC100 FCR_XMITRES 0x04
|
||||
|
||||
#/* Interrupt Enable Register */
|
||||
#// UART 16550
|
||||
#// Enable Received Data Available Interrupt
|
||||
dict set regsC100 IER_RXTH 0x01
|
||||
#// Enable Transmitter Empty Interrupt
|
||||
dict set regsC100 IER_TXTH 0x02
|
||||
|
||||
|
||||
|
||||
#////////////////////////////////////////////////////////////
|
||||
#// CLK + RESET block
|
||||
#////////////////////////////////////////////////////////////
|
||||
|
||||
dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00]
|
||||
dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04]
|
||||
dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08]
|
||||
dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C]
|
||||
dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10]
|
||||
dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14]
|
||||
dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18]
|
||||
dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C]
|
||||
dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20]
|
||||
dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24]
|
||||
dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40]
|
||||
|
||||
dict set regsC100 ARM_PLL_BY_CTRL 0x80000000
|
||||
dict set regsC100 ARM_AHB_BYP 0x04000000
|
||||
dict set regsC100 PLL_DISABLE 0x02000000
|
||||
dict set regsC100 PLL_CLK_BYPASS 0x01000000
|
||||
|
||||
dict set regsC100 AHB_PLL_BY_CTRL 0x80000000
|
||||
dict set regsC100 DIV_BYPASS 0x40000000
|
||||
dict set regsC100 SYNC_MODE 0x20000000
|
||||
|
||||
dict set regsC100 EPHY_CLKDIV_BYPASS 0x00200000
|
||||
dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT 16
|
||||
dict set regsC100 PUI_CLKDIV_BYPASS 0x00004000
|
||||
dict set regsC100 PUI_CLKDIV_SRCCLK 0x00002000
|
||||
dict set regsC100 PUI_CLKDIV_RATIO_SHIFT 8
|
||||
dict set regsC100 PCI_CLKDIV_BYPASS 0x00000020
|
||||
dict set regsC100 PCI_CLKDIV_RATIO_SHIFT 0
|
||||
|
||||
dict set regsC100 ARM0_CLK_PD 0x00200000
|
||||
dict set regsC100 ARM1_CLK_PD 0x00100000
|
||||
dict set regsC100 EPHY_CLK_PD 0x00080000
|
||||
dict set regsC100 TDM_CLK_PD 0x00040000
|
||||
dict set regsC100 PUI_CLK_PD 0x00020000
|
||||
dict set regsC100 PCI_CLK_PD 0x00010000
|
||||
dict set regsC100 MDMA_AHBCLK_PD 0x00000400
|
||||
dict set regsC100 I2CSPI_AHBCLK_PD 0x00000200
|
||||
dict set regsC100 UART_AHBCLK_PD 0x00000100
|
||||
dict set regsC100 IPSEC_AHBCLK_PD 0x00000080
|
||||
dict set regsC100 TDM_AHBCLK_PD 0x00000040
|
||||
dict set regsC100 USB1_AHBCLK_PD 0x00000020
|
||||
dict set regsC100 USB0_AHBCLK_PD 0x00000010
|
||||
dict set regsC100 GEMAC1_AHBCLK_PD 0x00000008
|
||||
dict set regsC100 GEMAC0_AHBCLK_PD 0x00000004
|
||||
dict set regsC100 PUI_AHBCLK_PD 0x00000002
|
||||
dict set regsC100 HIF_AHBCLK_PD 0x00000001
|
||||
|
||||
dict set regsC100 ARM1_DIV_BP 0x00001000
|
||||
dict set regsC100 ARM1_DIV_VAL_SHIFT 8
|
||||
dict set regsC100 ARM0_DIV_BP 0x00000010
|
||||
dict set regsC100 ARM0_DIV_VAL_SHIFT 0
|
||||
|
||||
dict set regsC100 AHBCLK_PLL_LOCK 0x00000002
|
||||
dict set regsC100 FCLK_PLL_LOCK 0x00000001
|
||||
|
||||
|
||||
#// reset block
|
||||
dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100]
|
||||
dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104]
|
||||
|
||||
dict set regsC100 RNG_RST 0x1000
|
||||
dict set regsC100 IPSEC_RST 0x0800
|
||||
dict set regsC100 DDR_RST 0x0400
|
||||
dict set regsC100 USB1_PHY_RST 0x0200
|
||||
dict set regsC100 USB0_PHY_RST 0x0100
|
||||
dict set regsC100 USB1_RST 0x0080
|
||||
dict set regsC100 USB0_RST 0x0040
|
||||
dict set regsC100 GEMAC1_RST 0x0020
|
||||
dict set regsC100 GEMAC0_RST 0x0010
|
||||
dict set regsC100 TDM_RST 0x0008
|
||||
dict set regsC100 PUI_RST 0x0004
|
||||
dict set regsC100 HIF_RST 0x0002
|
||||
dict set regsC100 PCI_RST 0x0001
|
||||
|
||||
#////////////////////////////////////////////////////////////////
|
||||
#// DDR CONTROLLER block
|
||||
#////////////////////////////////////////////////////////////////
|
||||
|
||||
dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000
|
||||
dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00]
|
||||
dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08]
|
||||
dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10]
|
||||
dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18]
|
||||
dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20]
|
||||
dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28]
|
||||
dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30]
|
||||
dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38]
|
||||
dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40]
|
||||
dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48]
|
||||
dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50]
|
||||
dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58]
|
||||
dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60]
|
||||
dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68]
|
||||
dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70]
|
||||
dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78]
|
||||
dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80]
|
||||
dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88]
|
||||
dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90]
|
||||
dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98]
|
||||
dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0]
|
||||
|
||||
# 32-bit value
|
||||
dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44]
|
||||
# 8-bit
|
||||
dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D]
|
||||
# 8-bit
|
||||
dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A]
|
||||
# 8-bit
|
||||
dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F]
|
||||
# 8-bit
|
||||
dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50]
|
||||
# 8-bit
|
||||
dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51]
|
||||
# 8-bit
|
||||
dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52]
|
||||
|
||||
|
||||
# end of proc regsC100
|
||||
}
|
||||
31
debuggers/openocd/tcl/target/cs351x.cfg
Normal file
31
debuggers/openocd/tcl/target/cs351x.cfg
Normal file
@ -0,0 +1,31 @@
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME cs351x
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x00526fa1
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# Create the GDB Target.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME -variant fa526
|
||||
|
||||
# There is 16K of SRAM on this chip
|
||||
# FIXME: flash programming is not working by using this work area. So comment this out for now.
|
||||
#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
|
||||
|
||||
# This chip has a DCC ... use it
|
||||
arm7_9 dcc_downloads enable
|
||||
|
||||
377
debuggers/openocd/tcl/target/davinci.cfg
Normal file
377
debuggers/openocd/tcl/target/davinci.cfg
Normal file
@ -0,0 +1,377 @@
|
||||
#
|
||||
# Utility code for DaVinci-family chips
|
||||
#
|
||||
|
||||
# davinci_pinmux: assigns PINMUX$reg <== $value
|
||||
proc davinci_pinmux {soc reg value} {
|
||||
mww [expr [dict get $soc sysbase] + 4 * $reg] $value
|
||||
}
|
||||
|
||||
source [find mem_helper.tcl]
|
||||
|
||||
#
|
||||
# pll_setup: initialize PLL
|
||||
# - pll_addr ... physical addr of controller
|
||||
# - mult ... pll multiplier
|
||||
# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
|
||||
#
|
||||
# For PLLs that don't have a given register (e.g. plldiv8), or where a
|
||||
# given divider is non-programmable, caller provides *NO* config mapping.
|
||||
#
|
||||
|
||||
# PLL version 0x02: tested on dm355
|
||||
# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
|
||||
proc pll_v02_setup {pll_addr mult config} {
|
||||
set pll_ctrl_addr [expr $pll_addr + 0x100]
|
||||
set pll_ctrl [mrw $pll_ctrl_addr]
|
||||
|
||||
# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
|
||||
# NOTE: this assumes we should clear that bit
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0100]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 2 - clear PLLENSRC (bit 5)
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0020]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 3 - clear PLLEN (bit 0) ... enter bypass mode
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0001]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 4 - wait at least 4 refclk cycles
|
||||
sleep 1
|
||||
|
||||
# 5 - set PLLRST (bit 3)
|
||||
set pll_ctrl [expr $pll_ctrl | 0x0008]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 6 - set PLLDIS (bit 4)
|
||||
set pll_ctrl [expr $pll_ctrl | 0x0010]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 7 - clear PLLPWRDN (bit 1)
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0002]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 8 - clear PLLDIS (bit 4)
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0010]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 9 - optional: write prediv, postdiv, and pllm
|
||||
# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
|
||||
mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
|
||||
if { [dict exists $config prediv] } {
|
||||
set div [dict get $config prediv]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0114] $div
|
||||
}
|
||||
if { [dict exists $config postdiv] } {
|
||||
set div [dict get $config postdiv]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0128] $div
|
||||
}
|
||||
|
||||
# 10 - optional: set plldiv1, plldiv2, ...
|
||||
# NOTE: this assumes some registers have their just-reset values:
|
||||
# - PLLSTAT.GOSTAT is clear when we enter
|
||||
# - ALNCTL has everything set
|
||||
set go 0
|
||||
if { [dict exists $config div1] } {
|
||||
set div [dict get $config div1]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0118] $div
|
||||
set go 1
|
||||
}
|
||||
if { [dict exists $config div2] } {
|
||||
set div [dict get $config div2]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x011c] $div
|
||||
set go 1
|
||||
}
|
||||
if { [dict exists $config div3] } {
|
||||
set div [dict get $config div3]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0120] $div
|
||||
set go 1
|
||||
}
|
||||
if { [dict exists $config div4] } {
|
||||
set div [dict get $config div4]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0160] $div
|
||||
set go 1
|
||||
}
|
||||
if { [dict exists $config div5] } {
|
||||
set div [dict get $config div5]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0164] $div
|
||||
set go 1
|
||||
}
|
||||
if {$go != 0} {
|
||||
# write pllcmd.GO; poll pllstat.GO
|
||||
mww [expr $pll_addr + 0x0138] 0x01
|
||||
set pllstat [expr $pll_addr + 0x013c]
|
||||
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
|
||||
}
|
||||
mww [expr $pll_addr + 0x0138] 0x00
|
||||
|
||||
# 11 - wait at least 5 usec for reset to finish
|
||||
# (assume covered by overheads including JTAG messaging)
|
||||
|
||||
# 12 - clear PLLRST (bit 3)
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0008]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 13 - wait at least 8000 refclk cycles for PLL to lock
|
||||
# if we assume 24 MHz (slowest osc), that's 1/3 msec
|
||||
sleep 3
|
||||
|
||||
# 14 - set PLLEN (bit 0) ... leave bypass mode
|
||||
set pll_ctrl [expr $pll_ctrl | 0x0001]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
}
|
||||
|
||||
# PLL version 0x03: tested on dm365
|
||||
proc pll_v03_setup {pll_addr mult config} {
|
||||
set pll_ctrl_addr [expr $pll_addr + 0x100]
|
||||
set pll_secctrl_addr [expr $pll_addr + 0x108]
|
||||
set pll_ctrl [mrw $pll_ctrl_addr]
|
||||
|
||||
# 1 - power up the PLL
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0002]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 2 - clear PLLENSRC (bit 5)
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0020]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 2 - clear PLLEN (bit 0) ... enter bypass mode
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0001]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 3 - wait at least 4 refclk cycles
|
||||
sleep 1
|
||||
|
||||
# 4 - set PLLRST (bit 3)
|
||||
set pll_ctrl [expr $pll_ctrl | 0x0008]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 5 - wait at least 5 usec
|
||||
sleep 1
|
||||
|
||||
# 6 - clear PLLRST (bit 3)
|
||||
set pll_ctrl [expr $pll_ctrl & ~0x0008]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
|
||||
# 9 - optional: write prediv, postdiv, and pllm
|
||||
mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
|
||||
if { [dict exists $config prediv] } {
|
||||
set div [dict get $config prediv]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0114] $div
|
||||
}
|
||||
if { [dict exists $config postdiv] } {
|
||||
set div [dict get $config postdiv]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0128] $div
|
||||
}
|
||||
|
||||
# 10 - write start sequence to PLLSECCTL
|
||||
mww $pll_secctrl_addr 0x00470000
|
||||
mww $pll_secctrl_addr 0x00460000
|
||||
mww $pll_secctrl_addr 0x00400000
|
||||
mww $pll_secctrl_addr 0x00410000
|
||||
|
||||
# 11 - optional: set plldiv1, plldiv2, ...
|
||||
# NOTE: this assumes some registers have their just-reset values:
|
||||
# - PLLSTAT.GOSTAT is clear when we enter
|
||||
set aln 0
|
||||
if { [dict exists $config div1] } {
|
||||
set div [dict get $config div1]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0118] $div
|
||||
set aln [expr $aln | 0x1]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0118] 0
|
||||
}
|
||||
if { [dict exists $config div2] } {
|
||||
set div [dict get $config div2]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x011c] $div
|
||||
set aln [expr $aln | 0x2]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x011c] 0
|
||||
}
|
||||
if { [dict exists $config div3] } {
|
||||
set div [dict get $config div3]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0120] $div
|
||||
set aln [expr $aln | 0x4]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0120] 0
|
||||
}
|
||||
if { [dict exists $config oscdiv] } {
|
||||
set div [dict get $config oscdiv]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0124] $div
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0124] 0
|
||||
}
|
||||
if { [dict exists $config div4] } {
|
||||
set div [dict get $config div4]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0160] $div
|
||||
set aln [expr $aln | 0x8]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0160] 0
|
||||
}
|
||||
if { [dict exists $config div5] } {
|
||||
set div [dict get $config div5]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0164] $div
|
||||
set aln [expr $aln | 0x10]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0164] 0
|
||||
}
|
||||
if { [dict exists $config div6] } {
|
||||
set div [dict get $config div6]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0168] $div
|
||||
set aln [expr $aln | 0x20]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0168] 0
|
||||
}
|
||||
if { [dict exists $config div7] } {
|
||||
set div [dict get $config div7]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x016c] $div
|
||||
set aln [expr $aln | 0x40]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x016c] 0
|
||||
}
|
||||
if { [dict exists $config div8] } {
|
||||
set div [dict get $config div8]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0170] $div
|
||||
set aln [expr $aln | 0x80]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0170] 0
|
||||
}
|
||||
if { [dict exists $config div9] } {
|
||||
set div [dict get $config div9]
|
||||
set div [expr 0x8000 | ($div - 1)]
|
||||
mww [expr $pll_addr + 0x0174] $div
|
||||
set aln [expr $aln | 0x100]
|
||||
} else {
|
||||
mww [expr $pll_addr + 0x0174] 0
|
||||
}
|
||||
if {$aln != 0} {
|
||||
# clear pllcmd.GO
|
||||
mww [expr $pll_addr + 0x0138] 0x00
|
||||
# write alingment flags
|
||||
mww [expr $pll_addr + 0x0140] $aln
|
||||
# write pllcmd.GO; poll pllstat.GO
|
||||
mww [expr $pll_addr + 0x0138] 0x01
|
||||
set pllstat [expr $pll_addr + 0x013c]
|
||||
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
|
||||
}
|
||||
mww [expr $pll_addr + 0x0138] 0x00
|
||||
set addr [dict get $config ctladdr]
|
||||
while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 }
|
||||
|
||||
# 12 - set PLLEN (bit 0) ... leave bypass mode
|
||||
set pll_ctrl [expr $pll_ctrl | 0x0001]
|
||||
mww $pll_ctrl_addr $pll_ctrl
|
||||
}
|
||||
|
||||
# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
|
||||
# modules can be enabled.
|
||||
|
||||
# prepare a non-DSP module to be enabled; finish with psc_go
|
||||
proc psc_enable {module} {
|
||||
set psc_addr 0x01c41000
|
||||
# write MDCTL
|
||||
mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
|
||||
}
|
||||
|
||||
# prepare a non-DSP module to be reset; finish with psc_go
|
||||
proc psc_reset {module} {
|
||||
set psc_addr 0x01c41000
|
||||
# write MDCTL
|
||||
mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
|
||||
}
|
||||
|
||||
# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
|
||||
proc psc_go {} {
|
||||
set psc_addr 0x01c41000
|
||||
set ptstat_addr [expr $psc_addr + 0x0128]
|
||||
|
||||
# just in case PTSTAT.go isn't clear
|
||||
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
|
||||
|
||||
# write PTCMD.go ... ignoring any DSP power domain
|
||||
mww [expr $psc_addr + 0x0120] 1
|
||||
|
||||
# wait for PTSTAT.go to clear (again ignoring DSP power domain)
|
||||
while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
|
||||
}
|
||||
|
||||
#
|
||||
# A reset using only SRST is a "Warm Reset", resetting everything in the
|
||||
# chip except ARM emulation (and everything _outside_ the chip that hooks
|
||||
# up to SRST). But many boards don't expose SRST via their JTAG connectors
|
||||
# (it's not present on TI-14 headers).
|
||||
#
|
||||
# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
|
||||
# without any board-wide side effects, since it's triggered using JTAG using
|
||||
# either (a) ARM watchdog timer, or (b) ICEpick.
|
||||
#
|
||||
proc davinci_wdog_reset {} {
|
||||
set timer2_phys 0x01c21c00
|
||||
|
||||
# NOTE -- on entry
|
||||
# - JTAG communication with the ARM *must* be working OK; this
|
||||
# may imply using adaptive clocking or disabling WFI-in-idle
|
||||
# - current target must be the DaVinci ARM
|
||||
# - that ARM core must be halted
|
||||
# - timer2 clock is still enabled (PSC 29 on most chips)
|
||||
|
||||
#
|
||||
# Part I -- run regardless of being halted via JTAG
|
||||
#
|
||||
# NOTE: for now, we assume there's no DSP that could control the
|
||||
# watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
|
||||
# suspend signal is controlled via ARM emulation suspend.
|
||||
#
|
||||
|
||||
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
|
||||
mww phys [expr $timer2_phys + 0x28] 0x00004000
|
||||
|
||||
#
|
||||
# Part II -- in case watchdog hasn't been set up
|
||||
#
|
||||
|
||||
# TCR: disable, force internal clock source
|
||||
mww phys [expr $timer2_phys + 0x20] 0
|
||||
|
||||
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
|
||||
mww phys [expr $timer2_phys + 0x24] 0
|
||||
mww phys [expr $timer2_phys + 0x24] 0x110b
|
||||
|
||||
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
|
||||
# so watchdog triggers ASAP
|
||||
mww phys [expr $timer2_phys + 0x10] 0
|
||||
mww phys [expr $timer2_phys + 0x14] 0
|
||||
mww phys [expr $timer2_phys + 0x18] 0
|
||||
mww phys [expr $timer2_phys + 0x1c] 0
|
||||
|
||||
# WDTCR: put into pre-active state, then active
|
||||
mww phys [expr $timer2_phys + 0x28] 0xa5c64000
|
||||
mww phys [expr $timer2_phys + 0x28] 0xda7e4000
|
||||
|
||||
#
|
||||
# Part III -- it's ready to rumble
|
||||
#
|
||||
|
||||
# WDTCR: write invalid WDKEY to trigger reset
|
||||
mww phys [expr $timer2_phys + 0x28] 0x00004000
|
||||
}
|
||||
31
debuggers/openocd/tcl/target/dragonite.cfg
Normal file
31
debuggers/openocd/tcl/target/dragonite.cfg
Normal file
@ -0,0 +1,31 @@
|
||||
######################################
|
||||
# Target: Marvell Dragonite CPU core
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME dragonite
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x121003d3
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
reset_config trst_and_srst
|
||||
adapter_nsrst_delay 200
|
||||
jtag_ntrst_delay 200
|
||||
|
||||
37
debuggers/openocd/tcl/target/dsp56321.cfg
Normal file
37
debuggers/openocd/tcl/target/dsp56321.cfg
Normal file
@ -0,0 +1,37 @@
|
||||
# Script for freescale DSP56321
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME dsp56321
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
# this defaults to a big endian
|
||||
set _ENDIAN big
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x1181501d
|
||||
}
|
||||
|
||||
#jtag speed
|
||||
adapter_khz 4500
|
||||
|
||||
#has only srst
|
||||
reset_config srst_only
|
||||
|
||||
#jtag scan chain
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID
|
||||
|
||||
#target configuration
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
#working area at base of ram
|
||||
$_TARGETNAME configure -work-area-virt 0
|
||||
76
debuggers/openocd/tcl/target/dsp568013.cfg
Normal file
76
debuggers/openocd/tcl/target/dsp568013.cfg
Normal file
@ -0,0 +1,76 @@
|
||||
# Script for freescale DSP568013
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME dsp568013
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
# this defaults to a big endian
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x01f2401d
|
||||
}
|
||||
|
||||
#jtag speed
|
||||
adapter_khz 800
|
||||
|
||||
reset_config srst_only
|
||||
|
||||
#MASTER tap
|
||||
jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
|
||||
|
||||
#CORE tap
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
|
||||
|
||||
#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# Setup the interesting tap
|
||||
# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
|
||||
jtag configure $_CHIPNAME.chp -event setup "
|
||||
jtag tapenable $_TARGETNAME
|
||||
poll off
|
||||
"
|
||||
|
||||
#select CORE tap by modifying the TLM register.
|
||||
#to be used when MASTER tap is selected.
|
||||
jtag configure $_TARGETNAME -event tap-enable "
|
||||
irscan $_CHIPNAME.chp 0x05;
|
||||
drscan $_CHIPNAME.chp 4 0x02;
|
||||
jtag tapdisable $_CHIPNAME.chp;
|
||||
"
|
||||
|
||||
#select MASTER tap by modifying the TLM register.
|
||||
#to be used when CORE tap is selected.
|
||||
jtag configure $_CHIPNAME.chp -event tap-enable "
|
||||
irscan $_TARGETNAME 0x08;
|
||||
drscan $_TARGETNAME 4 0x1;
|
||||
jtag tapdisable $_TARGETNAME;
|
||||
"
|
||||
|
||||
#disables the master tap
|
||||
jtag configure $_TARGETNAME -event tap-disable "
|
||||
"
|
||||
#TODO FIND SMARTER WAY.
|
||||
|
||||
jtag configure $_CHIPNAME.chp -event tap-disable "
|
||||
"
|
||||
#TODO FIND SMARTER WAY.
|
||||
|
||||
|
||||
#working area at base of ram
|
||||
$_TARGETNAME configure -work-area-virt 0
|
||||
|
||||
#setup flash
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
|
||||
|
||||
72
debuggers/openocd/tcl/target/dsp568037.cfg
Normal file
72
debuggers/openocd/tcl/target/dsp568037.cfg
Normal file
@ -0,0 +1,72 @@
|
||||
# Script for freescale DSP568037
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME dsp568037
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
# this defaults to a big endian
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x01f2801d
|
||||
}
|
||||
|
||||
#jtag speed
|
||||
adapter_khz 800
|
||||
|
||||
reset_config srst_only
|
||||
|
||||
#MASTER tap
|
||||
jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
|
||||
|
||||
#CORE tap
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
|
||||
|
||||
#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# Setup the interesting tap
|
||||
jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
|
||||
|
||||
#select CORE tap by modifying the TLM register.
|
||||
#to be used when MASTER tap is selected.
|
||||
jtag configure $_TARGETNAME -event tap-enable "
|
||||
irscan $_CHIPNAME.chp 0x05;
|
||||
drscan $_CHIPNAME.chp 4 0x02;
|
||||
jtag tapdisable $_CHIPNAME.chp;
|
||||
"
|
||||
|
||||
#select MASTER tap by modifying the TLM register.
|
||||
#to be used when CORE tap is selected.
|
||||
jtag configure $_CHIPNAME.chp -event tap-enable "
|
||||
irscan $_TARGETNAME 0x08;
|
||||
drscan $_TARGETNAME 4 0x1;
|
||||
jtag tapdisable $_TARGETNAME;
|
||||
"
|
||||
|
||||
#disables the master tap
|
||||
jtag configure $_TARGETNAME -event tap-disable "
|
||||
"
|
||||
#TODO FIND SMARTER WAY.
|
||||
|
||||
jtag configure $_CHIPNAME.chp -event tap-disable "
|
||||
"
|
||||
#TODO FIND SMARTER WAY.
|
||||
|
||||
|
||||
#working area at base of ram
|
||||
$_TARGETNAME configure -work-area-virt 0
|
||||
|
||||
#setup flash
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
|
||||
|
||||
38
debuggers/openocd/tcl/target/efm32_stlink.cfg
Normal file
38
debuggers/openocd/tcl/target/efm32_stlink.cfg
Normal file
@ -0,0 +1,38 @@
|
||||
#
|
||||
# efm32 stlink pseudo target
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME efm32
|
||||
}
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# By default use 16kB
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x4000
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x2ba01477
|
||||
}
|
||||
|
||||
# EFM32 MCUs only support SW interface
|
||||
set _TRANSPORT hla_swd
|
||||
|
||||
transport select $_TRANSPORT
|
||||
|
||||
hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
|
||||
32
debuggers/openocd/tcl/target/epc9301.cfg
Normal file
32
debuggers/openocd/tcl/target/epc9301.cfg
Normal file
@ -0,0 +1,32 @@
|
||||
# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ep9301
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
# Force an error until we get a good number.
|
||||
set _CPUTAPID 0xffffffff
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
|
||||
|
||||
#flash configuration
|
||||
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
|
||||
30
debuggers/openocd/tcl/target/faux.cfg
Normal file
30
debuggers/openocd/tcl/target/faux.cfg
Normal file
@ -0,0 +1,30 @@
|
||||
#Script for faux target - used for testing
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME at91eb40a
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x00000000
|
||||
}
|
||||
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
#target configuration
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
|
||||
|
||||
#dummy flash driver
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME
|
||||
31
debuggers/openocd/tcl/target/feroceon.cfg
Normal file
31
debuggers/openocd/tcl/target/feroceon.cfg
Normal file
@ -0,0 +1,31 @@
|
||||
######################################
|
||||
# Target: Marvell Feroceon CPU core
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME feroceon
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x20a023d3
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
reset_config trst_and_srst
|
||||
adapter_nsrst_delay 200
|
||||
jtag_ntrst_delay 200
|
||||
|
||||
47
debuggers/openocd/tcl/target/fm3.cfg
Normal file
47
debuggers/openocd/tcl/target/fm3.cfg
Normal file
@ -0,0 +1,47 @@
|
||||
# MB96F506
|
||||
# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME mb9bf500
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
# delays on reset lines
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
# Fujitsu cortex-M3 reset configuration
|
||||
reset_config trst_only
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# MB9BF506 has 64kB of SRAM on its main system bus
|
||||
$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
|
||||
|
||||
# MB9BF506 has 512kB internal FLASH
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
|
||||
|
||||
# 4MHz / 6 = 666kHz, so use 500
|
||||
adapter_khz 500
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
31
debuggers/openocd/tcl/target/hilscher_netx10.cfg
Normal file
31
debuggers/openocd/tcl/target/hilscher_netx10.cfg
Normal file
@ -0,0 +1,31 @@
|
||||
################################################################################
|
||||
# Author: Michael Trensch (MTrensch@googlemail.com)
|
||||
################################################################################
|
||||
|
||||
#Hilscher netX 10 CPU
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME netx10
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x25966021
|
||||
}
|
||||
|
||||
# jtag scan chain
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# that TAP is associated with a target
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
50
debuggers/openocd/tcl/target/hilscher_netx50.cfg
Normal file
50
debuggers/openocd/tcl/target/hilscher_netx50.cfg
Normal file
@ -0,0 +1,50 @@
|
||||
################################################################################
|
||||
# Author: Michael Trensch (MTrensch@googlemail.com)
|
||||
################################################################################
|
||||
|
||||
#Hilscher netX 50 CPU
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME netx50
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x25966021
|
||||
}
|
||||
|
||||
# jtag scan chain
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# that TAP is associated with a target
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from
|
||||
# DMA controller at init. This function will setup a dummy DMA to free this ares
|
||||
# and must be called before using SDRAM
|
||||
proc sdram_fix { } {
|
||||
|
||||
mww 0x1c005830 0x00000001
|
||||
|
||||
mww 0x1c005104 0xBFFFFFFC
|
||||
mww 0x1c00510c 0x00480001
|
||||
mww 0x1c005110 0x00000001
|
||||
|
||||
sleep 100
|
||||
|
||||
mww 0x1c00510c 0
|
||||
mww 0x1c005110 0
|
||||
mww 0x1c005830 0x00000000
|
||||
|
||||
puts "SDRAM Fix executed!"
|
||||
}
|
||||
47
debuggers/openocd/tcl/target/hilscher_netx500.cfg
Normal file
47
debuggers/openocd/tcl/target/hilscher_netx500.cfg
Normal file
@ -0,0 +1,47 @@
|
||||
#Hilscher netX 500 CPU
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME netx500
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x07926021
|
||||
}
|
||||
|
||||
# jtag scan chain
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# that TAP is associated with a target
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
proc mread32 {addr} {
|
||||
set value(0) 0
|
||||
mem2array value 32 $addr 1
|
||||
return $value(0)
|
||||
}
|
||||
|
||||
# This function must be called on netX100/500 right after halt
|
||||
# If it is called later the needed register cannot be written anymore
|
||||
proc sdram_fix { } {
|
||||
|
||||
set accesskey [mread32 0x00100070]
|
||||
mww 0x00100070 [expr $accesskey]
|
||||
mww 0x0010002c 0x00000001
|
||||
|
||||
if {[expr [mread32 0x0010002c] & 0x07] == 0x07} {
|
||||
puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!"
|
||||
} else {
|
||||
puts "SDRAM Fix succeeded!"
|
||||
}
|
||||
}
|
||||
115
debuggers/openocd/tcl/target/icepick.cfg
Normal file
115
debuggers/openocd/tcl/target/icepick.cfg
Normal file
@ -0,0 +1,115 @@
|
||||
#
|
||||
# Copyright (C) 2011 by Karl Kurbjun
|
||||
# Copyright (C) 2009 by David Brownell
|
||||
#
|
||||
|
||||
# Utilities for TI ICEpick-C ... used in DaVinci, OMAP3, and more.
|
||||
# Details about the ICEPickC are available in the AM/DM37x document SPRUGN4M
|
||||
|
||||
# create "constants"
|
||||
proc CONST { key } {
|
||||
|
||||
array set constant {
|
||||
# define ICEPick instructions
|
||||
IR_BYPASS 0x00
|
||||
IR_ROUTER 0x02
|
||||
IR_CONNECT 0x07
|
||||
IF_BYPASS 0x3F
|
||||
}
|
||||
return $constant($key)
|
||||
}
|
||||
|
||||
# Instruction to connect to the icepick module
|
||||
proc icepick_c_connect {jrc} {
|
||||
|
||||
# Send CONNECT instruction in IR state
|
||||
irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
|
||||
|
||||
# Send write and connect key
|
||||
drscan $jrc 8 0x89 -endstate DRPAUSE
|
||||
}
|
||||
|
||||
# Instruction to disconnect to the icepick module
|
||||
proc icepick_c_disconnect {jrc} {
|
||||
|
||||
# Send CONNECT instruction in IR state
|
||||
irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
|
||||
|
||||
# Send write and connect key
|
||||
drscan $jrc 8 0x86 -endstate DRPAUSE
|
||||
}
|
||||
|
||||
#
|
||||
# icepick_c_router:
|
||||
# this function is for sending router commands
|
||||
# arguments are:
|
||||
# jrc: TAP name for the ICEpick
|
||||
# rw: read/write (0 for read, 1 for write)
|
||||
# block: icepick or DAP
|
||||
# register: which register to read/write
|
||||
# payload: value to read/write
|
||||
# this function is for sending router commands
|
||||
#
|
||||
proc icepick_c_router {jrc rw block register payload} {
|
||||
|
||||
set new_dr_value \
|
||||
[expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \
|
||||
( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ]
|
||||
|
||||
# echo "\tNew router value:\t0x[format %x $new_dr_value]"
|
||||
|
||||
# select router
|
||||
irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
|
||||
|
||||
# ROUTER instructions are 32 bits wide
|
||||
set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
|
||||
}
|
||||
|
||||
# Configure the icepick control register
|
||||
proc icepick_c_setup {jrc} {
|
||||
|
||||
# send a router write, block is 0, register is 1, value is 0x2100
|
||||
icepick_c_router $jrc 1 0x0 0x1 0x001000
|
||||
}
|
||||
|
||||
# jrc == TAP name for the ICEpick
|
||||
# port == a port number, 0..15
|
||||
proc icepick_c_tapenable {jrc port} {
|
||||
|
||||
# First CONNECT to the ICEPick
|
||||
# echo "Connecting to ICEPick"
|
||||
icepick_c_connect $jrc
|
||||
|
||||
# echo "Configuring the ICEpick"
|
||||
icepick_c_setup $jrc
|
||||
|
||||
# NOTE: it's important not to enter RUN/IDLE state until
|
||||
# done sending these instructions and data to the ICEpick.
|
||||
# And never to enter RESET, which will disable the TAPs.
|
||||
|
||||
# first enable power and clock for TAP
|
||||
icepick_c_router $jrc 1 0x2 $port 0x100048
|
||||
|
||||
# TRM states that the register should be read back here, skipped for now
|
||||
|
||||
# enable debug "default" mode
|
||||
icepick_c_router $jrc 1 0x2 $port 0x102048
|
||||
|
||||
# TRM states that debug enable and debug mode should be read back and
|
||||
# confirmed - skipped for now
|
||||
|
||||
# Finally select the tap
|
||||
icepick_c_router $jrc 1 0x2 $port 0x102148
|
||||
|
||||
# Enter the bypass state
|
||||
irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
|
||||
runtest 10
|
||||
}
|
||||
|
||||
# This function uses the ICEPick to send a warm system reset
|
||||
proc icepick_c_wreset {jrc} {
|
||||
|
||||
# send a router write, block is 0, register is 1, value is 0x2100
|
||||
icepick_c_router $jrc 1 0x0 0x1 0x002101
|
||||
}
|
||||
|
||||
30
debuggers/openocd/tcl/target/imx.cfg
Normal file
30
debuggers/openocd/tcl/target/imx.cfg
Normal file
@ -0,0 +1,30 @@
|
||||
# utility fn's for Freescale i.MX series
|
||||
|
||||
global TARGETNAME
|
||||
set TARGETNAME $_TARGETNAME
|
||||
|
||||
# rewrite commands of the form below to arm11 mcr...
|
||||
# Data.Set c15:0x042f %long 0x40000015
|
||||
proc setc15 {regs value} {
|
||||
global TARGETNAME
|
||||
|
||||
echo [format "set p15 0x%04x, 0x%08x" $regs $value]
|
||||
|
||||
arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
|
||||
}
|
||||
|
||||
|
||||
proc imx3x_reset {} {
|
||||
# this reset script comes from the Freescale PDK
|
||||
#
|
||||
# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
|
||||
|
||||
echo "Target Setup: initialize DRAM controller and peripherals"
|
||||
|
||||
# Data.Set c15:0x01 %long 0x00050078
|
||||
setc15 0x01 0x00050078
|
||||
|
||||
echo "configuring CP15 for enabling the peripheral bus"
|
||||
# Data.Set c15:0x042f %long 0x40000015
|
||||
setc15 0x042f 0x40000015
|
||||
}
|
||||
34
debuggers/openocd/tcl/target/imx21.cfg
Normal file
34
debuggers/openocd/tcl/target/imx21.cfg
Normal file
@ -0,0 +1,34 @@
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
#
|
||||
# Hmmm.... should srst_pulls_trst be used here like i.MX27???
|
||||
reset_config trst_and_srst
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx21
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
|
||||
# Note above there is 1 tap
|
||||
|
||||
# The CPU tap
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x0792611f
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
|
||||
# Create the GDB Target.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
|
||||
|
||||
arm7_9 dcc_downloads enable
|
||||
46
debuggers/openocd/tcl/target/imx25.cfg
Normal file
46
debuggers/openocd/tcl/target/imx25.cfg
Normal file
@ -0,0 +1,46 @@
|
||||
#
|
||||
# imx25 config
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx25
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists ETBTAPID] } {
|
||||
set _ETBTAPID $ETBTAPID
|
||||
} else {
|
||||
set _ETBTAPID 0x1b900f0f
|
||||
}
|
||||
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x07926041
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
|
||||
jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0
|
||||
|
||||
if { [info exists SDMATAPID] } {
|
||||
set _SDMATAPID $SDMATAPID
|
||||
} else {
|
||||
set _SDMATAPID 0x0882301d
|
||||
}
|
||||
jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
|
||||
-chain-position $_TARGETNAME
|
||||
|
||||
# trace setup
|
||||
etm config $_TARGETNAME 16 normal full etb
|
||||
etb config $_TARGETNAME $_CHIPNAME.etb
|
||||
53
debuggers/openocd/tcl/target/imx27.cfg
Normal file
53
debuggers/openocd/tcl/target/imx27.cfg
Normal file
@ -0,0 +1,53 @@
|
||||
# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3"
|
||||
# SRST pulls TRST
|
||||
#
|
||||
# Without setting these options correctly you'll see all sorts
|
||||
# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset
|
||||
# failing, etc.
|
||||
reset_config trst_and_srst srst_pulls_trst
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx27
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
|
||||
# Note above there are 2 taps
|
||||
|
||||
# trace buffer
|
||||
if { [info exists ETBTAPID] } {
|
||||
set _ETBTAPID $ETBTAPID
|
||||
} else {
|
||||
set _ETBTAPID 0x1b900f0f
|
||||
}
|
||||
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
|
||||
|
||||
# The CPU tap
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x07926121
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# Create the GDB Target.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
|
||||
# REVISIT what operating environment sets up this virtual address mapping?
|
||||
$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
|
||||
-work-area-size 0x8000 -work-area-backup 1
|
||||
# Internal to the chip, there is 45K of SRAM
|
||||
#
|
||||
|
||||
arm7_9 dcc_downloads enable
|
||||
|
||||
# trace setup
|
||||
etm config $_TARGETNAME 16 normal full etb
|
||||
etb config $_TARGETNAME $_CHIPNAME.etb
|
||||
38
debuggers/openocd/tcl/target/imx28.cfg
Normal file
38
debuggers/openocd/tcl/target/imx28.cfg
Normal file
@ -0,0 +1,38 @@
|
||||
# i.MX28 config file.
|
||||
# based off of the imx21.cfg file.
|
||||
|
||||
reset_config trst_and_srst
|
||||
|
||||
#jtag nTRST and nSRST delay
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx28
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
|
||||
# Note above there is 1 tap
|
||||
|
||||
# The CPU tap
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x079264f3
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
|
||||
# Create the GDB Target.
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
|
||||
|
||||
arm7_9 dcc_downloads enable
|
||||
68
debuggers/openocd/tcl/target/imx31.cfg
Normal file
68
debuggers/openocd/tcl/target/imx31.cfg
Normal file
@ -0,0 +1,68 @@
|
||||
# imx31 config
|
||||
#
|
||||
|
||||
reset_config trst_and_srst srst_gates_jtag
|
||||
|
||||
adapter_nsrst_delay 5
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx31
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x07b3601d
|
||||
}
|
||||
|
||||
if { [info exists SDMATAPID] } {
|
||||
set _SDMATAPID $SDMATAPID
|
||||
} else {
|
||||
set _SDMATAPID 0x2190101d
|
||||
}
|
||||
|
||||
if { [info exists ETBTAPID] } {
|
||||
set _ETBTAPID $ETBTAPID
|
||||
} else {
|
||||
set _ETBTAPID 0x2b900f0f
|
||||
}
|
||||
|
||||
#========================================
|
||||
|
||||
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
|
||||
|
||||
# The "SDMA" - <S>mart <DMA> controller debug tap
|
||||
# Based on some IO pins - this can be disabled & removed
|
||||
# See diagram: 6-14
|
||||
# SIGNAL NAME:
|
||||
# SJC_MOD - controls multiplexer - disables ARM1136
|
||||
# SDMA_BYPASS - disables SDMA -
|
||||
#
|
||||
# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
|
||||
|
||||
# No IDCODE for this TAP
|
||||
jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
|
||||
|
||||
# Per section 40.17.1, table 40-85 the IR register is 4 bits
|
||||
# But this conflicts with Diagram 6-13, "3bits ir and drs"
|
||||
jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
|
||||
proc power_restore {} { echo "Sensed power restore. No action." }
|
||||
proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
|
||||
|
||||
# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
|
||||
etm config $_TARGETNAME 16 normal full etb
|
||||
etb config $_TARGETNAME $_CHIPNAME.etb
|
||||
55
debuggers/openocd/tcl/target/imx35.cfg
Normal file
55
debuggers/openocd/tcl/target/imx35.cfg
Normal file
@ -0,0 +1,55 @@
|
||||
# imx35 config
|
||||
#
|
||||
|
||||
reset_config trst_and_srst srst_gates_jtag
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx35
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x07b3601d
|
||||
}
|
||||
|
||||
if { [info exists SDMATAPID] } {
|
||||
set _SDMATAPID $SDMATAPID
|
||||
} else {
|
||||
set _SDMATAPID 0x0882601d
|
||||
}
|
||||
|
||||
if { [info exists ETBTAPID] } {
|
||||
set _ETBTAPID $ETBTAPID
|
||||
} else {
|
||||
set _ETBTAPID 0x2b900f0f
|
||||
}
|
||||
|
||||
#========================================
|
||||
|
||||
jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
|
||||
|
||||
# No IDCODE for this TAP
|
||||
jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
|
||||
|
||||
jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
proc power_restore {} { echo "Sensed power restore. No action." }
|
||||
proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
|
||||
|
||||
# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
|
||||
etm config $_TARGETNAME 16 normal full etb
|
||||
etb config $_TARGETNAME $_CHIPNAME.etb
|
||||
51
debuggers/openocd/tcl/target/imx51.cfg
Normal file
51
debuggers/openocd/tcl/target/imx51.cfg
Normal file
@ -0,0 +1,51 @@
|
||||
# Freescale i.MX51
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx51
|
||||
}
|
||||
|
||||
# CoreSight Debug Access Port
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x1ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
|
||||
-expected-id $_DAP_TAPID
|
||||
|
||||
# SDMA / no IDCODE
|
||||
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
|
||||
|
||||
# SJC
|
||||
if { [info exists SJC_TAPID] } {
|
||||
set _SJC_TAPID SJC_TAPID
|
||||
} else {
|
||||
set _SJC_TAPID 0x0190c01d
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
|
||||
-expected-id $_SJC_TAPID -ignore-version
|
||||
|
||||
# GDB target: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
|
||||
|
||||
# some TCK tycles are required to activate the DEBUG power domain
|
||||
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
|
||||
|
||||
# have the DAP "always" be active
|
||||
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
|
||||
|
||||
proc imx51_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a dbginit
|
||||
}
|
||||
|
||||
# Slow speed to be sure it will work
|
||||
jtag_rclk 1000
|
||||
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
|
||||
|
||||
$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"
|
||||
51
debuggers/openocd/tcl/target/imx53.cfg
Normal file
51
debuggers/openocd/tcl/target/imx53.cfg
Normal file
@ -0,0 +1,51 @@
|
||||
# Freescale i.MX53
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx53
|
||||
}
|
||||
|
||||
# CoreSight Debug Access Port
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x1ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
|
||||
-expected-id $_DAP_TAPID
|
||||
|
||||
# SDMA / no IDCODE
|
||||
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
|
||||
|
||||
# SJC
|
||||
if { [info exists SJC_TAPID] } {
|
||||
set _SJC_TAPID SJC_TAPID
|
||||
} else {
|
||||
set _SJC_TAPID 0x0190d01d
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
|
||||
-expected-id $_SJC_TAPID -ignore-version
|
||||
|
||||
# GDB target: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
|
||||
|
||||
# some TCK tycles are required to activate the DEBUG power domain
|
||||
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
|
||||
|
||||
# have the DAP "always" be active
|
||||
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
|
||||
|
||||
proc imx53_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a dbginit
|
||||
}
|
||||
|
||||
# Slow speed to be sure it will work
|
||||
jtag_rclk 1000
|
||||
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
|
||||
|
||||
$_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME"
|
||||
56
debuggers/openocd/tcl/target/imx6.cfg
Normal file
56
debuggers/openocd/tcl/target/imx6.cfg
Normal file
@ -0,0 +1,56 @@
|
||||
# Freescale i.MX6 series single/dual/quad core processor
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME imx6
|
||||
}
|
||||
|
||||
# CoreSight Debug Access Port
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
|
||||
-expected-id $_DAP_TAPID
|
||||
|
||||
# SDMA / no IDCODE
|
||||
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
|
||||
|
||||
# System JTAG Controller
|
||||
if { [info exists SJC_TAPID] } {
|
||||
set _SJC_TAPID SJC_TAPID
|
||||
} else {
|
||||
set _SJC_TAPID 0x0191c01d
|
||||
}
|
||||
set _SJC_TAPID2 0x2191c01d
|
||||
|
||||
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
|
||||
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2
|
||||
|
||||
# GDB target: Cortex-A9, using DAP, configuring only one core
|
||||
# Base addresses of cores:
|
||||
# core 0 - 0x82150000
|
||||
# core 1 - 0x82152000
|
||||
# core 2 - 0x82154000
|
||||
# core 3 - 0x82156000
|
||||
set _TARGETNAME $_CHIPNAME.cpu.0
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
|
||||
-coreid 0 -dbgbase 0x82150000
|
||||
|
||||
# some TCK cycles are required to activate the DEBUG power domain
|
||||
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
|
||||
|
||||
proc imx6_dbginit {target} {
|
||||
# General Cortex A8/A9 debug initialisation
|
||||
cortex_a8 dbginit
|
||||
}
|
||||
|
||||
# Slow speed to be sure it will work
|
||||
jtag_rclk 1000
|
||||
$_TARGETNAME configure -event reset-start { jtag_rclk 1000 }
|
||||
|
||||
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
|
||||
$_TARGETNAME configure -event gdb-attach { halt }
|
||||
46
debuggers/openocd/tcl/target/is5114.cfg
Normal file
46
debuggers/openocd/tcl/target/is5114.cfg
Normal file
@ -0,0 +1,46 @@
|
||||
# script for Insilica IS-5114
|
||||
# AKA: Atmel AT76C114 - an ARM946 chip
|
||||
# ATMEL sold his product line to Insilica...
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME is5114
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
# this defaults to a little endian
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
# Force an error until we get a good number.
|
||||
set _CPUTAPID 0xffffffff
|
||||
}
|
||||
|
||||
# jtag speed. We need to stick to 16kHz until we've finished reset.
|
||||
jtag_rclk 16
|
||||
|
||||
reset_config trst_and_srst
|
||||
|
||||
# Do not specify a tap id here...
|
||||
jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
|
||||
# This is the "arm946" chip.
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf
|
||||
jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
|
||||
|
||||
|
||||
#arm946e-s and
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
|
||||
|
||||
$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# We can increase speed now that we know the target is halted.
|
||||
jtag_rclk 3000
|
||||
}
|
||||
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
|
||||
107
debuggers/openocd/tcl/target/ixp42x.cfg
Normal file
107
debuggers/openocd/tcl/target/ixp42x.cfg
Normal file
@ -0,0 +1,107 @@
|
||||
#xscale ixp42x CPU
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ixp42x
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
# this defaults to a bigendian
|
||||
set _ENDIAN big
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x19274013
|
||||
}
|
||||
set _CPUTAPID2 0x19275013
|
||||
set _CPUTAPID3 0x19277013
|
||||
set _CPUTAPID4 0x29274013
|
||||
set _CPUTAPID5 0x29275013
|
||||
set _CPUTAPID6 0x29277013
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
|
||||
|
||||
|
||||
# register constants for IXP42x SDRAM controller
|
||||
global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
|
||||
global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
|
||||
set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000
|
||||
set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001
|
||||
|
||||
global IXP42x_SDRAM_CL3
|
||||
global IXP42x_SDRAM_CL2
|
||||
set IXP42x_SDRAM_CL3 0x0008
|
||||
set IXP42x_SDRAM_CL2 0x0000
|
||||
|
||||
global IXP42x_SDRAM_8MB_2Mx32_1BANK
|
||||
global IXP42x_SDRAM_16MB_2Mx32_2BANK
|
||||
global IXP42x_SDRAM_16MB_4Mx16_1BANK
|
||||
global IXP42x_SDRAM_32MB_4Mx16_2BANK
|
||||
global IXP42x_SDRAM_32MB_8Mx16_1BANK
|
||||
global IXP42x_SDRAM_64MB_8Mx16_2BANK
|
||||
global IXP42x_SDRAM_64MB_16Mx16_1BANK
|
||||
global IXP42x_SDRAM_128MB_16Mx16_2BANK
|
||||
global IXP42x_SDRAM_128MB_32Mx16_1BANK
|
||||
global IXP42x_SDRAM_256MB_32Mx16_2BANK
|
||||
|
||||
set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030
|
||||
set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031
|
||||
set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032
|
||||
set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033
|
||||
set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010
|
||||
set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011
|
||||
set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012
|
||||
set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013
|
||||
set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014
|
||||
set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015
|
||||
|
||||
|
||||
# helper function to init SDRAM on IXP42x.
|
||||
# SDRAM_CFG: one of IXP42X_SDRAM_xxx
|
||||
# REFRESH: refresh counter reload value (integer)
|
||||
# CASLAT: 2 or 3
|
||||
proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
|
||||
|
||||
switch $CASLAT {
|
||||
2 {
|
||||
set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
|
||||
set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
|
||||
}
|
||||
3 {
|
||||
set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
|
||||
set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
|
||||
}
|
||||
default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
|
||||
}
|
||||
echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
|
||||
|
||||
mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
|
||||
mww 0xCC000004 0 ;# disable refresh
|
||||
mww 0xCC000008 3 ;# NOP
|
||||
sleep 100
|
||||
mww 0xCC000004 $REFRESH ;# set refresh counter
|
||||
mww 0xCC000008 2 ;# Precharge All Banks
|
||||
sleep 100
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 4 ;# Auto Refresh
|
||||
mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3
|
||||
}
|
||||
|
||||
proc ixp42x_set_bigendian { } {
|
||||
reg XSCALE_CTRL 0xF8
|
||||
}
|
||||
|
||||
39
debuggers/openocd/tcl/target/k40.cfg
Normal file
39
debuggers/openocd/tcl/target/k40.cfg
Normal file
@ -0,0 +1,39 @@
|
||||
#
|
||||
# Freescale Kinetis K40 devices
|
||||
#
|
||||
|
||||
#
|
||||
# K40 devices support both JTAG and SWD transports.
|
||||
#
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME k40
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
|
||||
|
||||
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
|
||||
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
39
debuggers/openocd/tcl/target/k60.cfg
Normal file
39
debuggers/openocd/tcl/target/k60.cfg
Normal file
@ -0,0 +1,39 @@
|
||||
#
|
||||
# Freescale Kinetis K60 devices
|
||||
#
|
||||
|
||||
#
|
||||
# K60 devices support both JTAG and SWD transports.
|
||||
#
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME k60
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x4ba00477
|
||||
}
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
|
||||
|
||||
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
|
||||
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
21
debuggers/openocd/tcl/target/lpc1751.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1751.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1751
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x2000
|
||||
set CPUROMSIZE 0x8000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1752.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1752.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1752
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x4000
|
||||
set CPUROMSIZE 0x10000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1754.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1754.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1754
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x4000
|
||||
set CPUROMSIZE 0x20000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1756.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1756.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1756
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x40000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1758.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1758.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1758
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x80000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1759.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1759.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1759
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x80000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1763.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1763.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1763
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x40000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1764.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1764.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1764
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x4000
|
||||
set CPUROMSIZE 0x20000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1765.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1765.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1765
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x40000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1766.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1766.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1766
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x40000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
21
debuggers/openocd/tcl/target/lpc1767.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc1767.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# !!!!!!!!!!!!
|
||||
# ! UNTESTED !
|
||||
# !!!!!!!!!!!!
|
||||
|
||||
# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1767
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x80000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
17
debuggers/openocd/tcl/target/lpc1768.cfg
Normal file
17
debuggers/openocd/tcl/target/lpc1768.cfg
Normal file
@ -0,0 +1,17 @@
|
||||
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1768
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x80000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
17
debuggers/openocd/tcl/target/lpc1769.cfg
Normal file
17
debuggers/openocd/tcl/target/lpc1769.cfg
Normal file
@ -0,0 +1,17 @@
|
||||
# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1769
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x8000
|
||||
set CPUROMSIZE 0x80000
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 4000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
20
debuggers/openocd/tcl/target/lpc1788.cfg
Normal file
20
debuggers/openocd/tcl/target/lpc1788.cfg
Normal file
@ -0,0 +1,20 @@
|
||||
# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
|
||||
set CHIPNAME lpc1788
|
||||
set CPUTAPID 0x4ba00477
|
||||
set CPURAMSIZE 0x10000
|
||||
set CPUROMSIZE 0x80000
|
||||
|
||||
# After reset the chip is clocked by the ~12MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
set CCLK 12000
|
||||
|
||||
#Include the main configuration file.
|
||||
source [find target/lpc17xx.cfg];
|
||||
|
||||
# if srst is not fitted, use SYSRESETREQ to perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
97
debuggers/openocd/tcl/target/lpc17xx.cfg
Normal file
97
debuggers/openocd/tcl/target/lpc17xx.cfg
Normal file
@ -0,0 +1,97 @@
|
||||
# Main file for NXP LPC17xx Cortex-M3
|
||||
#
|
||||
# !!!!!!
|
||||
#
|
||||
# This file should not be included directly, rather
|
||||
# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
|
||||
# needed variables to the appropriate values.
|
||||
#
|
||||
# !!!!!!
|
||||
|
||||
# LPC17xx chips support both JTAG and SWD transports.
|
||||
# Adapt based on what transport is active.
|
||||
source [find target/swj-dp.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
|
||||
}
|
||||
|
||||
# After reset the chip is clocked by the ~4MHz internal RC oscillator.
|
||||
# When board-specific code (reset-init handler or device firmware)
|
||||
# configures another oscillator and/or PLL0, set CCLK to match; if
|
||||
# you don't, then flash erase and write operations may misbehave.
|
||||
# (The ROM code doing those updates cares about core clock speed...)
|
||||
#
|
||||
# CCLK is the core clock frequency in KHz
|
||||
if { [info exists CCLK] } {
|
||||
set _CCLK $CCLK
|
||||
} else {
|
||||
set _CCLK 4000
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
|
||||
}
|
||||
|
||||
if { [info exists CPURAMSIZE] } {
|
||||
set _CPURAMSIZE $CPURAMSIZE
|
||||
} else {
|
||||
error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
|
||||
}
|
||||
|
||||
if { [info exists CPUROMSIZE] } {
|
||||
set _CPUROMSIZE $CPUROMSIZE
|
||||
} else {
|
||||
error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
|
||||
}
|
||||
|
||||
#delays on reset lines
|
||||
adapter_nsrst_delay 200
|
||||
jtag_ntrst_delay 200
|
||||
|
||||
#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
|
||||
|
||||
# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
|
||||
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
|
||||
|
||||
# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
|
||||
# (including a boot loader which verifies the flash exception table's checksum).
|
||||
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
|
||||
lpc1700 $_CCLK calc_checksum
|
||||
|
||||
# Run with *real slow* clock by default since the
|
||||
# boot rom could have been playing with the PLL, so
|
||||
# we have no idea what clock the target is running at.
|
||||
adapter_khz 10
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
|
||||
# "User Flash Mode" where interrupt vectors are _not_ remapped,
|
||||
# and reside in flash instead).
|
||||
#
|
||||
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
|
||||
# Bit Symbol Value Description Reset
|
||||
# value
|
||||
# 0 MAP Memory map control. 0
|
||||
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
|
||||
# 1 User mode. The on-chip Flash memory is mapped to address 0.
|
||||
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
|
||||
#
|
||||
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
|
||||
|
||||
mww 0x400FC040 0x01
|
||||
}
|
||||
|
||||
# if srst is not fitted use VECTRESET to
|
||||
# perform a soft reset - SYSRESETREQ is not supported
|
||||
cortex_m reset_config vectreset
|
||||
31
debuggers/openocd/tcl/target/lpc1850.cfg
Normal file
31
debuggers/openocd/tcl/target/lpc1850.cfg
Normal file
@ -0,0 +1,31 @@
|
||||
|
||||
adapter_khz 500
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME lpc1850
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
#
|
||||
# M3 JTAG mode TAP
|
||||
#
|
||||
if { [info exists M3_JTAG_TAPID] } {
|
||||
set _M3_JTAG_TAPID $M3_JTAG_TAPID
|
||||
} else {
|
||||
set _M3_JTAG_TAPID 0x4ba00477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.m3
|
||||
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
21
debuggers/openocd/tcl/target/lpc2103.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2103.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
|
||||
# 32kB flash and 8kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 12MHz crystal
|
||||
echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2103 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2103 12000 1500
|
||||
}
|
||||
21
debuggers/openocd/tcl/target/lpc2124.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2124.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
|
||||
# 256kB flash and 16kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 12MHz crystal
|
||||
echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2124 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2124 12000 1500
|
||||
}
|
||||
21
debuggers/openocd/tcl/target/lpc2129.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2129.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
|
||||
# 256kB flash and 16kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 12MHz crystal
|
||||
echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2129 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2129 12000 1500
|
||||
}
|
||||
21
debuggers/openocd/tcl/target/lpc2148.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2148.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
|
||||
# 500kB flash and 32kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 12MHz crystal
|
||||
echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2148 12000 1500
|
||||
}
|
||||
23
debuggers/openocd/tcl/target/lpc2294.cfg
Normal file
23
debuggers/openocd/tcl/target/lpc2294.cfg
Normal file
@ -0,0 +1,23 @@
|
||||
# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
|
||||
# 256kB flash and 16kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
|
||||
# !! TAPID unknown !!
|
||||
setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 12MHz crystal
|
||||
echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2294 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2294 12000 1500
|
||||
}
|
||||
21
debuggers/openocd/tcl/target/lpc2378.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2378.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
|
||||
# 504kB flash and 32kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 4MHz internal oscillator
|
||||
echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2378 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2378 4000 500
|
||||
}
|
||||
21
debuggers/openocd/tcl/target/lpc2460.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2460.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
|
||||
# 64kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 4MHz internal oscillator
|
||||
echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2460 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2460 4000 500
|
||||
}
|
||||
21
debuggers/openocd/tcl/target/lpc2478.cfg
Normal file
21
debuggers/openocd/tcl/target/lpc2478.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
|
||||
|
||||
source [find target/lpc2xxx.cfg]
|
||||
|
||||
# parameters:
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
|
||||
# 504kB flash and 64kB SRAM
|
||||
# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# default to core clocked with 4MHz internal oscillator
|
||||
echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
|
||||
|
||||
# setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
|
||||
setup_lpc2478 4000 500
|
||||
}
|
||||
66
debuggers/openocd/tcl/target/lpc2900.cfg
Normal file
66
debuggers/openocd/tcl/target/lpc2900.cfg
Normal file
@ -0,0 +1,66 @@
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME lpc2900
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x0596802B
|
||||
}
|
||||
|
||||
if { [info exists HAS_ETB] } {
|
||||
} else {
|
||||
# Set default (no ETB).
|
||||
# Show a warning, because this should have been configured explicitely.
|
||||
set HAS_ETB 0
|
||||
# TODO: warning?
|
||||
}
|
||||
|
||||
if { [info exists ETBTAPID] } {
|
||||
set _ETBTAPID $ETBTAPID
|
||||
} else {
|
||||
set _ETBTAPID 0x1B900F0F
|
||||
}
|
||||
|
||||
# TRST and SRST both exist, and can be controlled independently
|
||||
reset_config trst_and_srst separate
|
||||
|
||||
# Define the _TARGETNAME
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
# Include the ETB tap controller if asked for.
|
||||
# Has to be done manually for newer devices (not an "old" LPC2917/2919).
|
||||
if { $HAS_ETB == 1 } {
|
||||
# Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
|
||||
set HAS_ETB 0
|
||||
|
||||
# Add the ETB tap controller and the ARM9 core debug tap
|
||||
jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# Create the ".cpu" target
|
||||
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
|
||||
|
||||
# Configure ETM and ETB
|
||||
etm config $_TARGETNAME 8 normal full etb
|
||||
etb config $_TARGETNAME $_CHIPNAME.etb
|
||||
|
||||
} else {
|
||||
# Add the ARM9 core debug tap
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# Create the ".cpu" target
|
||||
target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME -variant arm966e
|
||||
}
|
||||
|
||||
arm7_9 dbgrq enable
|
||||
arm7_9 dcc_downloads enable
|
||||
|
||||
# Flash bank configuration:
|
||||
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
|
||||
# Flash base address, total flash size, and number of sectors are all configured automatically.
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
|
||||
44
debuggers/openocd/tcl/target/lpc2xxx.cfg
Normal file
44
debuggers/openocd/tcl/target/lpc2xxx.cfg
Normal file
@ -0,0 +1,44 @@
|
||||
# Common setup for the LPC2xxx parts
|
||||
|
||||
# parameters:
|
||||
# - chip_name - name of the chip, e.g. lpc2103
|
||||
# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or "0x3f0f0f0f 0x4f1f0f0f"
|
||||
# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000
|
||||
# - flash_variant - "type" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
|
||||
# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000
|
||||
# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
|
||||
# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
|
||||
|
||||
proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} {
|
||||
reset_config trst_and_srst
|
||||
|
||||
# reset delays
|
||||
adapter_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
adapter_khz $adapter_freq_khz
|
||||
|
||||
foreach i $cputapids {
|
||||
append expected_ids "-expected-id " $i " "
|
||||
}
|
||||
|
||||
eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids"
|
||||
|
||||
global _TARGETNAME
|
||||
set _TARGETNAME $chip_name.cpu
|
||||
target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0
|
||||
|
||||
if { $flash_size > 0 } {
|
||||
# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
|
||||
set _FLASHNAME $chip_name.flash
|
||||
flash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum
|
||||
}
|
||||
}
|
||||
|
||||
proc init_targets {} {
|
||||
# FIX!!! read out CPUTAPID here and choose right setup. In addition to the
|
||||
# CPUTAPID some querying of the target would be required.
|
||||
return -error "This is a generic LPC2xxx configuration file, use a specific target file."
|
||||
}
|
||||
76
debuggers/openocd/tcl/target/lpc3131.cfg
Normal file
76
debuggers/openocd/tcl/target/lpc3131.cfg
Normal file
@ -0,0 +1,76 @@
|
||||
######################################
|
||||
# Target: NXP lpc3131
|
||||
######################################
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME lpc3131
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# ARM926EJS core
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x07926f0f
|
||||
}
|
||||
|
||||
# Scan Tap
|
||||
# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
|
||||
# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
|
||||
if { [info exists SJCTAPID] } {
|
||||
set _SJCTAPID $SJCTAPID
|
||||
} else {
|
||||
set _SJCTAPID 0x1541E02B
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
|
||||
|
||||
##################################################################
|
||||
# various symbol definitions, to avoid hard-wiring addresses
|
||||
##################################################################
|
||||
|
||||
global lpc313x
|
||||
set lpc313x [ dict create ]
|
||||
|
||||
# Physical addresses for controllers and memory
|
||||
dict set lpc313x sram0 0x11028000
|
||||
dict set lpc313x sram1 0x11040000
|
||||
dict set lpc313x uart 0x15001000
|
||||
dict set lpc313x cgu 0x13004000
|
||||
dict set lpc313x ioconfig 0x13003000
|
||||
dict set lpc313x sysconfig 0x13002800
|
||||
dict set lpc313x wdt 0x13002400
|
||||
|
||||
##################################################################
|
||||
# Target configuration
|
||||
##################################################################
|
||||
|
||||
adapter_nsrst_delay 1000
|
||||
jtag_ntrst_delay 0
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME invoke-event halted
|
||||
|
||||
$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
echo "\nRunning reset init script for LPC3131\n"
|
||||
halt
|
||||
wait_halt
|
||||
reg cpsr 0xa00000d3 ;#Supervisor mode
|
||||
reg pc 0x11029000
|
||||
poll
|
||||
sleep 500
|
||||
}
|
||||
|
||||
arm7_9 fast_memory_access enable
|
||||
arm7_9 dcc_downloads enable
|
||||
43
debuggers/openocd/tcl/target/lpc3250.cfg
Normal file
43
debuggers/openocd/tcl/target/lpc3250.cfg
Normal file
@ -0,0 +1,43 @@
|
||||
# lpc3250 config
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME lpc3250
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x17900f0f
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID_REV_A0] } {
|
||||
set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0
|
||||
} else {
|
||||
set _CPUTAPID_REV_A0 0x17926f0f
|
||||
}
|
||||
|
||||
if { [info exists SJCTAPID] } {
|
||||
set _SJCTAPID $SJCTAPID
|
||||
} else {
|
||||
set _SJCTAPID 0x1b900f0f
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \
|
||||
-expected-id $_CPUTAPID_REV_A0
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0
|
||||
|
||||
proc power_restore {} { echo "Sensed power restore. No action." }
|
||||
proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
|
||||
51
debuggers/openocd/tcl/target/lpc4350.cfg
Normal file
51
debuggers/openocd/tcl/target/lpc4350.cfg
Normal file
@ -0,0 +1,51 @@
|
||||
|
||||
adapter_khz 500
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME lpc4350
|
||||
}
|
||||
|
||||
#
|
||||
# M4 JTAG mode TAP
|
||||
#
|
||||
if { [info exists M4_JTAG_TAPID] } {
|
||||
set _M4_JTAG_TAPID $M4_JTAG_TAPID
|
||||
} else {
|
||||
set _M4_JTAG_TAPID 0x4ba00477
|
||||
}
|
||||
|
||||
#
|
||||
# M4 SWD mode TAP
|
||||
#
|
||||
if { [info exists M4_SWD_TAPID] } {
|
||||
set _M4_SWD_TAPID $M4_SWD_TAPID
|
||||
} else {
|
||||
set _M4_SWD_TAPID 0x2ba01477
|
||||
}
|
||||
|
||||
#
|
||||
# M0 TAP
|
||||
#
|
||||
if { [info exists M0_JTAG_TAPID] } {
|
||||
set _M0_JTAG_TAPID $M0_JTAG_TAPID
|
||||
} else {
|
||||
set _M0_JTAG_TAPID 0x0ba01477
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
|
||||
-expected-id $_M4_JTAG_TAPID
|
||||
|
||||
jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
|
||||
-expected-id $_M0_JTAG_TAPID
|
||||
|
||||
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
|
||||
target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
|
||||
|
||||
# on this CPU we should use VECTRESET to perform a soft reset and
|
||||
# manually reset the periphery
|
||||
# SRST or SYSRESETREQ disable the debug interface for the time of
|
||||
# the reset and will not fit our requirements for a consistent debug
|
||||
# session
|
||||
cortex_m reset_config vectreset
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user