debuggers: import openocd-0.7.0
Initial check-in of openocd-0.7.0 as it can be downloaded from http://sourceforge.net/projects/openocd/files/openocd/0.7.0/ Any modifications will follow. Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55
This commit is contained in:
Lars Rademacher
75
debuggers/openocd/tcl/chip/st/spear/quirk_no_srst.tcl
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75
debuggers/openocd/tcl/chip/st/spear/quirk_no_srst.tcl
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@ -0,0 +1,75 @@
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# Quirks to bypass missing SRST on JTAG connector
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# EVALSPEAr310 Rev. 2.0
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# http://www.st.com/spear
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#
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# Date: 2010-08-17
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# Author: Antonio Borneo <borneo.antonio@gmail.com>
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# For boards that have JTAG SRST not connected.
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# We use "arm9 vector_catch reset" to catch button reset event.
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$_TARGETNAME configure -event reset-assert sp_reset_assert
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$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post
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# keeps the name of the SPEAr target
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global sp_target_name
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set sp_target_name $_TARGETNAME
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# Keeps the argument of "reset" command (run, init, halt).
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global sp_reset_mode
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set sp_reset_mode ""
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# Helper procedure. Returns 0 is target is halted.
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proc sp_is_halted {} {
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global sp_target_name
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return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
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}
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# wait for reset button to be pressed, causing CPU to get halted
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proc sp_reset_deassert_post {} {
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global sp_reset_mode
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set bar(0) |
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set bar(1) /
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set bar(2) -
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set bar(3) \\
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poll on
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echo "====> Press reset button on the board <===="
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for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} {
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echo -n "$bar([expr $i & 3])\r"
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sleep 200
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}
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# Remove catch reset event
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arm9 vector_catch none
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# CPU is halted, but we typed "reset run" ...
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if { [string compare $sp_reset_mode "run"] == 0 } {
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resume
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}
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}
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# Override reset-assert, since no SRST available
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# Catch reset event
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proc sp_reset_assert {} {
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arm9 vector_catch reset
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}
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# Override default init_reset{mode} to catch parameter "mode"
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proc init_reset {mode} {
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global sp_reset_mode
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set sp_reset_mode $mode
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# We need to detect CPU get halted, so exit from halt
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if { [sp_is_halted] } {
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echo "Resuming CPU to detect reset"
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resume
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}
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# Execute default init_reset{mode}
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jtag arp_init-reset
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}
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129
debuggers/openocd/tcl/chip/st/spear/spear3xx.tcl
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129
debuggers/openocd/tcl/chip/st/spear/spear3xx.tcl
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@ -0,0 +1,129 @@
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# Generic init scripts for all ST SPEAr3xx family
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# http://www.st.com/spear
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#
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# Date: 2010-09-23
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# Author: Antonio Borneo <borneo.antonio@gmail.com>
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# Initialize internal clock
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# Default:
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# - Crystal = 24 MHz
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# - PLL1 = 332 MHz
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# - PLL2 = 332 MHz
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# - CPU_CLK = 332 MHz
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# - DDR_CLK = 332 MHz async
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# - HCLK = 166 MHz
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# - PCLK = 83 MHz
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proc sp3xx_clock_default {} {
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mww 0xfca00000 0x00000002 ;# set sysclk slow
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mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
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# DDRCORE disable to change frequency
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set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
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mww 0xfca8002c $val
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mww 0xfca8002c $val ;# Yes, write twice!
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# programming PLL1
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mww 0xfca8000c 0xa600010c ;# M=166 P=1 N=12
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mww 0xfca80008 0x00001c0a ;# power down
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mww 0xfca80008 0x00001c0e ;# enable
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mww 0xfca80008 0x00001c06 ;# strobe
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mww 0xfca80008 0x00001c0e
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while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
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# programming PLL2
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mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
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mww 0xfca80014 0x00001c0a ;# power down
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mww 0xfca80014 0x00001c0e ;# enable
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mww 0xfca80014 0x00001c06 ;# strobe
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mww 0xfca80014 0x00001c0e
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while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
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mww 0xfca80028 0x00000082 ;# enable plltimeen
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mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
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mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
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while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
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# Select source of DDR clock
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#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
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mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
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# DDRCORE enable after change frequency
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mmw 0xfca8002c 0x20000000 0x00000000
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}
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proc sp3xx_common_init {} {
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mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals
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mww 0xfca80038 0x00000000 ;# remove reset of all peripherals
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mww 0xfca80034 0x0000ffff ;# enable all RAS clocks
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mww 0xfca80040 0x00000000 ;# remove all RAS resets
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mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
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mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
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mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
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mww 0xfc000000 0x00000f5f
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# Initialize Bus Interconnection Matrix
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# All ports Round-Robin and lowest priority
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mww 0xfca8007c 0x80000007
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mww 0xfca80080 0x80000007
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mww 0xfca80084 0x80000007
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mww 0xfca80088 0x80000007
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mww 0xfca8008c 0x80000007
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mww 0xfca80090 0x80000007
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mww 0xfca80094 0x80000007
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mww 0xfca80098 0x80000007
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mww 0xfca8009c 0x80000007
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}
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# Specific init scripts for ST SPEAr300
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proc sp300_init {} {
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mww 0x99000000 0x00003fff ;# RAS function enable
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}
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# Specific init scripts for ST SPEAr310
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proc sp310_init {} {
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mww 0xb4000008 0x00002ff4 ;# RAS function enable
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mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
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mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
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mww 0xfca80140 0x017bdef6
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}
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proc sp310_emi_init {} {
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# set EMI pad strength
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mmw 0xfca80134 0x0e000000 0x00000000
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mmw 0xfca80138 0x0e739ce7 0x00000000
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mmw 0xfca8013c 0x00039ce7 0x00000000
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# set safe EMI timing as in BootROM
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#mww 0x4f000000 0x0000000f ;# tAP_0_reg
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#mww 0x4f000004 0x00000000 ;# tSDP_0_reg
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#mww 0x4f000008 0x000000ff ;# tDPw_0_reg
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#mww 0x4f00000c 0x00000111 ;# tDPr_0_reg
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#mww 0x4f000010 0x00000002 ;# tDCS_0_reg
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# set fast EMI timing as in Linux
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mww 0x4f000000 0x00000010 ;# tAP_0_reg
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mww 0x4f000004 0x00000005 ;# tSDP_0_reg
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mww 0x4f000008 0x0000000a ;# tDPw_0_reg
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mww 0x4f00000c 0x0000000a ;# tDPr_0_reg
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mww 0x4f000010 0x00000005 ;# tDCS_0_re
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# 32bit wide, 8/16/32bit access
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mww 0x4f000014 0x0000000e ;# control_0_reg
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mww 0x4f000094 0x0000003f ;# ack_reg
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}
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# Specific init scripts for ST SPEAr320
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proc sp320_init {} {
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mww 0xb300000c 0xffffac04 ;# RAS function enable
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mww 0xb3000010 0x00000001 ;# RAS mode select
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}
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127
debuggers/openocd/tcl/chip/st/spear/spear3xx_ddr.tcl
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127
debuggers/openocd/tcl/chip/st/spear/spear3xx_ddr.tcl
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@ -0,0 +1,127 @@
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# Init scripts to configure DDR controller of SPEAr3xx
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# http://www.st.com/spear
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# Original values taken from XLoader source code
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#
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# Date: 2010-09-23
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# Author: Antonio Borneo <borneo.antonio@gmail.com>
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proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
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if { $ddr_chips != 1 && $ddr_chips != 2 } {
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error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips
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}
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if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
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ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips
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set ddr_size 0x08000000
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## add here new DDR chip definition. Prototype:
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#} elseif { $ddr_type == "?????" } {
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# ????? $ddr_chips
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# set ddr_size 0x?????
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} else {
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error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
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}
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# MPMC START
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mww 0xfc60001c 0x01000100
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if { $ddr_chips == 2 } {
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echo [format \
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"Double chip DDR memory. Total memory size 0x%08x byte" \
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[expr 2 * $ddr_size]]
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} else {
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echo [format \
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"Single chip DDR memory. Memory size 0x%08x byte" \
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$ddr_size]
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}
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}
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# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
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proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {
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# DDR_PAD_REG
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mww 0xfca800f0 0x00003aa5
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# Use "1:2 sync" only when DDR clock source is PLL1 and
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# HCLK is half of PLL1
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mww 0xfc600000 0x00000001 ;# MEMCTL_AHB_SET_00 # This is async
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mww 0xfc600004 0x00000000 ;# MEMCTL_AHB_SET_01
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# mww 0xfc600000 0x02020201 ;# MEMCTL_AHB_SET_00 # This is 1:2 sync
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# mww 0xfc600004 0x02020202 ;# MEMCTL_AHB_SET_01
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mww 0xfc600008 0x01000000 ;# MEMCTL_RFSH_SET_00
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mww 0xfc60000c 0x00000101 ;# MEMCTL_DLL_SET_00
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mww 0xfc600010 0x00000101 ;# MEMCTL_GP_00
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mww 0xfc600014 0x01000000 ;# MEMCTL_GP_01
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mww 0xfc600018 0x00010001 ;# MEMCTL_GP_02
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mww 0xfc60001c 0x00000100 ;# MEMCTL_GP_03
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mww 0xfc600020 0x00010001 ;# MEMCTL_GP_04
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if { $ddr_chips == 2 } {
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mww 0xfc600024 0x01020203 ;# MEMCTL_GP_05
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mww 0xfc600028 0x01000102 ;# MEMCTL_GP_06
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mww 0xfc60002c 0x02000202 ;# MEMCTL_AHB_SET_02
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} else {
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mww 0xfc600024 0x00000201 ;# MEMCTL_GP_05
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mww 0xfc600028 0x02000001 ;# MEMCTL_GP_06
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mww 0xfc60002c 0x02000201 ;# MEMCTL_AHB_SET_02
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}
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mww 0xfc600030 0x04040105 ;# MEMCTL_AHB_SET_03
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mww 0xfc600034 0x03030302 ;# MEMCTL_AHB_SET_04
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mww 0xfc600038 0x02040101 ;# MEMCTL_AHB_SET_05
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mww 0xfc60003c 0x00000002 ;# MEMCTL_AHB_SET_06
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mww 0xfc600044 0x03000405 ;# MEMCTL_DQS_SET_0
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mww 0xfc600048 0x03040002 ;# MEMCTL_TIME_SET_01
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mww 0xfc60004c 0x04000305 ;# MEMCTL_TIME_SET_02
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mww 0xfc600050 0x0505053f ;# MEMCTL_AHB_RELPR_00
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mww 0xfc600054 0x05050505 ;# MEMCTL_AHB_RELPR_01
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mww 0xfc600058 0x04040405 ;# MEMCTL_AHB_RELPR_02
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mww 0xfc60005c 0x04040404 ;# MEMCTL_AHB_RELPR_03
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mww 0xfc600060 0x03030304 ;# MEMCTL_AHB_RELPR_04
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mww 0xfc600064 0x03030303 ;# MEMCTL_AHB_RELPR_05
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mww 0xfc600068 0x02020203 ;# MEMCTL_AHB_RELPR_06
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mww 0xfc60006c 0x02020202 ;# MEMCTL_AHB_RELPR_07
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mww 0xfc600070 0x01010102 ;# MEMCTL_AHB_RELPR_08
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mww 0xfc600074 0x01010101 ;# MEMCTL_AHB_RELPR_09
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mww 0xfc600078 0x00000001 ;# MEMCTL_AHB_RELPR_10
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mww 0xfc600088 0x0a0c0a00 ;# MEMCTL_DQS_SET_1
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mww 0xfc60008c 0x0000023f ;# MEMCTL_GP_07
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mww 0xfc600090 0x00050a00 ;# MEMCTL_GP_08
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mww 0xfc600094 0x11000000 ;# MEMCTL_GP_09
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mww 0xfc600098 0x00001302 ;# MEMCTL_GP_10
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mww 0xfc60009c 0x00001c1c ;# MEMCTL_DLL_SET_01
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mww 0xfc6000a0 0x7c000000 ;# MEMCTL_DQS_OUT_SHIFT
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mww 0xfc6000a4 0x005c0000 ;# MEMCTL_WR_DQS_SHIFT
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mww 0xfc6000a8 0x2b050e00 ;# MEMCTL_TIME_SET_03
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mww 0xfc6000ac 0x00640064 ;# MEMCTL_AHB_PRRLX_00
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mww 0xfc6000b0 0x00640064 ;# MEMCTL_AHB_PRRLX_01
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mww 0xfc6000b4 0x00000064 ;# MEMCTL_AHB_PRRLX_02
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mww 0xfc6000b8 0x00000000 ;# MEMCTL_OUTRANGE_LGTH
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mww 0xfc6000bc 0x00200020 ;# MEMCTL_AHB_RW_SET_00
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mww 0xfc6000c0 0x00200020 ;# MEMCTL_AHB_RW_SET_01
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mww 0xfc6000c4 0x00200020 ;# MEMCTL_AHB_RW_SET_02
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mww 0xfc6000c8 0x00200020 ;# MEMCTL_AHB_RW_SET_03
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mww 0xfc6000cc 0x00200020 ;# MEMCTL_AHB_RW_SET_04
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mww 0xfc6000d8 0x00000a24 ;# MEMCTL_TREF
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mww 0xfc6000dc 0x00000000 ;# MEMCTL_EMRS3_DATA
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mww 0xfc6000e0 0x5b1c00c8 ;# MEMCTL_TIME_SET_04
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mww 0xfc6000e4 0x00c8002e ;# MEMCTL_TIME_SET_05
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mww 0xfc6000e8 0x00000000 ;# MEMCTL_VERSION
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mww 0xfc6000ec 0x0001046b ;# MEMCTL_TINIT
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mww 0xfc6000f0 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_01
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mww 0xfc6000f4 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_02
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mww 0xfc600104 0x001c0000 ;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
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mww 0xfc600108 0x0019001c ;# MEMCTL_DLL_SET_02
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mww 0xfc60010c 0x00100000 ;# MEMCTL_DLL_SET_03
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mww 0xfc600110 0x001e007a ;# MEMCTL_DQS_SET_2
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mww 0xfc600188 0x00000000 ;# MEMCTL_USER_DEF_REG_0
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mww 0xfc60018c 0x00000000 ;# MEMCTL_USER_DEF_REG_1
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mww 0xfc600190 0x01010001 ;# MEMCTL_GP_11
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mww 0xfc600194 0x01000000 ;# MEMCTL_GP_12
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mww 0xfc600198 0x00000001 ;# MEMCTL_GP_13
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mww 0xfc60019c 0x00400000 ;# MEMCTL_GP_14
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mww 0xfc6001a0 0x00000000 ;# MEMCTL_EMRS2_DATA_X
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mww 0xfc6001a4 0x00000000 ;# MEMCTL_LWPWR_CNT
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mww 0xfc6001a8 0x00000000 ;# MEMCTL_LWPWR_REG
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mww 0xfc6001ac 0x00860000 ;# MEMCTL_GP_15
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mww 0xfc6001b0 0x00000002 ;# MEMCTL_TPDEX
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}
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