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debuggers: import openocd-0.7.0

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Initial check-in of openocd-0.7.0 as it can be downloaded from
http://sourceforge.net/projects/openocd/files/openocd/0.7.0/

Any modifications will follow.

Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55
This commit is contained in:
Lars Rademacher
2013-10-21 00:50:02 +02:00
parent 85fffe007e
commit 83d72a091e
1148 changed files with 571445 additions and 0 deletions
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101
debuggers/openocd/tcl/chip/atmel/at91/aic.tcl Normal file
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set AIC_SMR [expr $AT91C_BASE_AIC + 0x00000000 ]
global AIC_SMR
set AIC_SVR [expr $AT91C_BASE_AIC + 0x00000080 ]
global AIC_SVR
set AIC_IVR [expr $AT91C_BASE_AIC + 0x00000100 ]
global AIC_IVR
set AIC_FVR [expr $AT91C_BASE_AIC + 0x00000104 ]
global AIC_FVR
set AIC_ISR [expr $AT91C_BASE_AIC + 0x00000108 ]
global AIC_ISR
set AIC_IPR [expr $AT91C_BASE_AIC + 0x0000010C ]
global AIC_IPR
set AIC_IMR [expr $AT91C_BASE_AIC + 0x00000110 ]
global AIC_IMR
set AIC_CISR [expr $AT91C_BASE_AIC + 0x00000114 ]
global AIC_CISR
set AIC_IECR [expr $AT91C_BASE_AIC + 0x00000120 ]
global AIC_IECR
set AIC_IDCR [expr $AT91C_BASE_AIC + 0x00000124 ]
global AIC_IDCR
set AIC_ICCR [expr $AT91C_BASE_AIC + 0x00000128 ]
global AIC_ICCR
set AIC_ISCR [expr $AT91C_BASE_AIC + 0x0000012C ]
global AIC_ISCR
set AIC_EOICR [expr $AT91C_BASE_AIC + 0x00000130 ]
global AIC_EOICR
set AIC_SPU [expr $AT91C_BASE_AIC + 0x00000134 ]
global AIC_SPU
set AIC_DCR [expr $AT91C_BASE_AIC + 0x00000138 ]
global AIC_DCR
set AIC_FFER [expr $AT91C_BASE_AIC + 0x00000140 ]
global AIC_FFER
set AIC_FFDR [expr $AT91C_BASE_AIC + 0x00000144 ]
global AIC_FFDR
set AIC_FFSR [expr $AT91C_BASE_AIC + 0x00000148 ]
global AIC_FFSR
proc aic_enable_disable_list { VAL ENAME DNAME } {
global AT91C_ID
show_mmr32_bits AT91C_ID $VAL
}
proc show_AIC_IPR_helper { NAME ADDR VAL } {
aic_enable_disable_list $VAL "IRQ PENDING" "irq not-pending"
}
proc show_AIC_IMR_helper { NAME ADDR VAL } {
aic_enable_disable_list $VAL "IRQ ENABLED" "irq disabled"
}
proc show_AIC { } {
global AIC_SMR
if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] {
error [format "%s (%s)" $msg AIC_SMR]
}
echo "AIC_SMR: Mode & Type"
global AT91C_ID
for { set x 0 } { $x < 32 } { } {
echo -n " "
echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
incr x
echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
incr x
echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
incr x
echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
incr x
}
global AIC_SVR
if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] {
error [format "%s (%s)" $msg AIC_SVR]
}
echo "AIC_SVR: Vectors"
for { set x 0 } { $x < 32 } { } {
echo -n " "
echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
incr x
echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
incr x
echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
incr x
echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
incr x
}
foreach REG {
AIC_IVR AIC_FVR AIC_ISR
AIC_IPR AIC_IMR AIC_CISR AIC_IECR AIC_IDCR
AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR
AIC_FFER AIC_FFDR AIC_FFSR } {
if [catch { show_mmr32_reg $REG } msg ] {
error $msg
break
}
}
}

29
debuggers/openocd/tcl/chip/atmel/at91/at91_pio.cfg Normal file
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set PIO_PER 0x00 ;# Enable Register
set PIO_PDR 0x04 ;# Disable Register
set PIO_PSR 0x08 ;# Status Register
set PIO_OER 0x10 ;# Output Enable Register
set PIO_ODR 0x14 ;# Output Disable Register
set PIO_OSR 0x18 ;# Output Status Register
set PIO_IFER 0x20 ;# Glitch Input Filter Enable
set PIO_IFDR 0x24 ;# Glitch Input Filter Disable
set PIO_IFSR 0x28 ;# Glitch Input Filter Status
set PIO_SODR 0x30 ;# Set Output Data Register
set PIO_CODR 0x34 ;# Clear Output Data Register
set PIO_ODSR 0x38 ;# Output Data Status Register
set PIO_PDSR 0x3c ;# Pin Data Status Register
set PIO_IER 0x40 ;# Interrupt Enable Register
set PIO_IDR 0x44 ;# Interrupt Disable Register
set PIO_IMR 0x48 ;# Interrupt Mask Register
set PIO_ISR 0x4c ;# Interrupt Status Register
set PIO_MDER 0x50 ;# Multi-driver Enable Register
set PIO_MDDR 0x54 ;# Multi-driver Disable Register
set PIO_MDSR 0x58 ;# Multi-driver Status Register
set PIO_PUDR 0x60 ;# Pull-up Disable Register
set PIO_PUER 0x64 ;# Pull-up Enable Register
set PIO_PUSR 0x68 ;# Pull-up Status Register
set PIO_ASR 0x70 ;# Peripheral A Select Register
set PIO_BSR 0x74 ;# Peripheral B Select Register
set PIO_ABSR 0x78 ;# AB Status Register
set PIO_OWER 0xa0 ;# Output Write Enable Register
set PIO_OWDR 0xa4 ;# Output Write Disable Register
set PIO_OWSR 0xa8 ;# Output Write Status Register

113
debuggers/openocd/tcl/chip/atmel/at91/at91_pmc.cfg Normal file
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set AT91_PMC_SCER [expr ($AT91_PMC + 0x00)] ;# System Clock Enable Register
set AT91_PMC_SCDR [expr ($AT91_PMC + 0x04)] ;# System Clock Disable Register
set AT91_PMC_SCSR [expr ($AT91_PMC + 0x08)] ;# System Clock Status Register
set AT91_PMC_PCK [expr (1 << 0)] ;# Processor Clock
set AT91RM9200_PMC_UDP [expr (1 << 1)] ;# USB Devcice Port Clock [AT91RM9200 only]
set AT91RM9200_PMC_MCKUDP [expr (1 << 2)] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
set AT91CAP9_PMC_DDR [expr (1 << 2)] ;# DDR Clock [CAP9 revC & some SAM9 only]
set AT91RM9200_PMC_UHP [expr (1 << 4)] ;# USB Host Port Clock [AT91RM9200 only]
set AT91SAM926x_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91SAM926x only]
set AT91CAP9_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91CAP9 only]
set AT91SAM926x_PMC_UDP [expr (1 << 7)] ;# USB Devcice Port Clock [AT91SAM926x only]
set AT91_PMC_PCK0 [expr (1 << 8)] ;# Programmable Clock 0
set AT91_PMC_PCK1 [expr (1 << 9)] ;# Programmable Clock 1
set AT91_PMC_PCK2 [expr (1 << 10)] ;# Programmable Clock 2
set AT91_PMC_PCK3 [expr (1 << 11)] ;# Programmable Clock 3
set AT91_PMC_HCK0 [expr (1 << 16)] ;# AHB Clock (USB host) [AT91SAM9261 only]
set AT91_PMC_HCK1 [expr (1 << 17)] ;# AHB Clock (LCD) [AT91SAM9261 only]
set AT91_PMC_PCER [expr ($AT91_PMC + 0x10)] ;# Peripheral Clock Enable Register
set AT91_PMC_PCDR [expr ($AT91_PMC + 0x14)] ;# Peripheral Clock Disable Register
set AT91_PMC_PCSR [expr ($AT91_PMC + 0x18)] ;# Peripheral Clock Status Register
set AT91_CKGR_UCKR [expr ($AT91_PMC + 0x1C)] ;# UTMI Clock Register [some SAM9, CAP9]
set AT91_PMC_UPLLEN [expr (1 << 16)] ;# UTMI PLL Enable
set AT91_PMC_UPLLCOUNT [expr (0xf << 20)] ;# UTMI PLL Start-up Time
set AT91_PMC_BIASEN [expr (1 << 24)] ;# UTMI BIAS Enable
set AT91_PMC_BIASCOUNT [expr (0xf << 28)] ;# UTMI BIAS Start-up Time
set AT91_CKGR_MOR [expr ($AT91_PMC + 0x20)] ;# Main Oscillator Register [not on SAM9RL]
set AT91_PMC_MOSCEN [expr (1 << 0)] ;# Main Oscillator Enable
set AT91_PMC_OSCBYPASS [expr (1 << 1)] ;# Oscillator Bypass [SAM9x, CAP9]
set AT91_PMC_OSCOUNT [expr (0xff << 8)] ;# Main Oscillator Start-up Time
set AT91_CKGR_MCFR [expr ($AT91_PMC + 0x24)] ;# Main Clock Frequency Register
set AT91_PMC_MAINF [expr (0xffff << 0)] ;# Main Clock Frequency
set AT91_PMC_MAINRDY [expr (1 << 16)] ;# Main Clock Ready
set AT91_CKGR_PLLAR [expr ($AT91_PMC + 0x28)] ;# PLL A Register
set AT91_CKGR_PLLBR [expr ($AT91_PMC + 0x2c)] ;# PLL B Register
set AT91_PMC_DIV [expr (0xff << 0)] ;# Divider
set AT91_PMC_PLLCOUNT [expr (0x3f << 8)] ;# PLL Counter
set AT91_PMC_OUT [expr (3 << 14)] ;# PLL Clock Frequency Range
set AT91_PMC_MUL [expr (0x7ff << 16)] ;# PLL Multiplier
set AT91_PMC_USBDIV [expr (3 << 28)] ;# USB Divisor (PLLB only)
set AT91_PMC_USBDIV_1 [expr (0 << 28)]
set AT91_PMC_USBDIV_2 [expr (1 << 28)]
set AT91_PMC_USBDIV_4 [expr (2 << 28)]
set AT91_PMC_USB96M [expr (1 << 28)] ;# Divider by 2 Enable (PLLB only)
set AT91_PMC_PLLA_WR_ERRATA [expr (1 << 29)] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register
set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection
set AT91_PMC_CSS_SLOW [expr (0 << 0)]
set AT91_PMC_CSS_MAIN [expr (1 << 0)]
set AT91_PMC_CSS_PLLA [expr (2 << 0)]
set AT91_PMC_CSS_PLLB [expr (3 << 0)]
set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only]
set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler
set AT91_PMC_PRES_1 [expr (0 << 2)]
set AT91_PMC_PRES_2 [expr (1 << 2)]
set AT91_PMC_PRES_4 [expr (2 << 2)]
set AT91_PMC_PRES_8 [expr (3 << 2)]
set AT91_PMC_PRES_16 [expr (4 << 2)]
set AT91_PMC_PRES_32 [expr (5 << 2)]
set AT91_PMC_PRES_64 [expr (6 << 2)]
set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division
set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only]
set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)]
set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)]
set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)]
set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only]
set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)]
set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)]
set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only]
set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only]
set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only]
set AT91_PMC_PDIV_1 [expr (0 << 12)]
set AT91_PMC_PDIV_2 [expr (1 << 12)]
set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only]
set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)]
set AT91_PMC_PLLADIV2_ON [expr (1 << 12)]
set AT91_PMC_USB [expr ($AT91_PMC + 0x38)] ;# USB Clock Register [some SAM9 only]
set AT91_PMC_USBS [expr (0x1 << 0)] ;# USB OHCI Input clock selection
set AT91_PMC_USBS_PLLA [expr (0 << 0)]
set AT91_PMC_USBS_UPLL [expr (1 << 0)]
set AT91_PMC_OHCIUSBDIV [expr (0xF << 8)] ;# Divider for USB OHCI Clock
;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers
set AT91_PMC_CSSMCK [expr (0x1 << 8)] ;# CSS or Master Clock Selection
set AT91_PMC_CSSMCK_CSS [expr (0 << 8)]
set AT91_PMC_CSSMCK_MCK [expr (1 << 8)]
set AT91_PMC_IER [expr ($AT91_PMC + 0x60)] ;# Interrupt Enable Register
set AT91_PMC_IDR [expr ($AT91_PMC + 0x64)] ;# Interrupt Disable Register
set AT91_PMC_SR [expr ($AT91_PMC + 0x68)] ;# Status Register
set AT91_PMC_MOSCS [expr (1 << 0)] ;# MOSCS Flag
set AT91_PMC_LOCKA [expr (1 << 1)] ;# PLLA Lock
set AT91_PMC_LOCKB [expr (1 << 2)] ;# PLLB Lock
set AT91_PMC_MCKRDY [expr (1 << 3)] ;# Master Clock
set AT91_PMC_LOCKU [expr (1 << 6)] ;# UPLL Lock [some SAM9, AT91CAP9 only]
set AT91_PMC_OSCSEL [expr (1 << 7)] ;# Slow Clock Oscillator [AT91CAP9 revC only]
set AT91_PMC_PCK0RDY [expr (1 << 8)] ;# Programmable Clock 0
set AT91_PMC_PCK1RDY [expr (1 << 9)] ;# Programmable Clock 1
set AT91_PMC_PCK2RDY [expr (1 << 10)] ;# Programmable Clock 2
set AT91_PMC_PCK3RDY [expr (1 << 11)] ;# Programmable Clock 3
set AT91_PMC_IMR [expr ($AT91_PMC + 0x6c)] ;# Interrupt Mask Register
set AT91_PMC_PROT [expr ($AT91_PMC + 0xe4)] ;# Protect Register [AT91CAP9 revC only]
set AT91_PMC_PROTKEY 0x504d4301 ;# Activation Code
set AT91_PMC_VER [expr ($AT91_PMC + 0xfc)] ;# PMC Module Version [AT91CAP9 only]

21
debuggers/openocd/tcl/chip/atmel/at91/at91_rstc.cfg Normal file
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set AT91_RSTC_CR [expr ($AT91_RSTC + 0x00)] ;# Reset Controller Control Register
set AT91_RSTC_PROCRST [expr (1 << 0)] ;# Processor Reset
set AT91_RSTC_PERRST [expr (1 << 2)] ;# Peripheral Reset
set AT91_RSTC_EXTRST [expr (1 << 3)] ;# External Reset
set AT91_RSTC_KEY [expr (0xa5 << 24)] ;# KEY Password
set AT91_RSTC_SR [expr ($AT91_RSTC + 0x04)] ;# Reset Controller Status Register
set AT91_RSTC_URSTS [expr (1 << 0)] ;# User Reset Status
set AT91_RSTC_RSTTYP [expr (7 << 8)] ;# Reset Type
set AT91_RSTC_RSTTYP_GENERAL [expr (0 << 8)]
set AT91_RSTC_RSTTYP_WAKEUP [expr (1 << 8)]
set AT91_RSTC_RSTTYP_WATCHDOG [expr (2 << 8)]
set AT91_RSTC_RSTTYP_SOFTWARE [expr (3 << 8)]
set AT91_RSTC_RSTTYP_USER [expr (4 << 8)]
set AT91_RSTC_NRSTL [expr (1 << 16)] ;# NRST Pin Level
set AT91_RSTC_SRCMP [expr (1 << 17)] ;# Software Reset Command in Progress
set AT91_RSTC_MR [expr ($AT91_RSTC + 0x08)] ;# Reset Controller Mode Register
set AT91_RSTC_URSTEN [expr (1 << 0)] ;# User Reset Enable
set AT91_RSTC_URSTIEN [expr (1 << 4)] ;# User Reset Interrupt Enable
set AT91_RSTC_ERSTL [expr (0xf << 8)] ;# External Reset Length

17
debuggers/openocd/tcl/chip/atmel/at91/at91_wdt.cfg Normal file
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set AT91_WDT_CR [expr ($AT91_WDT + 0x00)] ;# Watchdog Control Register
set AT91_WDT_WDRSTT [expr (1 << 0)] ;# Restart
set AT91_WDT_KEY [expr (0xa5 << 24)] ;# KEY Password
set AT91_WDT_MR [expr ($AT91_WDT + 0x04)] ;# Watchdog Mode Register
set AT91_WDT_WDV [expr (0xfff << 0)] ;# Counter Value
set AT91_WDT_WDFIEN [expr (1 << 12)] ;# Fault Interrupt Enable
set AT91_WDT_WDRSTEN [expr (1 << 13)] ;# Reset Processor
set AT91_WDT_WDRPROC [expr (1 << 14)] ;# Timer Restart
set AT91_WDT_WDDIS [expr (1 << 15)] ;# Watchdog Disable
set AT91_WDT_WDD [expr (0xfff << 16)] ;# Delta Value
set AT91_WDT_WDDBGHLT [expr (1 << 28)] ;# Debug Halt
set AT91_WDT_WDIDLEHLT [expr (1 << 29)] ;# Idle Halt
set AT91_WDT_SR [expr ($AT91_WDT + 0x08)] ;# Watchdog Status Register
set AT91_WDT_WDUNF [expr (1 << 0)] ;# Watchdog Underflow
set AT91_WDT_WDERR [expr (1 << 1)] ;# Watchdog Error

128
debuggers/openocd/tcl/chip/atmel/at91/at91sam7x128.tcl Normal file
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source [find bitsbytes.tcl]
source [find cpu/arm/arm7tdmi.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
set CHIP_MAKER atmel
set CHIP_FAMILY at91sam7
set CHIP_NAME at91sam7x128
# how many flash regions.
set N_FLASH 1
set FLASH(0,CHIPSELECT) -1
set FLASH(0,BASE) 0x00100000
set FLASH(0,LEN) $__128K
set FLASH(0,HUMAN) "internal flash"
set FLASH(0,TYPE) "flash"
set FLASH(0,RWX) $RWX_R_X
set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
# how many ram regions.
set N_RAM 1
set RAM(0,CHIPSELECT) -1
set RAM(0,BASE) 0x00200000
set RAM(0,LEN) $__32K
set RAM(0,HUMAN) "internal ram"
set RAM(0,TYPE) "ram"
set RAM(0,RWX) $RWX_RWX
set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
# I AM LAZY... I create 1 region for all MMRs.
set N_MMREGS 1
set MMREGS(0,CHIPSELECT) -1
set MMREGS(0,BASE) 0xfff00000
set MMREGS(0,LEN) 0x000fffff
set MMREGS(0,HUMAN) "mm-regs"
set MMREGS(0,TYPE) "mmr"
set MMREGS(0,RWX) $RWX_RW
set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
# no external memory
set N_XMEM 0
set AT91C_BASE_SYS 0xFFFFF000
set AT91C_BASE_AIC 0xFFFFF000
set AT91C_BASE_PDC_DBGU 0xFFFFF300
set AT91C_BASE_DBGU 0xFFFFF200
set AT91C_BASE_PIOA 0xFFFFF400
set AT91C_BASE_PIOB 0xFFFFF600
set AT91C_BASE_CKGR 0xFFFFFC20
set AT91C_BASE_PMC 0xFFFFFC00
set AT91C_BASE_RSTC 0xFFFFFD00
set AT91C_BASE_RTTC 0xFFFFFD20
set AT91C_BASE_PITC 0xFFFFFD30
set AT91C_BASE_WDTC 0xFFFFFD40
set AT91C_BASE_VREG 0xFFFFFD60
set AT91C_BASE_MC 0xFFFFFF00
set AT91C_BASE_PDC_SPI1 0xFFFE4100
set AT91C_BASE_SPI1 0xFFFE4000
set AT91C_BASE_PDC_SPI0 0xFFFE0100
set AT91C_BASE_SPI0 0xFFFE0000
set AT91C_BASE_PDC_US1 0xFFFC4100
set AT91C_BASE_US1 0xFFFC4000
set AT91C_BASE_PDC_US0 0xFFFC0100
set AT91C_BASE_US0 0xFFFC0000
set AT91C_BASE_PDC_SSC 0xFFFD4100
set AT91C_BASE_SSC 0xFFFD4000
set AT91C_BASE_TWI 0xFFFB8000
set AT91C_BASE_PWMC_CH3 0xFFFCC260
set AT91C_BASE_PWMC_CH2 0xFFFCC240
set AT91C_BASE_PWMC_CH1 0xFFFCC220
set AT91C_BASE_PWMC_CH0 0xFFFCC200
set AT91C_BASE_PWMC 0xFFFCC000
set AT91C_BASE_UDP 0xFFFB0000
set AT91C_BASE_TC0 0xFFFA0000
set AT91C_BASE_TC1 0xFFFA0040
set AT91C_BASE_TC2 0xFFFA0080
set AT91C_BASE_TCB 0xFFFA0000
set AT91C_BASE_CAN_MB0 0xFFFD0200
set AT91C_BASE_CAN_MB1 0xFFFD0220
set AT91C_BASE_CAN_MB2 0xFFFD0240
set AT91C_BASE_CAN_MB3 0xFFFD0260
set AT91C_BASE_CAN_MB4 0xFFFD0280
set AT91C_BASE_CAN_MB5 0xFFFD02A0
set AT91C_BASE_CAN_MB6 0xFFFD02C0
set AT91C_BASE_CAN_MB7 0xFFFD02E0
set AT91C_BASE_CAN 0xFFFD0000
set AT91C_BASE_EMAC 0xFFFDC000
set AT91C_BASE_PDC_ADC 0xFFFD8100
set AT91C_BASE_ADC 0xFFFD8000
set AT91C_ID(0) FIQ
set AT91C_ID(1) SYS
set AT91C_ID(2) PIOA
set AT91C_ID(3) PIOB
set AT91C_ID(4) SPI0
set AT91C_ID(5) SPI1
set AT91C_ID(6) US0
set AT91C_ID(7) US1
set AT91C_ID(8) SSC
set AT91C_ID(9) TWI
set AT91C_ID(10) PWMC
set AT91C_ID(11) UDP
set AT91C_ID(12) TC0
set AT91C_ID(13) TC1
set AT91C_ID(14) TC2
set AT91C_ID(15) CAN
set AT91C_ID(16) EMAC
set AT91C_ID(17) ADC
set AT91C_ID(18) ""
set AT91C_ID(19) ""
set AT91C_ID(20) ""
set AT91C_ID(21) ""
set AT91C_ID(22) ""
set AT91C_ID(23) ""
set AT91C_ID(24) ""
set AT91C_ID(25) ""
set AT91C_ID(26) ""
set AT91C_ID(27) ""
set AT91C_ID(28) ""
set AT91C_ID(29) ""
set AT91C_ID(30) IRQ0
set AT91C_ID(31) IRQ1
source [find chip/atmel/at91/aic.tcl]
source [find chip/atmel/at91/usarts.tcl]
source [find chip/atmel/at91/pmc.tcl]
source [find chip/atmel/at91/rtt.tcl]

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debuggers/openocd/tcl/chip/atmel/at91/at91sam7x256.tcl Normal file
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source [find bitsbytes.tcl]
source [find cpu/arm/arm7tdmi.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
set CHIP_MAKER atmel
set CHIP_FAMILY at91sam7
set CHIP_NAME at91sam7x256
# how many flash regions.
set N_FLASH 1
set FLASH(0,CHIPSELECT) -1
set FLASH(0,BASE) 0x00100000
set FLASH(0,LEN) $__256K
set FLASH(0,HUMAN) "internal flash"
set FLASH(0,TYPE) "flash"
set FLASH(0,RWX) $RWX_R_X
set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
# how many ram regions.
set N_RAM 1
set RAM(0,CHIPSELECT) -1
set RAM(0,BASE) 0x00200000
set RAM(0,LEN) $__64K
set RAM(0,HUMAN) "internal ram"
set RAM(0,TYPE) "ram"
set RAM(0,RWX) $RWX_RWX
set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
# I AM LAZY... I create 1 region for all MMRs.
set N_MMREGS 1
set MMREGS(0,CHIPSELECT) -1
set MMREGS(0,BASE) 0xfff00000
set MMREGS(0,LEN) 0x000fffff
set MMREGS(0,HUMAN) "mm-regs"
set MMREGS(0,TYPE) "mmr"
set MMREGS(0,RWX) $RWX_RW
set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
# no external memory
set N_XMEM 0
set AT91C_BASE_SYS 0xFFFFF000
set AT91C_BASE_AIC 0xFFFFF000
set AT91C_BASE_PDC_DBGU 0xFFFFF300
set AT91C_BASE_DBGU 0xFFFFF200
set AT91C_BASE_PIOA 0xFFFFF400
set AT91C_BASE_PIOB 0xFFFFF600
set AT91C_BASE_CKGR 0xFFFFFC20
set AT91C_BASE_PMC 0xFFFFFC00
set AT91C_BASE_RSTC 0xFFFFFD00
set AT91C_BASE_RTTC 0xFFFFFD20
set AT91C_BASE_PITC 0xFFFFFD30
set AT91C_BASE_WDTC 0xFFFFFD40
set AT91C_BASE_VREG 0xFFFFFD60
set AT91C_BASE_MC 0xFFFFFF00
set AT91C_BASE_PDC_SPI1 0xFFFE4100
set AT91C_BASE_SPI1 0xFFFE4000
set AT91C_BASE_PDC_SPI0 0xFFFE0100
set AT91C_BASE_SPI0 0xFFFE0000
set AT91C_BASE_PDC_US1 0xFFFC4100
set AT91C_BASE_US1 0xFFFC4000
set AT91C_BASE_PDC_US0 0xFFFC0100
set AT91C_BASE_US0 0xFFFC0000
set AT91C_BASE_PDC_SSC 0xFFFD4100
set AT91C_BASE_SSC 0xFFFD4000
set AT91C_BASE_TWI 0xFFFB8000
set AT91C_BASE_PWMC_CH3 0xFFFCC260
set AT91C_BASE_PWMC_CH2 0xFFFCC240
set AT91C_BASE_PWMC_CH1 0xFFFCC220
set AT91C_BASE_PWMC_CH0 0xFFFCC200
set AT91C_BASE_PWMC 0xFFFCC000
set AT91C_BASE_UDP 0xFFFB0000
set AT91C_BASE_TC0 0xFFFA0000
set AT91C_BASE_TC1 0xFFFA0040
set AT91C_BASE_TC2 0xFFFA0080
set AT91C_BASE_TCB 0xFFFA0000
set AT91C_BASE_CAN_MB0 0xFFFD0200
set AT91C_BASE_CAN_MB1 0xFFFD0220
set AT91C_BASE_CAN_MB2 0xFFFD0240
set AT91C_BASE_CAN_MB3 0xFFFD0260
set AT91C_BASE_CAN_MB4 0xFFFD0280
set AT91C_BASE_CAN_MB5 0xFFFD02A0
set AT91C_BASE_CAN_MB6 0xFFFD02C0
set AT91C_BASE_CAN_MB7 0xFFFD02E0
set AT91C_BASE_CAN 0xFFFD0000
set AT91C_BASE_EMAC 0xFFFDC000
set AT91C_BASE_PDC_ADC 0xFFFD8100
set AT91C_BASE_ADC 0xFFFD8000
set AT91C_ID(0) "FIQ"
set AT91C_ID(1) "SYS"
set AT91C_ID(2) "PIOA"
set AT91C_ID(3) "PIOB"
set AT91C_ID(4) "SPI0"
set AT91C_ID(5) "SPI1"
set AT91C_ID(6) "US0"
set AT91C_ID(7) "US1"
set AT91C_ID(8) "SSC"
set AT91C_ID(9) "TWI"
set AT91C_ID(10) "PWMC"
set AT91C_ID(11) "UDP"
set AT91C_ID(12) "TC0"
set AT91C_ID(13) "TC1"
set AT91C_ID(14) "TC2"
set AT91C_ID(15) "CAN"
set AT91C_ID(16) "EMAC"
set AT91C_ID(17) "ADC"
set AT91C_ID(18) ""
set AT91C_ID(19) ""
set AT91C_ID(20) ""
set AT91C_ID(21) ""
set AT91C_ID(22) ""
set AT91C_ID(23) ""
set AT91C_ID(24) ""
set AT91C_ID(25) ""
set AT91C_ID(26) ""
set AT91C_ID(27) ""
set AT91C_ID(28) ""
set AT91C_ID(29) ""
set AT91C_ID(30) "IRQ0"
set AT91C_ID(31) "IRQ1"
source [find chip/atmel/at91/aic.tcl]
source [find chip/atmel/at91/usarts.tcl]
source [find chip/atmel/at91/pmc.tcl]
source [find chip/atmel/at91/rtt.tcl]

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#
# Peripheral identifiers/interrupts.
#
set AT91_ID_FIQ 0 ;# Advanced Interrupt Controller (FIQ)
set AT91_ID_SYS 1 ;# System Peripherals
set AT91SAM9261_ID_PIOA 2 ;# Parallel IO Controller A
set AT91SAM9261_ID_PIOB 3 ;# Parallel IO Controller B
set AT91SAM9261_ID_PIOC 4 ;# Parallel IO Controller C
set AT91SAM9261_ID_US0 6 ;# USART 0
set AT91SAM9261_ID_US1 7 ;# USART 1
set AT91SAM9261_ID_US2 8 ;# USART 2
set AT91SAM9261_ID_MCI 9 ;# Multimedia Card Interface
set AT91SAM9261_ID_UDP 10 ;# USB Device Port
set AT91SAM9261_ID_TWI 11 ;# Two-Wire Interface
set AT91SAM9261_ID_SPI0 12 ;# Serial Peripheral Interface 0
set AT91SAM9261_ID_SPI1 13 ;# Serial Peripheral Interface 1
set AT91SAM9261_ID_SSC0 14 ;# Serial Synchronous Controller 0
set AT91SAM9261_ID_SSC1 15 ;# Serial Synchronous Controller 1
set AT91SAM9261_ID_SSC2 16 ;# Serial Synchronous Controller 2
set AT91SAM9261_ID_TC0 17 ;# Timer Counter 0
set AT91SAM9261_ID_TC1 18 ;# Timer Counter 1
set AT91SAM9261_ID_TC2 19 ;# Timer Counter 2
set AT91SAM9261_ID_UHP 20 ;# USB Host port
set AT91SAM9261_ID_LCDC 21 ;# LDC Controller
set AT91SAM9261_ID_IRQ0 29 ;# Advanced Interrupt Controller (IRQ0)
set AT91SAM9261_ID_IRQ1 30 ;# Advanced Interrupt Controller (IRQ1)
set AT91SAM9261_ID_IRQ2 31 ;# Advanced Interrupt Controller (IRQ2)
#
# User Peripheral physical base addresses.
#
set AT91SAM9261_BASE_TCB0 0xfffa0000
set AT91SAM9261_BASE_TC0 0xfffa0000
set AT91SAM9261_BASE_TC1 0xfffa0040
set AT91SAM9261_BASE_TC2 0xfffa0080
set AT91SAM9261_BASE_UDP 0xfffa4000
set AT91SAM9261_BASE_MCI 0xfffa8000
set AT91SAM9261_BASE_TWI 0xfffac000
set AT91SAM9261_BASE_US0 0xfffb0000
set AT91SAM9261_BASE_US1 0xfffb4000
set AT91SAM9261_BASE_US2 0xfffb8000
set AT91SAM9261_BASE_SSC0 0xfffbc000
set AT91SAM9261_BASE_SSC1 0xfffc0000
set AT91SAM9261_BASE_SSC2 0xfffc4000
set AT91SAM9261_BASE_SPI0 0xfffc8000
set AT91SAM9261_BASE_SPI1 0xfffcc000
set AT91_BASE_SYS 0xffffea00
#
# System Peripherals (offset from AT91_BASE_SYS)
#
set AT91_SDRAMC 0xffffea00
set AT91_SMC 0xffffec00
set AT91_MATRIX 0xffffee00
set AT91_AIC 0xfffff000
set AT91_DBGU 0xfffff200
set AT91_PIOA 0xfffff400
set AT91_PIOB 0xfffff600
set AT91_PIOC 0xfffff800
set AT91_PMC 0xfffffc00
set AT91_RSTC 0xfffffd00
set AT91_SHDWC 0xfffffd10
set AT91_RTT 0xfffffd20
set AT91_PIT 0xfffffd30
set AT91_WDT 0xfffffd40
set AT91_GPBR 0xfffffd50
set AT91_USART0 $AT91SAM9261_BASE_US0
set AT91_USART1 $AT91SAM9261_BASE_US1
set AT91_USART2 $AT91SAM9261_BASE_US2
#
# Internal Memory.
#
set AT91SAM9261_SRAM_BASE 0x00300000 ;# Internal SRAM base address
set AT91SAM9261_SRAM_SIZE 0x00028000 ;# Internal SRAM size (160Kb)
set AT91SAM9261_ROM_BASE 0x00400000 ;# Internal ROM base address
set AT91SAM9261_ROM_SIZE 0x00008000 ;# Internal ROM size (32Kb)
set AT91SAM9261_UHP_BASE 0x00500000 ;# USB Host controller
set AT91SAM9261_LCDC_BASE 0x00600000 ;# LDC controller
#
# Cpu Name
#
set AT91_CPU_NAME "AT91SAM9261"

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set AT91_MATRIX_MCFG [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register #
set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x04)] ;# Slave Configuration Register 0
set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x08)] ;# Slave Configuration Register 1
set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x0C)] ;# Slave Configuration Register 2
set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x10)] ;# Slave Configuration Register 3
set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x14)] ;# Slave Configuration Register 4
set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst
set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type
set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)]
set AT91_MATRIX_FIXED_DEFMSTR [expr (7 << 18)] ;# Fixed Index of Default Master
set AT91_MATRIX_TCR [expr ($AT91_MATRIX + 0x24)] ;# TCM Configuration Register
set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block
set AT91_MATRIX_ITCM_0 [expr (0 << 0)]
set AT91_MATRIX_ITCM_16 [expr (5 << 0)]
set AT91_MATRIX_ITCM_32 [expr (6 << 0)]
set AT91_MATRIX_ITCM_64 [expr (7 << 0)]
set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block
set AT91_MATRIX_DTCM_0 [expr (0 << 4)]
set AT91_MATRIX_DTCM_16 [expr (5 << 4)]
set AT91_MATRIX_DTCM_32 [expr (6 << 4)]
set AT91_MATRIX_DTCM_64 [expr (7 << 4)]
set AT91_MATRIX_EBICSA [expr ($AT91_MATRIX + 0x30)] ;# EBI Chip Select Assignment Register
set AT91_MATRIX_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
set AT91_MATRIX_CS1A_SMC [expr (0 << 1)]
set AT91_MATRIX_CS1A_SDRAMC [expr (1 << 1)]
set AT91_MATRIX_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignment
set AT91_MATRIX_CS3A_SMC [expr (0 << 3)]
set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr (1 << 3)]
set AT91_MATRIX_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment
set AT91_MATRIX_CS4A_SMC [expr (0 << 4)]
set AT91_MATRIX_CS4A_SMC_CF1 [expr (1 << 4)]
set AT91_MATRIX_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment
set AT91_MATRIX_CS5A_SMC [expr (0 << 5)]
set AT91_MATRIX_CS5A_SMC_CF2 [expr (1 << 5)]
set AT91_MATRIX_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_USBPUCR [expr ($AT91_MATRIX + 0x34)] ;# USB Pad Pull-Up Control Register
set AT91_MATRIX_USBPUCR_PUON [expr (1 << 30)] ;# USB Device PAD Pull-up Enable

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#
# Peripheral identifiers/interrupts.
#
set AT91_ID_FIQ 0 ;# Advanced Interrupt Controller (FIQ)
set AT91_ID_SYS 1 ;# System Peripherals
set AT91SAM9263_ID_PIOA 2 ;# Parallel IO Controller A
set AT91SAM9263_ID_PIOB 3 ;# Parallel IO Controller B
set AT91SAM9263_ID_PIOCDE 4 ;# Parallel IO Controller C, D and E
set AT91SAM9263_ID_US0 7 ;# USART 0
set AT91SAM9263_ID_US1 8 ;# USART 1
set AT91SAM9263_ID_US2 9 ;# USART 2
set AT91SAM9263_ID_MCI0 10 ;# Multimedia Card Interface 0
set AT91SAM9263_ID_MCI1 11 ;# Multimedia Card Interface 1
set AT91SAM9263_ID_CAN 12 ;# CAN
set AT91SAM9263_ID_TWI 13 ;# Two-Wire Interface
set AT91SAM9263_ID_SPI0 14 ;# Serial Peripheral Interface 0
set AT91SAM9263_ID_SPI1 15 ;# Serial Peripheral Interface 1
set AT91SAM9263_ID_SSC0 16 ;# Serial Synchronous Controller 0
set AT91SAM9263_ID_SSC1 17 ;# Serial Synchronous Controller 1
set AT91SAM9263_ID_AC97C 18 ;# AC97 Controller
set AT91SAM9263_ID_TCB 19 ;# Timer Counter 0, 1 and 2
set AT91SAM9263_ID_PWMC 20 ;# Pulse Width Modulation Controller
set AT91SAM9263_ID_EMAC 21 ;# Ethernet
set AT91SAM9263_ID_2DGE 23 ;# 2D Graphic Engine
set AT91SAM9263_ID_UDP 24 ;# USB Device Port
set AT91SAM9263_ID_ISI 25 ;# Image Sensor Interface
set AT91SAM9263_ID_LCDC 26 ;# LCD Controller
set AT91SAM9263_ID_DMA 27 ;# DMA Controller
set AT91SAM9263_ID_UHP 29 ;# USB Host port
set AT91SAM9263_ID_IRQ0 30 ;# Advanced Interrupt Controller (IRQ0)
set AT91SAM9263_ID_IRQ1 31 ;# Advanced Interrupt Controller (IRQ1)
#
# User Peripheral physical base addresses.
#
set AT91SAM9263_BASE_UDP 0xfff78000
set AT91SAM9263_BASE_TCB0 0xfff7c000
set AT91SAM9263_BASE_TC0 0xfff7c000
set AT91SAM9263_BASE_TC1 0xfff7c040
set AT91SAM9263_BASE_TC2 0xfff7c080
set AT91SAM9263_BASE_MCI0 0xfff80000
set AT91SAM9263_BASE_MCI1 0xfff84000
set AT91SAM9263_BASE_TWI 0xfff88000
set AT91SAM9263_BASE_US0 0xfff8c000
set AT91SAM9263_BASE_US1 0xfff90000
set AT91SAM9263_BASE_US2 0xfff94000
set AT91SAM9263_BASE_SSC0 0xfff98000
set AT91SAM9263_BASE_SSC1 0xfff9c000
set AT91SAM9263_BASE_AC97C 0xfffa0000
set AT91SAM9263_BASE_SPI0 0xfffa4000
set AT91SAM9263_BASE_SPI1 0xfffa8000
set AT91SAM9263_BASE_CAN 0xfffac000
set AT91SAM9263_BASE_PWMC 0xfffb8000
set AT91SAM9263_BASE_EMAC 0xfffbc000
set AT91SAM9263_BASE_ISI 0xfffc4000
set AT91SAM9263_BASE_2DGE 0xfffc8000
set AT91_BASE_SYS 0xffffe000
#
# System Peripherals (offset from AT91_BASE_SYS)
#
set AT91_ECC0 0xffffe000
set AT91_SDRAMC0 0xffffe200
set AT91_SMC0 0xffffe400
set AT91_ECC1 0xffffe600
set AT91_SDRAMC1 0xffffe800
set AT91_SMC1 0xffffea00
set AT91_MATRIX 0xffffec00
set AT91_CCFG 0xffffed10
set AT91_DBGU 0xffffee00
set AT91_AIC 0xfffff000
set AT91_PIOA 0xfffff200
set AT91_PIOB 0xfffff400
set AT91_PIOC 0xfffff600
set AT91_PIOD 0xfffff800
set AT91_PIOE 0xfffffa00
set AT91_PMC 0xfffffc00
set AT91_RSTC 0xfffffd00
set AT91_SHDWC 0xfffffd10
set AT91_RTT0 0xfffffd20
set AT91_PIT 0xfffffd30
set AT91_WDT 0xfffffd40
set AT91_RTT1 0xfffffd50
set AT91_GPBR 0xfffffd60
set AT91_USART0 $AT91SAM9263_BASE_US0
set AT91_USART1 $AT91SAM9263_BASE_US1
set AT91_USART2 $AT91SAM9263_BASE_US2
set AT91_SMC $AT91_SMC0
set AT91_SDRAMC $AT91_SDRAMC0
#
# Internal Memory.
#
set AT91SAM9263_SRAM0_BASE 0x00300000 ;# Internal SRAM 0 base address
set AT91SAM9263_SRAM0_SIZE 0x00014000 ;# Internal SRAM 0 size (80Kb)
set AT91SAM9263_ROM_BASE 0x00400000 ;# Internal ROM base address
set AT91SAM9263_ROM_SIZE 0x00020000 ;# Internal ROM size (128Kb)
set AT91SAM9263_SRAM1_BASE 0x00500000 ;# Internal SRAM 1 base address
set AT91SAM9263_SRAM1_SIZE 0x00004000 ;# Internal SRAM 1 size (16Kb)
set AT91SAM9263_LCDC_BASE 0x00700000 ;# LCD Controller
set AT91SAM9263_DMAC_BASE 0x00800000 ;# DMA Controller
set AT91SAM9263_UHP_BASE 0x00a00000 ;# USB Host controller
#
# Cpu Name
#
set AT91_CPU_NAME "AT91SAM9263"

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set AT91_MATRIX_MCFG0 [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register 0
set AT91_MATRIX_MCFG1 [expr ($AT91_MATRIX + 0x04)] ;# Master Configuration Register 1
set AT91_MATRIX_MCFG2 [expr ($AT91_MATRIX + 0x08)] ;# Master Configuration Register 2
set AT91_MATRIX_MCFG3 [expr ($AT91_MATRIX + 0x0C)] ;# Master Configuration Register 3
set AT91_MATRIX_MCFG4 [expr ($AT91_MATRIX + 0x10)] ;# Master Configuration Register 4
set AT91_MATRIX_MCFG5 [expr ($AT91_MATRIX + 0x14)] ;# Master Configuration Register 5
set AT91_MATRIX_MCFG6 [expr ($AT91_MATRIX + 0x18)] ;# Master Configuration Register 6
set AT91_MATRIX_MCFG7 [expr ($AT91_MATRIX + 0x1C)] ;# Master Configuration Register 7
set AT91_MATRIX_MCFG8 [expr ($AT91_MATRIX + 0x20)] ;# Master Configuration Register 8
set AT91_MATRIX_ULBT [expr (7 << 0)] ;# Undefined Length Burst Type
set AT91_MATRIX_ULBT_INFINITE [expr (0 << 0)]
set AT91_MATRIX_ULBT_SINGLE [expr (1 << 0)]
set AT91_MATRIX_ULBT_FOUR [expr (2 << 0)]
set AT91_MATRIX_ULBT_EIGHT [expr (3 << 0)]
set AT91_MATRIX_ULBT_SIXTEEN [expr (4 << 0)]
set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x40)] ;# Slave Configuration Register 0
set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x44)] ;# Slave Configuration Register 1
set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x48)] ;# Slave Configuration Register 2
set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x4C)] ;# Slave Configuration Register 3
set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x50)] ;# Slave Configuration Register 4
set AT91_MATRIX_SCFG5 [expr ($AT91_MATRIX + 0x54)] ;# Slave Configuration Register 5
set AT91_MATRIX_SCFG6 [expr ($AT91_MATRIX + 0x58)] ;# Slave Configuration Register 6
set AT91_MATRIX_SCFG7 [expr ($AT91_MATRIX + 0x5C)] ;# Slave Configuration Register 7
set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst
set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type
set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)]
set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)]
set AT91_MATRIX_FIXED_DEFMSTR [expr (0xf << 18)] ;# Fixed Index of Default Master
set AT91_MATRIX_ARBT [expr (3 << 24)] ;# Arbitration Type
set AT91_MATRIX_ARBT_ROUND_ROBIN [expr (0 << 24)]
set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr (1 << 24)]
set AT91_MATRIX_PRAS0 [expr ($AT91_MATRIX + 0x80)] ;# Priority Register A for Slave 0
set AT91_MATRIX_PRBS0 [expr ($AT91_MATRIX + 0x84)] ;# Priority Register B for Slave 0
set AT91_MATRIX_PRAS1 [expr ($AT91_MATRIX + 0x88)] ;# Priority Register A for Slave 1
set AT91_MATRIX_PRBS1 [expr ($AT91_MATRIX + 0x8C)] ;# Priority Register B for Slave 1
set AT91_MATRIX_PRAS2 [expr ($AT91_MATRIX + 0x90)] ;# Priority Register A for Slave 2
set AT91_MATRIX_PRBS2 [expr ($AT91_MATRIX + 0x94)] ;# Priority Register B for Slave 2
set AT91_MATRIX_PRAS3 [expr ($AT91_MATRIX + 0x98)] ;# Priority Register A for Slave 3
set AT91_MATRIX_PRBS3 [expr ($AT91_MATRIX + 0x9C)] ;# Priority Register B for Slave 3
set AT91_MATRIX_PRAS4 [expr ($AT91_MATRIX + 0xA0)] ;# Priority Register A for Slave 4
set AT91_MATRIX_PRBS4 [expr ($AT91_MATRIX + 0xA4)] ;# Priority Register B for Slave 4
set AT91_MATRIX_PRAS5 [expr ($AT91_MATRIX + 0xA8)] ;# Priority Register A for Slave 5
set AT91_MATRIX_PRBS5 [expr ($AT91_MATRIX + 0xAC)] ;# Priority Register B for Slave 5
set AT91_MATRIX_PRAS6 [expr ($AT91_MATRIX + 0xB0)] ;# Priority Register A for Slave 6
set AT91_MATRIX_PRBS6 [expr ($AT91_MATRIX + 0xB4)] ;# Priority Register B for Slave 6
set AT91_MATRIX_PRAS7 [expr ($AT91_MATRIX + 0xB8)] ;# Priority Register A for Slave 7
set AT91_MATRIX_PRBS7 [expr ($AT91_MATRIX + 0xBC)] ;# Priority Register B for Slave 7
set AT91_MATRIX_M0PR [expr (3 << 0)] ;# Master 0 Priority
set AT91_MATRIX_M1PR [expr (3 << 4)] ;# Master 1 Priority
set AT91_MATRIX_M2PR [expr (3 << 8)] ;# Master 2 Priority
set AT91_MATRIX_M3PR [expr (3 << 12)] ;# Master 3 Priority
set AT91_MATRIX_M4PR [expr (3 << 16)] ;# Master 4 Priority
set AT91_MATRIX_M5PR [expr (3 << 20)] ;# Master 5 Priority
set AT91_MATRIX_M6PR [expr (3 << 24)] ;# Master 6 Priority
set AT91_MATRIX_M7PR [expr (3 << 28)] ;# Master 7 Priority
set AT91_MATRIX_M8PR [expr (3 << 0)] ;# Master 8 Priority (in Register B)
set AT91_MATRIX_MRCR [expr ($AT91_MATRIX + 0x100)] ;# Master Remap Control Register
set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
set AT91_MATRIX_RCB2 [expr (1 << 2)]
set AT91_MATRIX_RCB3 [expr (1 << 3)]
set AT91_MATRIX_RCB4 [expr (1 << 4)]
set AT91_MATRIX_RCB5 [expr (1 << 5)]
set AT91_MATRIX_RCB6 [expr (1 << 6)]
set AT91_MATRIX_RCB7 [expr (1 << 7)]
set AT91_MATRIX_RCB8 [expr (1 << 8)]
set AT91_MATRIX_TCMR [expr ($AT91_MATRIX + 0x114)] ;# TCM Configuration Register
set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block
set AT91_MATRIX_ITCM_0 [expr (0 << 0)]
set AT91_MATRIX_ITCM_16 [expr (5 << 0)]
set AT91_MATRIX_ITCM_32 [expr (6 << 0)]
set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block
set AT91_MATRIX_DTCM_0 [expr (0 << 4)]
set AT91_MATRIX_DTCM_16 [expr (5 << 4)]
set AT91_MATRIX_DTCM_32 [expr (6 << 4)]
set AT91_MATRIX_EBI0CSA [expr ($AT91_MATRIX + 0x120)] ;# EBI0 Chip Select Assignment Register
set AT91_MATRIX_EBI0_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
set AT91_MATRIX_EBI0_CS1A_SMC [expr (0 << 1)]
set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr (1 << 1)]
set AT91_MATRIX_EBI0_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignmen
set AT91_MATRIX_EBI0_CS3A_SMC [expr (0 << 3)]
set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr (1 << 3)]
set AT91_MATRIX_EBI0_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment
set AT91_MATRIX_EBI0_CS4A_SMC [expr (0 << 4)]
set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr (1 << 4)]
set AT91_MATRIX_EBI0_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment
set AT91_MATRIX_EBI0_CS5A_SMC [expr (0 << 5)]
set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr (1 << 5)]
set AT91_MATRIX_EBI0_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBI0_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr (0 << 16)]
set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr (1 << 16)]
set AT91_MATRIX_EBI1CSA [expr ($AT91_MATRIX + 0x124)] ;# EBI1 Chip Select Assignment Register
set AT91_MATRIX_EBI1_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
set AT91_MATRIX_EBI1_CS1A_SMC [expr (0 << 1)]
set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr (1 << 1)]
set AT91_MATRIX_EBI1_CS2A [expr (1 << 3)] ;# Chip Select 3 Assignment
set AT91_MATRIX_EBI1_CS2A_SMC [expr (0 << 3)]
set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr (1 << 3)]
set AT91_MATRIX_EBI1_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
set AT91_MATRIX_EBI1_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr (0 << 16)]
set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr (1 << 16)]

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uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
proc at91sam9_reset_start { } {
arm7_9 fast_memory_access disable
jtag_rclk 8
halt
wait_halt 10000
set rstc_mr_val [expr $::AT91_RSTC_KEY]
set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
}
proc at91sam9_reset_init { config } {
mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)]
set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
set pllar_val [expr ($pllar_val | $config(master_pll_div))]
mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
;# PCK/2 = MCK Master Clock from PLLA
set mckr_val [expr $::AT91_PMC_CSS_PLLA]
set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)]
set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)]
mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
## switch JTAG clock to highseepd clock
jtag_rclk 0
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
arm7_9 fast_memory_access enable
set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
if { [info exists config(sdram_piod)] } {
set pdr_addr [expr ($::AT91_PIOD + $::PIO_PDR)]
set pudr_addr [expr ($::AT91_PIOD + $::PIO_PUDR)]
set asr_addr [expr ($::AT91_PIOD + $::PIO_ASR)]
mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
mww $asr_addr 0xffff0000
} else {
set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
}
mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register
mww $::AT91_SDRAMC_TR $config(sdram_tr_val) ;# SDRAMC_TR - Refresh Timer register
mww $::AT91_SDRAMC_CR $config(sdram_cr_val) ;# SDRAMC_CR - Configuration register
mww $::AT91_SDRAMC_MDR $::AT91_SDRAMC_MD_SDRAM ;# Memory Device Register -> SDRAM
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_PRECHARGE ;# SDRAMC_MR
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_REFRESH ;# SDRC_MR
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_LMR ;# SDRC_MR
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRC_MR
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $::AT91_SDRAMC_TR 1200 ;# SDRAM_TR
mww $config(sdram_base) 0 ;# SDRAM_BASE
mww $::AT91_MATRIX 0xf ;# MATRIX_MCFG - REMAP all masters
}

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# SDRAM Controller (SDRAMC) registers
set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register
set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode
set AT91_SDRAMC_MODE_NORMAL 0
set AT91_SDRAMC_MODE_NOP 1
set AT91_SDRAMC_MODE_PRECHARGE 2
set AT91_SDRAMC_MODE_LMR 3
set AT91_SDRAMC_MODE_REFRESH 4
set AT91_SDRAMC_MODE_EXT_LMR 5
set AT91_SDRAMC_MODE_DEEP 6
set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register
set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter
set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register
set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits
set AT91_SDRAMC_NC_8 [expr (0 << 0)]
set AT91_SDRAMC_NC_9 [expr (1 << 0)]
set AT91_SDRAMC_NC_10 [expr (2 << 0)]
set AT91_SDRAMC_NC_11 [expr (3 << 0)]
set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits
set AT91_SDRAMC_NR_11 [expr (0 << 2)]
set AT91_SDRAMC_NR_12 [expr (1 << 2)]
set AT91_SDRAMC_NR_13 [expr (2 << 2)]
set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks
set AT91_SDRAMC_NB_2 [expr (0 << 4)]
set AT91_SDRAMC_NB_4 [expr (1 << 4)]
set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency
set AT91_SDRAMC_CAS_1 [expr (1 << 5)]
set AT91_SDRAMC_CAS_2 [expr (2 << 5)]
set AT91_SDRAMC_CAS_3 [expr (3 << 5)]
set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width
set AT91_SDRAMC_DBW_32 [expr (0 << 7)]
set AT91_SDRAMC_DBW_16 [expr (1 << 7)]
set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay
set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay
set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay
set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay
set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay
set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay
set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register
set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations
set AT91_SDRAMC_LPCB_DISABLE 0
set AT91_SDRAMC_LPCB_SELF_REFRESH 1
set AT91_SDRAMC_LPCB_POWER_DOWN 2
set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh
set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh
set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength
set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled
set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)]
set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)]
set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)]
set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register
set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register
set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register
set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register
set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status
set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register
set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type
set AT91_SDRAMC_MD_SDRAM 0
set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1

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debuggers/openocd/tcl/chip/atmel/at91/at91sam9_smc.cfg Normal file
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set AT91_SMC_READMODE [expr (1 << 0)] ;# Read Mode
set AT91_SMC_WRITEMODE [expr (1 << 1)] ;# Write Mode
set AT91_SMC_EXNWMODE [expr (3 << 4)] ;# NWAIT Mode
set AT91_SMC_EXNWMODE_DISABLE [expr (0 << 4)]
set AT91_SMC_EXNWMODE_FROZEN [expr (2 << 4)]
set AT91_SMC_EXNWMODE_READY [expr (3 << 4)]
set AT91_SMC_BAT [expr (1 << 8)] ;# Byte Access Type
set AT91_SMC_BAT_SELECT [expr (0 << 8)]
set AT91_SMC_BAT_WRITE [expr (1 << 8)]
set AT91_SMC_DBW [expr (3 << 12)] ;# Data Bus Width */
set AT91_SMC_DBW_8 [expr (0 << 12)]
set AT91_SMC_DBW_16 [expr (1 << 12)]
set AT91_SMC_DBW_32 [expr (2 << 12)]
set AT91_SMC_TDFMODE [expr (1 << 20)] ;# TDF Optimization - Enabled
set AT91_SMC_PMEN [expr (1 << 24)] ;# Page Mode Enabled
set AT91_SMC_PS [expr (3 << 28)] ;# Page Size
set AT91_SMC_PS_4 [expr (0 << 28)]
set AT91_SMC_PS_8 [expr (1 << 28)]
set AT91_SMC_PS_16 [expr (2 << 28)]
set AT91_SMC_PS_32 [expr (3 << 28)]

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# External Memory Map
set AT91_CHIPSELECT_0 0x10000000
set AT91_CHIPSELECT_1 0x20000000
set AT91_CHIPSELECT_2 0x30000000
set AT91_CHIPSELECT_3 0x40000000
set AT91_CHIPSELECT_4 0x50000000
set AT91_CHIPSELECT_5 0x60000000
set AT91_CHIPSELECT_6 0x70000000
set AT91_CHIPSELECT_7 0x80000000

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debuggers/openocd/tcl/chip/atmel/at91/pmc.tcl Normal file
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if [info exists AT91C_MAINOSC_FREQ] {
# user set this... let it be.
} {
# 18.432mhz is a common thing...
set AT91C_MAINOSC_FREQ 18432000
}
global AT91C_MAINOSC_FREQ
if [info exists AT91C_SLOWOSC_FREQ] {
# user set this... let it be.
} {
# 32khz is the norm
set AT91C_SLOWOSC_FREQ 32768
}
global AT91C_SLOWOSC_FREQ

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debuggers/openocd/tcl/chip/atmel/at91/rtt.tcl Normal file
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set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
global RTTC_RTMR
global RTTC_RTAR
global RTTC_RTVR
global RTTC_RTSR
proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
set rtpres [expr $VAL & 0x0ffff]
global BIT16 BIT17
if { $rtpres == 0 } {
set rtpres 65536;
}
global AT91C_SLOWOSC_FREQ
# Nasty hack, make this a float by tacking a .0 on the end
# otherwise, jim makes the value an integer
set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
if { $VAL & $BIT16 } {
echo "\tBit16 -> Alarm IRQ Enabled"
} else {
echo "\tBit16 -> Alarm IRQ Disabled"
}
if { $VAL & $BIT17 } {
echo "\tBit17 -> RTC Inc IRQ Enabled"
} else {
echo "\tBit17 -> RTC Inc IRQ Disabled"
}
# Bit 18 is write only.
}
proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
global BIT0 BIT1
if { $VAL & $BIT0 } {
echo "\tBit0 -> ALARM PENDING"
} else {
echo "\tBit0 -> alarm not pending"
}
if { $VAL & $BIT1 } {
echo "\tBit0 -> RTINC PENDING"
} else {
echo "\tBit0 -> rtinc not pending"
}
}
proc show_RTTC { } {
show_mmr32_reg RTTC_RTMR
show_mmr32_reg RTTC_RTAR
show_mmr32_reg RTTC_RTVR
show_mmr32_reg RTTC_RTSR
}

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debuggers/openocd/tcl/chip/atmel/at91/sam9_smc.cfg Normal file
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# Setup register
#
# ncs_read_setup
# nrd_setup
# ncs_write_setup
# set nwe_setup
#
#
# Pulse register
#
# ncs_read_pulse
# nrd_pulse
# ncs_write_pulse
# nwe_pulse
#
#
# Cycle register
#
# read_cycle 0
# write_cycle 0
#
#
# Mode register
#
# mode
# tdf_cycles
proc sam9_smc_config { cs smc_config } {
;# Setup Register for CS n
set AT91_SMC_SETUP [expr ($::AT91_SMC + 0x00 + ((cs)*0x10))]
set val [expr ($smc_config(nwe_setup) << 0)]
set val [expr ($val | $smc_config(ncs_write_setup) << 8]
set val [expr ($val | $smc_config(nrd_setup)) << 16]
set val [expr ($val | $smc_config(ncs_read_setup) << 24]
mww $AT91_SMC_SETUP $val
;# Pulse Register for CS n
set AT91_SMC_PULSE [expr ($::AT91_SMC + 0x04 + ((cs)*0x10))]
set val [expr ($smc_config(nwe_pulse) << 0)]
set val [expr ($val | $smc_config(ncs_write_pulse) << 8]
set val [expr ($val | $smc_config(nrd_pulse) << 16]
set val [expr ($val | $smc_config(ncs_read_pulse) << 24]
mww $AT91_SMC_PULSE $val
;# Cycle Register for CS n
set AT91_SMC_CYCLE [expr ($::AT91_SMC + 0x08 + ((cs)*0x10))]
set val [expr ($smc_config(write_cycle) << 0)]
set val [expr ($val | $smc_config(read_cycle) << 16]
mww $AT91_SMC_CYCLE $val
;# Mode Register for CS n
set AT91_SMC_MODE [expr ($::AT91_SMC + 0x0c + ((cs)*0x10))]
set val [expr ($smc_config(mode) << 0)]
set val [expr ($val | $smc_config(tdf_cycles) << 16]
mww $AT91_SMC_MODE $val
}

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# the DBGU and USARTs are 'almost' indentical'
set DBGU_CR [expr $AT91C_BASE_DBGU + 0x00000000]
set DBGU_MR [expr $AT91C_BASE_DBGU + 0x00000004]
set DBGU_IER [expr $AT91C_BASE_DBGU + 0x00000008]
set DBGU_IDR [expr $AT91C_BASE_DBGU + 0x0000000C]
set DBGU_IMR [expr $AT91C_BASE_DBGU + 0x00000010]
set DBGU_CSR [expr $AT91C_BASE_DBGU + 0x00000014]
set DBGU_RHR [expr $AT91C_BASE_DBGU + 0x00000018]
set DBGU_THR [expr $AT91C_BASE_DBGU + 0x0000001C]
set DBGU_BRGR [expr $AT91C_BASE_DBGU + 0x00000020]
# no RTOR
# no TTGR
# no FIDI
# no NER
set DBGU_CIDR [expr $AT91C_BASE_DBGU + 0x00000040]
set DBGU_EXID [expr $AT91C_BASE_DBGU + 0x00000044]
set DBGU_FNTR [expr $AT91C_BASE_DBGU + 0x00000048]
set USx_CR 0x00000000
set USx_MR 0x00000004
set USx_IER 0x00000008
set USx_IDR 0x0000000C
set USx_IMR 0x00000010
set USx_CSR 0x00000014
set USx_RHR 0x00000018
set USx_THR 0x0000001C
set USx_BRGR 0x00000020
set USx_RTOR 0x00000024
set USx_TTGR 0x00000028
set USx_FIDI 0x00000040
set USx_NER 0x00000044
set USx_IF 0x0000004C
# Create all the uarts that exist..
# we blow up if there are >9
proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
# First - just print it
set x [show_normalize_bitfield $VAL 3 0]
if { $x == 0 } {
echo "\tNormal operation"
} else {
echo [format "\tNon Normal operation mode: 0x%02x" $x]
}
set x [show_normalize_bitfield $VAL 11 9]
set s "unknown"
switch -exact $x {
0 { set s "Even" }
1 { set s "Odd" }
2 { set s "Force=0" }
3 { set s "Force=1" }
* {
set $x [expr $x & 6]
switch -exact $x {
4 { set s "None" }
6 { set s "Multidrop Mode" }
}
}
}
echo [format "\tParity: %s " $s]
set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
echo [format "\tDatabits: %d" $x]
set x [show_normalize_bitfield $VAL 13 12]
switch -exact $x {
0 { echo "\tStop bits: 1" }
1 { echo "\tStop bits: 1.5" }
2 { echo "\tStop bits: 2" }
3 { echo "\tStop bits: Illegal/Reserved" }
}
}
# For every possbile usart...
foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
set n AT91C_BASE_[set WHO]
set str ""
# Only if it exists on the chip
if [ info exists $n ] {
# Hence: $n - is like AT91C_BASE_USx
# For every sub-register
foreach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF} {
# vn = variable name
set vn [set WHO]_[set REG]
# vn = USx_IER
# vv = variable value
set vv [expr $$n + [set USx_[set REG]]]
# And VV is the address in memory of that register
# make that VN a GLOBAL so others can find it
global $vn
set $vn $vv
# Create a command for this specific register.
proc show_$vn { } "show_mmr32_reg $vn"
# Add this command to the Device(as a whole) command
set str "$str\nshow_$vn"
}
# Now - create the DEVICE(as a whole) command
set fn show_$WHO
proc $fn { } $str
}
}
# The Debug Uart is special..
set str ""
# For every sub-register
foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
# Create a command for this specific register.
proc show_$REG { } "show_mmr32_reg $REG"
# Add this command to the Device(as a whole) command
set str "$str\nshow_$REG"
}
# Now - create the DEVICE(as a whole) command
proc show_DBGU { } $str
unset str
proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }

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debuggers/openocd/tcl/chip/st/spear/quirk_no_srst.tcl Normal file
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# Quirks to bypass missing SRST on JTAG connector
# EVALSPEAr310 Rev. 2.0
# http://www.st.com/spear
#
# Date: 2010-08-17
# Author: Antonio Borneo <borneo.antonio@gmail.com>
# For boards that have JTAG SRST not connected.
# We use "arm9 vector_catch reset" to catch button reset event.
$_TARGETNAME configure -event reset-assert sp_reset_assert
$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post
# keeps the name of the SPEAr target
global sp_target_name
set sp_target_name $_TARGETNAME
# Keeps the argument of "reset" command (run, init, halt).
global sp_reset_mode
set sp_reset_mode ""
# Helper procedure. Returns 0 is target is halted.
proc sp_is_halted {} {
global sp_target_name
return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
}
# wait for reset button to be pressed, causing CPU to get halted
proc sp_reset_deassert_post {} {
global sp_reset_mode
set bar(0) |
set bar(1) /
set bar(2) -
set bar(3) \\
poll on
echo "====> Press reset button on the board <===="
for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} {
echo -n "$bar([expr $i & 3])\r"
sleep 200
}
# Remove catch reset event
arm9 vector_catch none
# CPU is halted, but we typed "reset run" ...
if { [string compare $sp_reset_mode "run"] == 0 } {
resume
}
}
# Override reset-assert, since no SRST available
# Catch reset event
proc sp_reset_assert {} {
arm9 vector_catch reset
}
# Override default init_reset{mode} to catch parameter "mode"
proc init_reset {mode} {
global sp_reset_mode
set sp_reset_mode $mode
# We need to detect CPU get halted, so exit from halt
if { [sp_is_halted] } {
echo "Resuming CPU to detect reset"
resume
}
# Execute default init_reset{mode}
jtag arp_init-reset
}

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# Generic init scripts for all ST SPEAr3xx family
# http://www.st.com/spear
#
# Date: 2010-09-23
# Author: Antonio Borneo <borneo.antonio@gmail.com>
# Initialize internal clock
# Default:
# - Crystal = 24 MHz
# - PLL1 = 332 MHz
# - PLL2 = 332 MHz
# - CPU_CLK = 332 MHz
# - DDR_CLK = 332 MHz async
# - HCLK = 166 MHz
# - PCLK = 83 MHz
proc sp3xx_clock_default {} {
mww 0xfca00000 0x00000002 ;# set sysclk slow
mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
# DDRCORE disable to change frequency
set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
mww 0xfca8002c $val
mww 0xfca8002c $val ;# Yes, write twice!
# programming PLL1
mww 0xfca8000c 0xa600010c ;# M=166 P=1 N=12
mww 0xfca80008 0x00001c0a ;# power down
mww 0xfca80008 0x00001c0e ;# enable
mww 0xfca80008 0x00001c06 ;# strobe
mww 0xfca80008 0x00001c0e
while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
# programming PLL2
mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
mww 0xfca80014 0x00001c0a ;# power down
mww 0xfca80014 0x00001c0e ;# enable
mww 0xfca80014 0x00001c06 ;# strobe
mww 0xfca80014 0x00001c0e
while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
mww 0xfca80028 0x00000082 ;# enable plltimeen
mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
# Select source of DDR clock
#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
# DDRCORE enable after change frequency
mmw 0xfca8002c 0x20000000 0x00000000
}
proc sp3xx_common_init {} {
mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals
mww 0xfca80038 0x00000000 ;# remove reset of all peripherals
mww 0xfca80034 0x0000ffff ;# enable all RAS clocks
mww 0xfca80040 0x00000000 ;# remove all RAS resets
mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
mww 0xfc000000 0x00000f5f
# Initialize Bus Interconnection Matrix
# All ports Round-Robin and lowest priority
mww 0xfca8007c 0x80000007
mww 0xfca80080 0x80000007
mww 0xfca80084 0x80000007
mww 0xfca80088 0x80000007
mww 0xfca8008c 0x80000007
mww 0xfca80090 0x80000007
mww 0xfca80094 0x80000007
mww 0xfca80098 0x80000007
mww 0xfca8009c 0x80000007
}
# Specific init scripts for ST SPEAr300
proc sp300_init {} {
mww 0x99000000 0x00003fff ;# RAS function enable
}
# Specific init scripts for ST SPEAr310
proc sp310_init {} {
mww 0xb4000008 0x00002ff4 ;# RAS function enable
mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
mww 0xfca80140 0x017bdef6
}
proc sp310_emi_init {} {
# set EMI pad strength
mmw 0xfca80134 0x0e000000 0x00000000
mmw 0xfca80138 0x0e739ce7 0x00000000
mmw 0xfca8013c 0x00039ce7 0x00000000
# set safe EMI timing as in BootROM
#mww 0x4f000000 0x0000000f ;# tAP_0_reg
#mww 0x4f000004 0x00000000 ;# tSDP_0_reg
#mww 0x4f000008 0x000000ff ;# tDPw_0_reg
#mww 0x4f00000c 0x00000111 ;# tDPr_0_reg
#mww 0x4f000010 0x00000002 ;# tDCS_0_reg
# set fast EMI timing as in Linux
mww 0x4f000000 0x00000010 ;# tAP_0_reg
mww 0x4f000004 0x00000005 ;# tSDP_0_reg
mww 0x4f000008 0x0000000a ;# tDPw_0_reg
mww 0x4f00000c 0x0000000a ;# tDPr_0_reg
mww 0x4f000010 0x00000005 ;# tDCS_0_re
# 32bit wide, 8/16/32bit access
mww 0x4f000014 0x0000000e ;# control_0_reg
mww 0x4f000094 0x0000003f ;# ack_reg
}
# Specific init scripts for ST SPEAr320
proc sp320_init {} {
mww 0xb300000c 0xffffac04 ;# RAS function enable
mww 0xb3000010 0x00000001 ;# RAS mode select
}

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# Init scripts to configure DDR controller of SPEAr3xx
# http://www.st.com/spear
# Original values taken from XLoader source code
#
# Date: 2010-09-23
# Author: Antonio Borneo <borneo.antonio@gmail.com>
proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
if { $ddr_chips != 1 && $ddr_chips != 2 } {
error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips
}
if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips
set ddr_size 0x08000000
## add here new DDR chip definition. Prototype:
#} elseif { $ddr_type == "?????" } {
# ????? $ddr_chips
# set ddr_size 0x?????
} else {
error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
}
# MPMC START
mww 0xfc60001c 0x01000100
if { $ddr_chips == 2 } {
echo [format \
"Double chip DDR memory. Total memory size 0x%08x byte" \
[expr 2 * $ddr_size]]
} else {
echo [format \
"Single chip DDR memory. Memory size 0x%08x byte" \
$ddr_size]
}
}
# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {
# DDR_PAD_REG
mww 0xfca800f0 0x00003aa5
# Use "1:2 sync" only when DDR clock source is PLL1 and
# HCLK is half of PLL1
mww 0xfc600000 0x00000001 ;# MEMCTL_AHB_SET_00 # This is async
mww 0xfc600004 0x00000000 ;# MEMCTL_AHB_SET_01
# mww 0xfc600000 0x02020201 ;# MEMCTL_AHB_SET_00 # This is 1:2 sync
# mww 0xfc600004 0x02020202 ;# MEMCTL_AHB_SET_01
mww 0xfc600008 0x01000000 ;# MEMCTL_RFSH_SET_00
mww 0xfc60000c 0x00000101 ;# MEMCTL_DLL_SET_00
mww 0xfc600010 0x00000101 ;# MEMCTL_GP_00
mww 0xfc600014 0x01000000 ;# MEMCTL_GP_01
mww 0xfc600018 0x00010001 ;# MEMCTL_GP_02
mww 0xfc60001c 0x00000100 ;# MEMCTL_GP_03
mww 0xfc600020 0x00010001 ;# MEMCTL_GP_04
if { $ddr_chips == 2 } {
mww 0xfc600024 0x01020203 ;# MEMCTL_GP_05
mww 0xfc600028 0x01000102 ;# MEMCTL_GP_06
mww 0xfc60002c 0x02000202 ;# MEMCTL_AHB_SET_02
} else {
mww 0xfc600024 0x00000201 ;# MEMCTL_GP_05
mww 0xfc600028 0x02000001 ;# MEMCTL_GP_06
mww 0xfc60002c 0x02000201 ;# MEMCTL_AHB_SET_02
}
mww 0xfc600030 0x04040105 ;# MEMCTL_AHB_SET_03
mww 0xfc600034 0x03030302 ;# MEMCTL_AHB_SET_04
mww 0xfc600038 0x02040101 ;# MEMCTL_AHB_SET_05
mww 0xfc60003c 0x00000002 ;# MEMCTL_AHB_SET_06
mww 0xfc600044 0x03000405 ;# MEMCTL_DQS_SET_0
mww 0xfc600048 0x03040002 ;# MEMCTL_TIME_SET_01
mww 0xfc60004c 0x04000305 ;# MEMCTL_TIME_SET_02
mww 0xfc600050 0x0505053f ;# MEMCTL_AHB_RELPR_00
mww 0xfc600054 0x05050505 ;# MEMCTL_AHB_RELPR_01
mww 0xfc600058 0x04040405 ;# MEMCTL_AHB_RELPR_02
mww 0xfc60005c 0x04040404 ;# MEMCTL_AHB_RELPR_03
mww 0xfc600060 0x03030304 ;# MEMCTL_AHB_RELPR_04
mww 0xfc600064 0x03030303 ;# MEMCTL_AHB_RELPR_05
mww 0xfc600068 0x02020203 ;# MEMCTL_AHB_RELPR_06
mww 0xfc60006c 0x02020202 ;# MEMCTL_AHB_RELPR_07
mww 0xfc600070 0x01010102 ;# MEMCTL_AHB_RELPR_08
mww 0xfc600074 0x01010101 ;# MEMCTL_AHB_RELPR_09
mww 0xfc600078 0x00000001 ;# MEMCTL_AHB_RELPR_10
mww 0xfc600088 0x0a0c0a00 ;# MEMCTL_DQS_SET_1
mww 0xfc60008c 0x0000023f ;# MEMCTL_GP_07
mww 0xfc600090 0x00050a00 ;# MEMCTL_GP_08
mww 0xfc600094 0x11000000 ;# MEMCTL_GP_09
mww 0xfc600098 0x00001302 ;# MEMCTL_GP_10
mww 0xfc60009c 0x00001c1c ;# MEMCTL_DLL_SET_01
mww 0xfc6000a0 0x7c000000 ;# MEMCTL_DQS_OUT_SHIFT
mww 0xfc6000a4 0x005c0000 ;# MEMCTL_WR_DQS_SHIFT
mww 0xfc6000a8 0x2b050e00 ;# MEMCTL_TIME_SET_03
mww 0xfc6000ac 0x00640064 ;# MEMCTL_AHB_PRRLX_00
mww 0xfc6000b0 0x00640064 ;# MEMCTL_AHB_PRRLX_01
mww 0xfc6000b4 0x00000064 ;# MEMCTL_AHB_PRRLX_02
mww 0xfc6000b8 0x00000000 ;# MEMCTL_OUTRANGE_LGTH
mww 0xfc6000bc 0x00200020 ;# MEMCTL_AHB_RW_SET_00
mww 0xfc6000c0 0x00200020 ;# MEMCTL_AHB_RW_SET_01
mww 0xfc6000c4 0x00200020 ;# MEMCTL_AHB_RW_SET_02
mww 0xfc6000c8 0x00200020 ;# MEMCTL_AHB_RW_SET_03
mww 0xfc6000cc 0x00200020 ;# MEMCTL_AHB_RW_SET_04
mww 0xfc6000d8 0x00000a24 ;# MEMCTL_TREF
mww 0xfc6000dc 0x00000000 ;# MEMCTL_EMRS3_DATA
mww 0xfc6000e0 0x5b1c00c8 ;# MEMCTL_TIME_SET_04
mww 0xfc6000e4 0x00c8002e ;# MEMCTL_TIME_SET_05
mww 0xfc6000e8 0x00000000 ;# MEMCTL_VERSION
mww 0xfc6000ec 0x0001046b ;# MEMCTL_TINIT
mww 0xfc6000f0 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_01
mww 0xfc6000f4 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_02
mww 0xfc600104 0x001c0000 ;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
mww 0xfc600108 0x0019001c ;# MEMCTL_DLL_SET_02
mww 0xfc60010c 0x00100000 ;# MEMCTL_DLL_SET_03
mww 0xfc600110 0x001e007a ;# MEMCTL_DQS_SET_2
mww 0xfc600188 0x00000000 ;# MEMCTL_USER_DEF_REG_0
mww 0xfc60018c 0x00000000 ;# MEMCTL_USER_DEF_REG_1
mww 0xfc600190 0x01010001 ;# MEMCTL_GP_11
mww 0xfc600194 0x01000000 ;# MEMCTL_GP_12
mww 0xfc600198 0x00000001 ;# MEMCTL_GP_13
mww 0xfc60019c 0x00400000 ;# MEMCTL_GP_14
mww 0xfc6001a0 0x00000000 ;# MEMCTL_EMRS2_DATA_X
mww 0xfc6001a4 0x00000000 ;# MEMCTL_LWPWR_CNT
mww 0xfc6001a8 0x00000000 ;# MEMCTL_LWPWR_REG
mww 0xfc6001ac 0x00860000 ;# MEMCTL_GP_15
mww 0xfc6001b0 0x00000002 ;# MEMCTL_TPDEX
}

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source [find bitsbytes.tcl]
source [find cpu/arm/cortex_m3.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
source [find chip/st/stm32/stm32_regs.tcl]
source [find chip/st/stm32/stm32_rcc.tcl]

290
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set RCC_CR [expr $RCC_BASE + 0x00]
set RCC_CFGR [expr $RCC_BASE + 0x04]
set RCC_CIR [expr $RCC_BASE + 0x08]
set RCC_APB2RSTR [expr $RCC_BASE + 0x0c]
set RCC_APB1RSTR [expr $RCC_BASE + 0x10]
set RCC_AHBENR [expr $RCC_BASE + 0x14]
set RCC_APB2ENR [expr $RCC_BASE + 0x18]
set RCC_APB1ENR [expr $RCC_BASE + 0x1c]
set RCC_BDCR [expr $RCC_BASE + 0x20]
set RCC_CSR [expr $RCC_BASE + 0x24]
proc show_RCC_CR { } {
if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
error $msg
}
show_mmr_bitfield 0 0 $val HSI { OFF ON }
show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }
show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }
show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }
show_mmr_bitfield 16 16 $val HSEON { OFF ON }
show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY }
show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED }
show_mmr_bitfield 19 19 $val CSSON { OFF ON }
show_mmr_bitfield 24 24 $val PLLON { OFF ON }
show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }
}
proc show_RCC_CFGR { } {
if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
error $msg
}
show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL }
show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL }
show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE }
show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 }
show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 }
show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }
}
proc show_RCC_CIR { } {
if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
error $msg
}
}
proc show_RCC_APB2RSTR { } {
if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
error $msg
}
for { set x 0 } { $x < 32 } { incr x } {
set bits($x) xxx
}
set bits(15) adc3
set bits(14) usart1
set bits(13) tim8
set bits(12) spi1
set bits(11) tim1
set bits(10) adc2
set bits(9) adc1
set bits(8) iopg
set bits(7) iopf
set bits(6) iope
set bits(5) iopd
set bits(4) iopc
set bits(3) iopb
set bits(2) iopa
set bits(1) xxx
set bits(0) afio
show_mmr32_bits bits $val
}
proc show_RCC_APB1RSTR { } {
if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
error $msg
}
set bits(31) xxx
set bits(30) xxx
set bits(29) dac
set bits(28) pwr
set bits(27) bkp
set bits(26) xxx
set bits(25) can
set bits(24) xxx
set bits(23) usb
set bits(22) i2c2
set bits(21) i2c1
set bits(20) uart5
set bits(19) uart4
set bits(18) uart3
set bits(17) uart2
set bits(16) xxx
set bits(15) spi3
set bits(14) spi2
set bits(13) xxx
set bits(12) xxx
set bits(11) wwdg
set bits(10) xxx
set bits(9) xxx
set bits(8) xxx
set bits(7) xxx
set bits(6) xxx
set bits(5) tim7
set bits(4) tim6
set bits(3) tim5
set bits(2) tim4
set bits(1) tim3
set bits(0) tim2
show_mmr32_bits bits $val
}
proc show_RCC_AHBENR { } {
if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] {
error $msg
}
set bits(31) xxx
set bits(30) xxx
set bits(29) xxx
set bits(28) xxx
set bits(27) xxx
set bits(26) xxx
set bits(25) xxx
set bits(24) xxx
set bits(23) xxx
set bits(22) xxx
set bits(21) xxx
set bits(20) xxx
set bits(19) xxx
set bits(18) xxx
set bits(17) xxx
set bits(16) xxx
set bits(15) xxx
set bits(14) xxx
set bits(13) xxx
set bits(12) xxx
set bits(11) xxx
set bits(10) sdio
set bits(9) xxx
set bits(8) fsmc
set bits(7) xxx
set bits(6) crce
set bits(5) xxx
set bits(4) flitf
set bits(3) xxx
set bits(2) sram
set bits(1) dma2
set bits(0) dma1
show_mmr32_bits bits $val
}
proc show_RCC_APB2ENR { } {
if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
error $msg
}
set bits(31) xxx
set bits(30) xxx
set bits(29) xxx
set bits(28) xxx
set bits(27) xxx
set bits(26) xxx
set bits(25) xxx
set bits(24) xxx
set bits(23) xxx
set bits(22) xxx
set bits(21) xxx
set bits(20) xxx
set bits(19) xxx
set bits(18) xxx
set bits(17) xxx
set bits(16) xxx
set bits(15) adc3
set bits(14) usart1
set bits(13) tim8
set bits(12) spi1
set bits(11) tim1
set bits(10) adc2
set bits(9) adc1
set bits(8) iopg
set bits(7) iopf
set bits(6) iope
set bits(5) iopd
set bits(4) iopc
set bits(3) iopb
set bits(2) iopa
set bits(1) xxx
set bits(0) afio
show_mmr32_bits bits $val
}
proc show_RCC_APB1ENR { } {
if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
error $msg
}
set bits(31) xxx
set bits(30) xxx
set bits(29) dac
set bits(28) pwr
set bits(27) bkp
set bits(26) xxx
set bits(25) can
set bits(24) xxx
set bits(23) usb
set bits(22) i2c2
set bits(21) i2c1
set bits(20) usart5
set bits(19) usart4
set bits(18) usart3
set bits(17) usart2
set bits(16) xxx
set bits(15) spi3
set bits(14) spi2
set bits(13) xxx
set bits(12) xxx
set bits(11) wwdg
set bits(10) xxx
set bits(9) xxx
set bits(8) xxx
set bits(7) xxx
set bits(6) xxx
set bits(5) tim7
set bits(4) tim6
set bits(3) tim5
set bits(2) tim4
set bits(1) tim3
set bits(0) tim2
show_mmr32_bits bits $val
}
proc show_RCC_BDCR { } {
if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] {
error $msg
}
for { set x 0 } { $x < 32 } { incr x } {
set bits($x) xxx
}
set bits(0) lseon
set bits(1) lserdy
set bits(2) lsebyp
set bits(8) rtcsel0
set bits(9) rtcsel1
set bits(15) rtcen
set bits(16) bdrst
show_mmr32_bits bits $val
}
proc show_RCC_CSR { } {
if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] {
error $msg
}
for { set x 0 } { $x < 32 } { incr x } {
set bits($x) xxx
}
set bits(0) lsion
set bits(1) lsirdy
set bits(24) rmvf
set bits(26) pin
set bits(27) por
set bits(28) sft
set bits(29) iwdg
set bits(30) wwdg
set bits(31) lpwr
show_mmr32_bits bits $val
}
proc show_RCC { } {
show_RCC_CR
show_RCC_CFGR
show_RCC_CIR
show_RCC_APB2RSTR
show_RCC_APB1RSTR
show_RCC_AHBENR
show_RCC_APB2ENR
show_RCC_APB1ENR
show_RCC_BDCR
show_RCC_CSR
}

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# /* Peripheral and SRAM base address in the alias region */
set PERIPH_BB_BASE 0x42000000
set SRAM_BB_BASE 0x22000000
# /*Peripheral and SRAM base address in the bit-band region */
set SRAM_BASE 0x20000000
set PERIPH_BASE 0x40000000
# /*FSMC registers base address */
set FSMC_R_BASE 0xA0000000
# /*Peripheral memory map */
set APB1PERIPH_BASE [set PERIPH_BASE]
set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]
set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]
set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]
set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]
set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]
set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]
set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]
set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]
set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]
set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]
set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]
set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]
set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]
set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]
set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]
set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]
set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]
set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]
set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]
set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]
set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]
set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]
set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]
set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]
set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]
set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]
set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]
set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]
set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]
set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]
set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]
set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]
set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]
set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]
set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]
set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]
set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]
set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]
set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]
set SDIO_BASE [expr $PERIPH_BASE + 0x18000]
set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]
set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]
set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]
set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]
set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]
set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]
set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]
set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]
set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]
set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]
set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]
set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]
set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]
set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]
set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]
# /*Flash registers base address */
set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]
# /*Flash Option Bytes base address */
set OB_BASE 0x1FFFF800
# /*FSMC Bankx registers base address */
set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]
set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]
set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]
set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]
set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]
# /*Debug MCU registers base address */
set DBGMCU_BASE 0xE0042000
# /*System Control Space memory map */
set SCS_BASE 0xE000E000
set SysTick_BASE [expr $SCS_BASE + 0x0010]
set NVIC_BASE [expr $SCS_BASE + 0x0100]
set SCB_BASE [expr $SCS_BASE + 0x0D00]

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source [find chip/ti/lm3s/lm3s_regs.tcl]

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#*****************************************************************************
#
# The following are defines for the System Control register addresses.
#
#*****************************************************************************
set SYSCTL_DID0 0x400FE000 ;# Device Identification 0
set SYSCTL_DID1 0x400FE004 ;# Device Identification 1
set SYSCTL_DC0 0x400FE008 ;# Device Capabilities 0
set SYSCTL_DC1 0x400FE010 ;# Device Capabilities 1
set SYSCTL_DC2 0x400FE014 ;# Device Capabilities 2
set SYSCTL_DC3 0x400FE018 ;# Device Capabilities 3
set SYSCTL_DC4 0x400FE01C ;# Device Capabilities 4
set SYSCTL_DC5 0x400FE020 ;# Device Capabilities 5
set SYSCTL_DC6 0x400FE024 ;# Device Capabilities 6
set SYSCTL_DC7 0x400FE028 ;# Device Capabilities 7
set SYSCTL_DC8 0x400FE02C ;# Device Capabilities 8 ADC
;# Channels
set SYSCTL_PBORCTL 0x400FE030 ;# Brown-Out Reset Control
set SYSCTL_LDOPCTL 0x400FE034 ;# LDO Power Control
set SYSCTL_SRCR0 0x400FE040 ;# Software Reset Control 0
set SYSCTL_SRCR1 0x400FE044 ;# Software Reset Control 1
set SYSCTL_SRCR2 0x400FE048 ;# Software Reset Control 2
set SYSCTL_RIS 0x400FE050 ;# Raw Interrupt Status
set SYSCTL_IMC 0x400FE054 ;# Interrupt Mask Control
set SYSCTL_MISC 0x400FE058 ;# Masked Interrupt Status and
;# Clear
set SYSCTL_RESC 0x400FE05C ;# Reset Cause
set SYSCTL_RCC 0x400FE060 ;# Run-Mode Clock Configuration
set SYSCTL_PLLCFG 0x400FE064 ;# XTAL to PLL Translation
set SYSCTL_GPIOHSCTL 0x400FE06C ;# GPIO High-Speed Control
set SYSCTL_GPIOHBCTL 0x400FE06C ;# GPIO High-Performance Bus
;# Control
set SYSCTL_RCC2 0x400FE070 ;# Run-Mode Clock Configuration 2
set SYSCTL_MOSCCTL 0x400FE07C ;# Main Oscillator Control
set SYSCTL_RCGC0 0x400FE100 ;# Run Mode Clock Gating Control
;# Register 0
set SYSCTL_RCGC1 0x400FE104 ;# Run Mode Clock Gating Control
;# Register 1
set SYSCTL_RCGC2 0x400FE108 ;# Run Mode Clock Gating Control
;# Register 2
set SYSCTL_SCGC0 0x400FE110 ;# Sleep Mode Clock Gating Control
;# Register 0
set SYSCTL_SCGC1 0x400FE114 ;# Sleep Mode Clock Gating Control
;# Register 1
set SYSCTL_SCGC2 0x400FE118 ;# Sleep Mode Clock Gating Control
;# Register 2
set SYSCTL_DCGC0 0x400FE120 ;# Deep Sleep Mode Clock Gating
;# Control Register 0
set SYSCTL_DCGC1 0x400FE124 ;# Deep-Sleep Mode Clock Gating
;# Control Register 1
set SYSCTL_DCGC2 0x400FE128 ;# Deep Sleep Mode Clock Gating
;# Control Register 2
set SYSCTL_DSLPCLKCFG 0x400FE144 ;# Deep Sleep Clock Configuration
set SYSCTL_CLKVCLR 0x400FE150 ;# Clock Verification Clear
set SYSCTL_PIOSCCAL 0x400FE150 ;# Precision Internal Oscillator
;# Calibration
set SYSCTL_PIOSCSTAT 0x400FE154 ;# Precision Internal Oscillator
;# Statistics
set SYSCTL_LDOARST 0x400FE160 ;# Allow Unregulated LDO to Reset
;# the Part
set SYSCTL_I2SMCLKCFG 0x400FE170 ;# I2S MCLK Configuration
set SYSCTL_DC9 0x400FE190 ;# Device Capabilities 9 ADC
;# Digital Comparators
set SYSCTL_NVMSTAT 0x400FE1A0 ;# Non-Volatile Memory Information
set SYSCTL_RCC_USESYSDIV 0x00400000 ;# Enable System Clock Divider
set SYSCTL_RCC2_BYPASS2 0x00000800 ;# PLL Bypass 2
set SYSCTL_RCC_MOSCDIS 0x00000001 ;# Main Oscillator Disable
set SYSCTL_SRCR0 0x400FE040 ;# Software Reset Control 0
set SYSCTL_SRCR1 0x400FE044 ;# Software Reset Control 1
set SYSCTL_SRCR2 0x400FE048 ;# Software Reset Control 2
set SYSCTL_MISC 0x400FE058 ;# Masked Interrupt Status and Clear
set FLASH_FMA 0x400FD000 ;# Flash Memory Address
set FLASH_FMD 0x400FD004 ;# Flash Memory Data
set FLASH_FMC 0x400FD008 ;# Flash Memory Control
set FLASH_FCRIS 0x400FD00C ;# Flash Controller Raw Interrupt Status
set FLASH_FCIM 0x400FD010 ;# Flash Controller Interrupt Mask
set FLASH_FCMISC 0x400FD014 ;# Flash Controller Masked Interrupt Status and Clear
set FLASH_FMC2 0x400FD020 ;# Flash Memory Control 2
set FLASH_FWBVAL 0x400FD030 ;# Flash Write Buffer Valid