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debuggers: import openocd-0.7.0

Browse Source 
Initial check-in of openocd-0.7.0 as it can be downloaded from
http://sourceforge.net/projects/openocd/files/openocd/0.7.0/

Any modifications will follow.

Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55
This commit is contained in:
Lars Rademacher
2013-10-21 00:50:02 +02:00
parent 85fffe007e
commit 83d72a091e
1148 changed files with 571445 additions and 0 deletions
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61
debuggers/openocd/tcl/bitsbytes.tcl Normal file
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#----------------------------------------
# Purpose - Create some $BIT variables
# Create $K and $M variables
# and some bit field extraction variables.
# Creat helper variables ...
# BIT0.. BIT31
for { set x 0 } { $x < 32 } { set x [expr $x + 1]} {
set vn [format "BIT%d" $x]
global $vn
set $vn [expr (1 << $x)]
}
# Create K bytes values
# __1K ... to __2048K
for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
set vn [format "__%dK" $x]
global $vn
set $vn [expr (1024 * $x)]
}
# Create M bytes values
# __1M ... to __2048K
for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
set vn [format "__%dM" $x]
global $vn
set $vn [expr (1024 * 1024 * $x)]
}
proc create_mask { MSB LSB } {
return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)]
}
# Cut Bits $MSB to $LSB out of this value.
# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
# Result: 0x02340000
proc extract_bitfield { VALUE MSB LSB } {
return [expr [create_mask $MSB $LSB] & $VALUE]
}
# Cut bits $MSB to $LSB out of this value
# and shift (normalize) them down to bit 0.
#
# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
# Result: 0x00000234
#
proc normalize_bitfield { VALUE MSB LSB } {
return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB]
}
proc show_normalize_bitfield { VALUE MSB LSB } {
set m [create_mask $MSB $LSB]
set mr [expr $VALUE & $m]
set sr [expr $mr >> $LSB]
echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
return $sr
}

69
debuggers/openocd/tcl/board/actux3.cfg Normal file
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# board config file for AcTux3/XBA IXP42x board
# Date: 2010-12-16
# Author: Michael Schwingen <michael@schwingen.org>
reset_config trst_and_srst separate
adapter_nsrst_delay 100
jtag_ntrst_delay 100
source [find target/ixp42x.cfg]
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
$_TARGETNAME configure -event reset-init { init_actux3 }
proc init_actux3 { } {
##########################################################################
# setup expansion bus CS
##########################################################################
mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
mww 0xc4000004 0x94d10013 ;#CS1
mww 0xc4000008 0x95960003 ;#CS2
mww 0xc400000c 0x00000000 ;#CS3
mww 0xc4000010 0x80900003 ;#CS4
mww 0xc4000014 0x9d520003 ;#CS5
mww 0xc4000018 0x81860001 ;#CS6
mww 0xc400001c 0x80900003 ;#CS7
ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
#mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
ixp42x_set_bigendian
flash probe 0
}
proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
echo "writing bootloader: $FILE"
flash write_image erase $FILE 0x50000000 bin
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
init
reset init
# setup to debug u-boot in flash
proc uboot_debug {} {
gdb_breakpoint_override hard
xscale vector_catch 0xFF
xscale vector_table low 1 0xe59ff018
xscale vector_table low 2 0xe59ff018
xscale vector_table low 3 0xe59ff018
xscale vector_table low 4 0xe59ff018
xscale vector_table low 5 0xe59ff018
xscale vector_table low 6 0xe59ff018
xscale vector_table low 7 0xe59ff018
xscale vector_table high 1 0xe59ff018
xscale vector_table high 2 0xe59ff018
xscale vector_table high 3 0xe59ff018
xscale vector_table high 4 0xe59ff018
xscale vector_table high 5 0xe59ff018
xscale vector_table high 6 0xe59ff018
xscale vector_table high 7 0xe59ff018
}

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debuggers/openocd/tcl/board/am3517evm.cfg Normal file
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# DANGER!!!! early work in progress for this PCB/target.
#
# The most basic operations work well enough that it is
# useful to have this in the repository for cooperation
# alpha testing purposes.
#
# TI AM3517
#
# http://focus.ti.com/docs/prod/folders/print/am3517.html
# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
set CHIPTYPE "am35x"
source [find target/amdm37x.cfg]
# The TI-14 JTAG connector does not have srst. CPU reset is handled in
# hardware.
reset_config trst_only
# "amdm37x_dbginit am35x.cpu" needs to be run after init.

10
debuggers/openocd/tcl/board/arm_evaluator7t.cfg Normal file
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# This board is from ARM and has an samsung s3c45101x01 chip
source [find target/samsung_s3c4510.cfg]
#
# FIXME:
# Add (A) sdram configuration
# Add (B) flash cfi programing configuration
#

165
debuggers/openocd/tcl/board/at91cap7a-stk-sdram.cfg Normal file
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# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
#
# use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cap7
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x40700f0f
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -event reset-start {
# start off real slow when we're running off internal RC oscillator
adapter_khz 32
}
proc peek32 {address} {
mem2array t 32 $address 1
return $t(0)
}
# Wait for an expression to be true with a timeout
proc wait_state {expression} {
for {set i 0} {$i < 1000} {set i [expr $i + 1]} {
if {[uplevel 1 $expression] == 0} {
return
}
}
return -code 1 "Timed out"
}
# Use a global variable here to be able to tinker interactively with
# post reset jtag frequency.
global post_reset_khz
# Danger!!!! Even 16MHz kinda works with this target, but
# it needs to be as low as 2000kHz to be stable.
set post_reset_khz 2000
$_TARGETNAME configure -event reset-init {
echo "Configuring master clock"
# disable watchdog
mww 0xfffffd44 0xff008000
# enable user reset
mww 0xfffffd08 0xa5000001
# Enable main oscillator
mww 0xFFFFFc20 0x00000f01
wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
# Set PLLA to 96MHz
mww 0xFFFFFc28 0x20072801
wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
# Select prescaler
mww 0xFFFFFC30 0x00000004
wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
# Select master clock to 48MHz
mww 0xFFFFFC30 0x00000006
wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
echo "Master clock ok."
# Now that we're up and running, crank up speed!
global post_reset_khz ; adapter_khz $post_reset_khz
echo "Configuring the SDRAM controller..."
# Configure EBI Chip select for SDRAM
mww 0xFFFFEF30 0x00000102
# Enable clock on EBI PIOs
mww 0xFFFFFC10 0x00000004
# Configure PIO for SDRAM
mww 0xFFFFF470 0xFFFF0000
mww 0xFFFFF474 0x00000000
mww 0xFFFFF404 0xFFFF0000
# Configure SDRAMC CR
mww 0xFFFFEA08 0xA63392F9
# NOP command
mww 0xFFFFEA00 0x1
mww 0x20000000 0
# Precharge All Banks command
mww 0xFFFFEA00 0x2
mww 0x20000000 0
# Set 1st CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000010 0x00000001
# Set 2nd CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000020 0x00000002
# Set 3rd CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000030 0x00000003
# Set 4th CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000040 0x00000004
# Set 5th CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000050 0x00000005
# Set 6th CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000060 0x00000006
# Set 7th CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000070 0x00000007
# Set 8th CBR
mww 0xFFFFEA00 0x00000004
mww 0x20000080 0x00000008
# Set LMR operation
mww 0xFFFFEA00 0x00000003
# Perform LMR burst=1, lat=2
mww 0x20000020 0xCAFEDEDE
# Set Refresh Timer
mww 0xFFFFEA04 0x00000203
# Set Normal mode
mww 0xFFFFEA00 0x00000000
mww 0x20000000 0x00000000
#remap internal memory at address 0x0
mww 0xffffef00 0x3
echo "SDRAM configuration ok."
}
$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
#set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432

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debuggers/openocd/tcl/board/at91eb40a.cfg Normal file
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#Script for AT91EB40a
# FIXME use some standard target config, maybe create one from this
#
# source [find target/...cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME at91eb40a
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x1f0f0f0f
}
#Atmel ties SRST & TRST together, at which point it makes
#no sense to use TRST, but use TMS instead.
#
#The annoying thing with tying SRST & TRST together is that
#there is no way to halt the CPU *before and during* the
#SRST reset, which means that the CPU will run a number
#of cycles before it can be halted(as much as milliseconds).
reset_config srst_only srst_pulls_trst
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
#target configuration
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
# speed up memory downloads
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
#flash driver
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
# required for usable performance. Used for lots of
# other things than flash programming.
$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
$_TARGETNAME configure -event reset-init {
echo "Running reset init script for AT91EB40A"
# Reset script for AT91EB40a
reg cpsr 0x000000D3
mww 0xFFE00020 0x1
mww 0xFFE00024 0x00000000
mww 0xFFE00000 0x01002539
mww 0xFFFFF124 0xFFFFFFFF
mww 0xffff0010 0x100
mww 0xffff0034 0x100
}
# This target is pretty snappy...
adapter_khz 16000

82
debuggers/openocd/tcl/board/at91rm9200-dk.cfg Normal file
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#
# This is for the "at91rm9200-DK" (not the EK) eval board.
#
# The two are probably very simular.... I have DK...
#
# It has atmel at91rm9200 chip.
source [find target/at91rm9200.cfg]
reset_config trst_and_srst
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
proc at91rm9200_dk_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
adapter_khz 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
mww 0xfffffc04 0xfffffffe
## disable all clocks to pioa and piob
mww 0xfffffc14 0xffffffc3
## master clock = slow cpu = slow
## (means the CPU is running at 32khz!)
mww 0xfffffc30 0
## main osc enable
mww 0xfffffc20 0x0000ff01
## program pllA
mww 0xfffffc28 0x20263e04
## program pllB
mww 0xfffffc2c 0x10483e0e
## let pll settle... sleep 100msec
sleep 100
## switch to fast clock
mww 0xfffffc30 0x202
## Sleep some - (go read)
sleep 100
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
adapter_khz 40000
#========================================
## set memc for all memories
mww 0xffffff60 0x02
## program smc controller
mww 0xffffff70 0x3284
## init sdram
mww 0xffffff98 0x7fffffd0
## all banks precharge
mww 0xffffff80 0x02
## touch sdram chip to make it work
mww 0x20000000 0
## sdram controller mode register
mww 0xffffff90 0x04
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
## sdram controller mode register
## Refresh, etc....
mww 0xffffff90 0x03
mww 0x20000080 0
mww 0xffffff94 0x1f4
mww 0x20000080 0
mww 0xffffff90 0x10
mww 0x20000000 0
mww 0xffffff00 0x01
}

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debuggers/openocd/tcl/board/at91rm9200-ek.cfg Normal file
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#
# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
#
# under GPLv2 Only
#
# This is for the "at91rm9200-ek" eval board.
#
#
# It has atmel at91rm9200 chip.
source [find target/at91rm9200.cfg]
reset_config trst_and_srst
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# The chip may run @ 32khz, so set a really low JTAG speed
adapter_khz 8
proc at91rm9200_ek_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
adapter_khz 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
mww 0xfffffc04 0xfffffffe
## disable all clocks to pioa and piob
mww 0xfffffc14 0xffffffc3
## master clock = slow cpu = slow
## (means the CPU is running at 32khz!)
mww 0xfffffc30 0
## main osc enable
mww 0xfffffc20 0x0000ff01
## MC_PUP
mww 0xFFFFFF50 0x00000000
## MC_PUER: Memory controller protection unit disable
mww 0xFFFFFF54 0x00000000
## EBI_CFGR
mww 0xFFFFFF64 0x00000000
## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
mww 0xFFFFFF70 0x00003284
## Init Clocks
## CKGR_PLLAR
mww 0xFFFFFC28 0x2000BF05
## PLLAR: 179,712000 MHz for PCK
mww 0xFFFFFC28 0x20263E04
sleep 100
## PMC_MCKR
mww 0xFFFFFC30 0x00000100
sleep 100
## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
mww 0xFFFFFC30 0x00000202
sleep 100
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
adapter_khz 40000
#========================================
## Init SDRAM
## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
mww 0xFFFFF870 0xFFFF0000
## PIOC_BSR:
mww 0xFFFFF874 0x00000000
## PIOC_PDR:
mww 0xFFFFF804 0xFFFF0000
## EBI_CSA : CS1=SDRAM
mww 0xFFFFFF60 0x00000002
## EBI_CFGR:
mww 0xFFFFFF64 0x00000000
## SDRC_CR :
mww 0xFFFFFF98 0x2188c155
## SDRC_MR : Precharge All
mww 0xFFFFFF90 0x00000002
## access SDRAM
mww 0x20000000 0x00000000
## SDRC_MR : Refresh
mww 0xFFFFFF90 0x00000004
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
## SDRC_MR : Load Mode Register
mww 0xFFFFFF90 0x00000003
## access SDRAM
mww 0x20000080 0x00000000
## SDRC_TR : Write refresh rate
mww 0xFFFFFF94 0x000002E0
## access SDRAM
mww 0x20000000 0x00000000
## SDRC_MR : Normal Mode
mww 0xFFFFFF90 0x00000000
## access SDRAM
mww 0x20000000 0x00000000
}

63
debuggers/openocd/tcl/board/at91sam9261-ek.cfg Normal file
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################################################################################
# Atmel AT91SAM9261-EK eval board
################################################################################
source [find mem_helper.tcl]
source [find target/at91sam9261.cfg]
uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
# By default S1 is open and this means that NTRST is not connected.
# The reset_config in target/at91sam9261.cfg is overridden here.
# (or S1 must be populated with a 0 Ohm resistor)
reset_config srst_only
scan_chain
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
proc at91sam9261ek_reset_init { } {
;# for ppla at 199 Mhz
set config(master_pll_div) 15
set config(master_pll_mul) 162
;# for ppla at 239 Mhz
;# set master_pll_div 1
;# set master_pll_mul 13
set val [expr $::AT91_WDT_WDV] ;# Counter Value
set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
set config(wdt_mr_val) $val
;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA
set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9]
set val [expr ($val | $::AT91_SDRAMC_NR_13)]
set val [expr ($val | $::AT91_SDRAMC_NB_4)]
set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
set val [expr ($val | (2 << 8))] ;# Write Recovery Delay
set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
set val [expr ($val | (3 << 16))] ;# Row Precharge Delay
set val [expr ($val | (2 << 20))] ;# Row to Column Delay
set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
set val [expr ($val | (8 << 28))] ;# Exit Self Refresh to Active Delay
set config(sdram_cr_val) $val
set config(sdram_tr_val) 0x13c
set config(sdram_base) $::AT91_CHIPSELECT_1
at91sam9_reset_init $config
}

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debuggers/openocd/tcl/board/at91sam9263-ek.cfg Normal file
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################################################################################
# Atmel AT91SAM9263-EK eval board
################################################################################
source [find mem_helper.tcl]
source [find target/at91sam9263.cfg]
uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
# By default S1 is open and this means that NTRST is not connected.
# The reset_config in target/at91sam9263.cfg is overridden here.
# (or S1 must be populated with a 0 Ohm resistor)
reset_config srst_only
scan_chain
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
proc at91sam9263ek_reset_init { } {
set config(master_pll_div) 14
set config(master_pll_mul) 171
set val [expr $::AT91_WDT_WDV] ;# Counter Value
set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
set config(wdt_mr_val) $val
set config(sdram_piod) 1
;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
set val [expr $::AT91_MATRIX_EBI0_DBPUC]
set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
set config(matrix_ebicsa_val) $val
;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9]
set val [expr ($val | $::AT91_SDRAMC_NR_13)]
set val [expr ($val | $::AT91_SDRAMC_NB_4)]
set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
set val [expr ($val | (1 << 8))] ;# Write Recovery Delay
set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
set val [expr ($val | (2 << 16))] ;# Row Precharge Delay
set val [expr ($val | (2 << 20))] ;# Row to Column Delay
set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay
set config(sdram_cr_val) $val
set config(sdram_tr_val) 0x13c
set config(sdram_base) $::AT91_CHIPSELECT_1
at91sam9_reset_init $config
}

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#################################################################################################
# #
# Author: Gary Carlson (gcarlson@carlson-minot.com) #
# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. #
# #
#################################################################################################
# FIXME use some standard target config, maybe create one from this
#
# source [find target/...cfg]
source [find target/at91sam9g20.cfg]
set _FLASHTYPE nandflash_cs3
# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore
# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is
# added to the board to connect the trst signal, then this parameter may need to be changed.
reset_config srst_only
adapter_nsrst_delay 200
jtag_ntrst_delay 200
# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
# some powerful features, we want to have a special function that handles "reset init". To do this we declare
# an event handler where these special activities can take place.
scan_chain
$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
# NandFlash configuration and definition
nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
at91sam9 cle 0 22
at91sam9 ale 0 21
at91sam9 rdy_busy 0 0xfffff800 13
at91sam9 ce 0 0xfffff800 14
proc read_register {register} {
set result ""
mem2array result 32 $register 1
return $result(0)
}
proc at91sam9g20_reset_start { } {
# Make sure that the the jtag is running slow, since there are a number of different ways the board
# can be configured coming into this state that can cause communication problems with the jtag
# adapter. Also since this call can be made following a "reset init" where fast memory accesses
# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
# jtag speed without causing GDB keep alive problem.
arm7_9 fast_memory_access disable
adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
halt ;# Make sure processor is halted, or error will result in following steps.
wait_halt 10000
mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
}
proc at91sam9g20_reset_init { } {
# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
# a number of steps that must be carefully performed. The process outline below follows the
# recommended procedure outlined in the AT91SAM9G20 technical manual.
#
# Several key and very important things to keep in mind:
# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
mww 0xfffffc28 0x202a3f01
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00000101
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz
# -> PCLK = 396.288 MHz
# Switch over to adaptive clocking.
adapter_khz 0
# Enable faster DCC downloads and memory accesses.
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
# To be able to use external SDRAM, several peripheral configuration registers must
# be modified. The first change is made to PIO_ASR to select peripheral functions
# for D15 through D31. The second change is made to the PIO_PDR register to disable
# this for D15 through D31.
mww 0xfffff870 0xffff0000
mww 0xfffff804 0xffff0000
# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
# using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
mww 0xffffef1c 0x000100a
# The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
# a number of registers. The first step involves setting up the general I/O pins on the processor
# to be able to interface and support the external memory.
mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
# The exact physical timing characteristics for the memory type used on the current board
# (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers
# is a little tedious to do here. If you have questions about how to do this, Atmel has
# a decent application note #6255B that covers this process.
mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
# Identify NandFlash bank 0.
nand probe nandflash_cs3
# The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
# into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
# of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
#
# CAS latency = 3 cycles
# TXSR = 10 cycles
# TRAS = 6 cycles
# TRCD = 3 cycles
# TRP = 3 cycles
# TRC = 9 cycles
# TWR = 2 cycles
# 9 column, 13 row, 4 banks
# refresh equal to or less then 7.8 us for commerical/industrial rated devices
#
# Thus SDRAM_CR = 0xa6339279
mww 0xffffea08 0xa6339279
# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
# the starting memory location for the SDRAM.
mww 0xffffea00 0x00000001
mww 0x20000000 0
# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
# value into the starting memory location for the SDRAM.
mww 0xffffea00 0x00000002
mww 0x20000000 0
# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
# zero values eight times into the starting memory location for the SDRAM.
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
# the starting memory location for the SDRAM.
mww 0xffffea00 0x3
mww 0x20000000 0
# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
# memory location for the SDRAM.
mww 0xffffea00 0x0
mww 0x20000000 0
# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
mww 0xffffea04 0x0000039c
}

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# Atmel AT91SAM7S-EK
# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
set CHIPNAME at91sam7s256
source [find target/at91sam7sx.cfg]

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################################################################################
# Atmel AT91SAM9260-EK eval board
#
# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
#
# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
# OSCSEL configured for external 32.768 kHz crystal
#
# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
#
################################################################################
# We add to the minimal configuration.
source [find target/at91sam9260.cfg]
# By default S1 is open and this means that NTRST is not connected.
# The reset_config in target/at91sam9260.cfg is overridden here.
# (or S1 must be populated with a 0 Ohm resistor)
reset_config srst_only
$_TARGETNAME configure -event reset-start {
# At reset CPU runs at 32.768 kHz.
# JTAG Frequency must be 6 times slower if RCLK is not supported.
jtag_rclk 5
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
sleep 10 ;# wait 10 ms
mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
sleep 10 ;# wait 10 ms
mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
sleep 10 ;# wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
}

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debuggers/openocd/tcl/board/atmel_at91sam9rl-ek.cfg Normal file
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################################################################################
#
# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
#
# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
# OSCSEL configured for external 32.768 kHz crystal
#
# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
#
################################################################################
# We add to the minimal configuration.
source [find target/at91sam9rl.cfg]
$_TARGETNAME configure -event reset-start {
# At reset CPU runs at 32.768 kHz.
# JTAG Frequency must be 6 times slower if RCLK is not supported.
jtag_rclk 5
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
sleep 10 ;# wait 10 ms
mww 0xfffffc28 0x2031bf03 ;# CKGR_PLLR: Set PLL Register for 200 MHz
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
sleep 10 ;# wait 10 ms
mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
sleep 10 ;# wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
mww 0xfffff670 0xffff0000 ;# PIO_ASR : Select peripheral function for D16..D31 (PIOB)
mww 0xfffff604 0xffff0000 ;# PIO_PDR : Disable PIO function for D16..D31 (PIOB)
mww 0xffffef20 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
}

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debuggers/openocd/tcl/board/atmel_sam3n_ek.cfg Normal file
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#
# Board configuration for Atmel's SAM3N-EK
#
reset_config srst_only
set CHIPNAME at91sam3n4c
adapter_khz 32
source [find target/at91sam3nXX.cfg]

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debuggers/openocd/tcl/board/atmel_sam3s_ek.cfg Normal file
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source [find target/at91sam3sXX.cfg]
$_TARGETNAME configure -event gdb-attach { reset init }

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debuggers/openocd/tcl/board/atmel_sam3u_ek.cfg Normal file
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source [find target/at91sam3u4e.cfg]
reset_config srst_only

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debuggers/openocd/tcl/board/atmel_sam3x_ek.cfg Normal file
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source [find target/at91sam3ax_8x.cfg]
reset_config srst_only

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debuggers/openocd/tcl/board/atmel_sam4s_ek.cfg Normal file
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source [find target/at91sam4sXX.cfg]
$_TARGETNAME configure -event gdb-attach { reset init }

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debuggers/openocd/tcl/board/balloon3-cpu.cfg Normal file
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# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
# The board has separate JTAG ports for cpu and CPLD/FPGA devices
# Chaining is done on IO interfaces if desired.
source [find target/pxa270.cfg]
# The board supports separate reset lines
# Override this in the interface config for parallel dongles
reset_config trst_and_srst separate
# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
# 29LV650 64Mbit Flash
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME

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debuggers/openocd/tcl/board/colibri.cfg Normal file
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# Toradex Colibri PXA270
source [find target/pxa270.cfg]
reset_config trst_and_srst srst_push_pull
adapter_nsrst_assert_width 40
# CS0 -- one bank of CFI flash, 32 MBytes
# the bank is 32-bits wide, two 16-bit chips in parallel
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME

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debuggers/openocd/tcl/board/crossbow_tech_imote2.cfg Normal file
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# Crossbow Technology iMote2
set CHIPNAME imote2
source [find target/pxa270.cfg]
# longer-than-normal reset delay
adapter_nsrst_delay 800
reset_config trst_and_srst separate
# works for P30 flash
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME

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debuggers/openocd/tcl/board/csb337.cfg Normal file
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# Cogent CSB337
# http://cogcomp.com/csb_csb337.htm
source [find target/at91rm9200.cfg]
# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# ETM9 trace port connector present on this board, 16 data pins.
if { [info exists ETM_DRIVER] } {
etm config $_TARGETNAME 16 normal half $ETM_DRIVER
# OpenOCD may someday support a real trace port driver...
# system config file would need to configure it.
} else {
etm config $_TARGETNAME 16 normal half dummy
etm_dummy config $_TARGETNAME
}
proc csb337_clk_init { } {
# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
adapter_khz 8
# CKGR_MOR: start main oscillator (3.6864 MHz)
mww 0xfffffc20 0xff01
sleep 10
# CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
mww 0xfffffc28 0x20313e01
# CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
mww 0xfffffc2c 0x12703e18
# let PLLs lock
sleep 10
# PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
mww 0xfffffc30 0x0302
sleep 20
# CPU is in Normal Mode ... allows faster JTAG clock speed
adapter_khz 40000
}
proc csb337_nor_init { } {
# SMC_CSR0: adjust timings (10 wait states)
mww 0xffffff70 0x1100318a
flash probe 0
}
proc csb337_sdram_init { } {
# enable PIOC clock
mww 0xfffffc10 0x0010
# PC31..PC16 are D31..D16, with internal pullups like D15..D0
mww 0xfffff870 0xffff0000
mww 0xfffff874 0x0
mww 0xfffff804 0xffff0000
# SDRC_CR: set timings
mww 0xffffff98 0x2188b0d5
# SDRC_MR: issue all banks precharge to SDRAM
mww 0xffffff90 2
mww 0x20000000 0
# SDRC_MR: 8 autorefresh cycles
mww 0xffffff90 4
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
mww 0x20000000 0
# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
mww 0xffffff90 3
mww 0x20000080 0
# SDRC_TR: set refresh rate
mww 0xffffff94 0x200
mww 0x20000000 0
# SDRC_MR: normal mode, 32 bit bus
mww 0xffffff90 0
mww 0x20000000 0
}
# The rm9200 chip has just been reset. Bring it up far enough
# that we can write flash or run code from SDRAM.
proc csb337_reset_init { } {
csb337_clk_init
# EBI_CSA: CS0 = NOR, CS1 = SDRAM
mww 0xffffff60 0x02
csb337_nor_init
csb337_sdram_init
# Update CP15 control register ... we don't seem to be able to
# read/modify/write its value through a TCL variable, so just
# write it. Fields are zero unless listed here ... and note
# that OpenOCD numbers this register "2", not "1" (!).
#
# - Core to use Async Clocking mode (so it uses 184 MHz most
# of the time instead of limiting to the master clock rate):
# iA(31) = 1, nF(30) = 1
# - Icache on (it's disabled now, slowing i-fetches)
# I(12) = 1
# - Reserved/ones
# 6:3 = 1
arm920t cp15 2 0xc0001078
}
$_TARGETNAME configure -event reset-init {csb337_reset_init}
arm7_9 fast_memory_access enable

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debuggers/openocd/tcl/board/csb732.cfg Normal file
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# The Cogent CSB732 board has a single i.MX35 chip
source [find target/imx35.cfg]
# Determined by trial and error
reset_config trst_and_srst combined
adapter_nsrst_delay 200
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { csb732_init }
# Bare-bones initialization of core clocks and SDRAM
proc csb732_init { } {
# Disable fast writing only for init
memwrite burst disable
# All delay loops are omitted.
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
arm mcr 15 0 15 1 0 0x2001
# Disable MMU, caches, write buffer
arm mcr 15 0 1 0 0 0x78
# Grant manager access to all domains
arm mcr 15 0 3 0 0 0xFFFFFFFF
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000
# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
mww 0x53F8001C 0xB2C01
set ESDMISC 0xB8001010
set ESDCFG0 0xB8001004
set ESDCTL0 0xB8001000
# Enable DDR
mww $ESDMISC 0x4
# Timing
mww $ESDCFG0 0x007fff3f
# CS0
mww $ESDCTL0 0x92120080
# Precharge all dummy write
mww 0x80000400 0
# Enable CS) auto-refresh
mww $ESDCTL0 0xA2120080
# Refresh twice (dummy writes)
mww 0x80000000 0
mww 0x80000000 0
# Enable CS0 load mode register
mww $ESDCTL0 0xB2120080
# Dummy writes
mwb 0x80000033 0x01
mwb 0x81000000 0x01
mww $ESDCTL0 0x82226080
mww 0x80000000 0
# Re-enable fast writing
memwrite burst enable
}

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debuggers/openocd/tcl/board/da850evm.cfg Normal file
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#DA850 EVM board
# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
source [find target/omapl138.cfg]
reset_config trst_and_srst separate
#currently any pinmux/timing must be setup by UBL before openocd can do debug
#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg

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######################################
# Target: DIGI ConnectCore Wi-9C
######################################
reset_config trst_and_srst
# FIXME use some standard target config, maybe create one from this
#
# source [find target/...cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME ns9360
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# This config file was defaulting to big endian..
set _ENDIAN big
}
# What's a good fallback frequency for this board if RCLK is
# not available??
jtag_rclk 1000
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x07926031
}
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
adapter_nsrst_delay 200
jtag_ntrst_delay 0
######################
# Target configuration
######################
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -event reset-init {
mww 0x90600104 0x33313333
mww 0xA0700000 0x00000001 ;# Enable the memory controller.
mww 0xA0700024 0x00000006 ;# Set the refresh counter 6
mww 0xA0700028 0x00000001 ;#
mww 0xA0700030 0x00000001 ;# Set the precharge period
mww 0xA0700034 0x00000004 ;# Active to precharge command period is 16 clock cycles
mww 0xA070003C 0x00000001 ;# tAPR
mww 0xA0700040 0x00000005 ;# tDAL
mww 0xA0700044 0x00000001 ;# tWR
mww 0xA0700048 0x00000006 ;# tRC 32 clock cycles
mww 0xA070004C 0x00000006 ;# tRFC 32 clock cycles
mww 0xA0700054 0x00000001 ;# tRRD
mww 0xA0700058 0x00000001 ;# tMRD
mww 0xA0700100 0x00004280 ;# Dynamic Config 0 (cs4)
mww 0xA0700120 0x00004280 ;# Dynamic Config 1 (cs5)
mww 0xA0700140 0x00004280 ;# Dynamic Config 2 (cs6)
mww 0xA0700160 0x00004280 ;# Dynamic Config 3 (cs7)
#
mww 0xA0700104 0x00000203 ;# CAS latency is 2 at 100 MHz
mww 0xA0700124 0x00000203 ;# CAS latency is 2 at 100 MHz
mww 0xA0700144 0x00000203 ;# CAS latency is 2 at 100 MHz
mww 0xA0700164 0x00000203 ;# CAS latency is 2 at 100 MHz
#
mww 0xA0700020 0x00000103 ;# issue SDRAM PALL command
#
mww 0xA0700024 0x00000001 ;# Set the refresh counter to be as small as possible
#
# Add some dummy writes to give the SDRAM time to settle, it needs two
# AHB clock cycles, here we poke in the debugger flag, this lets
# the software know that we are in the debugger
mww 0xA0900000 0x00000002
mww 0xA0900000 0x00000002
mww 0xA0900000 0x00000002
mww 0xA0900000 0x00000002
mww 0xA0900000 0x00000002
#
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
mdw 0xA0900000
#
mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
#
# Next we perform a read of RAM.
# mw = move word.
mdw 0x00022000
# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
#
mww 0xA0700020 0x00000003 ;# issue SDRAM NORMAL command
mww 0xA0700100 0x00084280 ;# Enable buffer access
mww 0xA0700120 0x00084280 ;# Enable buffer access
mww 0xA0700140 0x00084280 ;# Enable buffer access
mww 0xA0700160 0x00084280 ;# Enable buffer access
#Set byte lane state (static mem 1)"
mww 0xA0700220 0x00000082
#Flash Start
mww 0xA09001F8 0x50000000
#Flash Mask Reg
mww 0xA09001FC 0xFF000001
mww 0xA0700028 0x00000001
# RAMAddr = 0x00020000
# RAMSize = 0x00004000
# Set the processor mode
reg cpsr 0xd3
}
$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
#####################
# Flash configuration
#####################
#M29DW323DB - not working
#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME

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debuggers/openocd/tcl/board/diolan_lpc4350-db1.cfg Normal file
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#
# Diolan LPC-4350-DB1 development board
#
set CHIPNAME lpc4350
source [find target/lpc4350.cfg]

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# DM355 EVM board
# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
# http://c6000.spectrumdigital.com/evmdm355/
source [find target/ti_dm355.cfg]
reset_config trst_and_srst separate
# NOTE: disable or replace this call to dm355evm_init if you're
# debugging new UBL code from SRAM.
$_TARGETNAME configure -event reset-init { dm355evm_init }
#
# This post-reset init is called when the MMU isn't active, all IRQs
# are disabled, etc. It should do most of what a UBL does, except for
# loading code (like U-Boot) into DRAM and running it.
#
proc dm355evm_init {} {
global dm355
echo "Initialize DM355 EVM board"
# CLKIN = 24 MHz ... can't talk quickly to ARM yet
jtag_rclk 1500
########################
# PLL1 = 432 MHz (/8, x144)
# ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
# ...SYSCLK2 = 108 MHz (/4) ... Peripherals
# ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
# ...SYSCLK4 = 108 MHz (/4) ... VPSS
# pll1.{prediv,div1,div2} are fixed
# pll1.postdiv set in MISC (for *this* speed grade)
set addr [dict get $dm355 pllc1]
set pll_divs [dict create]
dict set pll_divs div3 16
dict set pll_divs div4 4
pll_v02_setup $addr 144 $pll_divs
# ARM is now running at 216 MHz, so JTAG can go faster
jtag_rclk 20000
########################
# PLL2 = 342 MHz (/8, x114)
# ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
# pll2.{postdiv,div1} are fixed
set addr [dict get $dm355 pllc2]
set pll_divs [dict create]
dict set pll_divs div1 1
dict set pll_divs prediv 8
pll_v02_setup $addr 114 $pll_divs
########################
# PINMUX
# All Video Inputs
davinci_pinmux $dm355 0 0x00007f55
# All Video Outputs
davinci_pinmux $dm355 1 0x00145555
# EMIFA (NOTE: more could be set up for use as GPIOs)
davinci_pinmux $dm355 2 0x00000c08
# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
davinci_pinmux $dm355 3 0x1bff55ff
# MMC/SD0 instead of MS; SPI0
davinci_pinmux $dm355 4 0x00000000
########################
# PSC setup (minimal)
# DDR EMIF/13, AEMIF/14, UART0/19
psc_enable 13
psc_enable 14
psc_enable 19
psc_go
########################
# DDR2 EMIF
# VTPIOCR impedance calibration
set addr [dict get $dm355 sysbase]
set addr [expr $addr + 0x70]
# clear CLR, LOCK, PWRDN; wait a clock; set CLR
mmw $addr 0 0x20c0
mmw $addr 0x2000 0
# wait for READY
while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
# set IO_READY; then LOCK and PWRSAVE; then PWRDN
mmw $addr 0x4000 0
mmw $addr 0x0180 0
mmw $addr 0x0040 0
# NOTE: this DDR2 initialization sequence borrows from
# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
# reset (then re-enable) DDR controller
psc_reset 13
psc_go
psc_enable 13
psc_go
# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
set addr [dict get $dm355 ddr_emif]
# DDRPHYCR1
mww [expr $addr + 0xe4] 0x50006404
# PBBPR -- burst priority
mww [expr $addr + 0x20] 0xfe
# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
mmw [expr $addr + 0x08] 0x00800000 0
mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
# SDTIMR0, SDTIMR1
mww [expr $addr + 0x10] 0x2a923249
mww [expr $addr + 0x14] 0x4c17c763
# SDCR -- relock SDTIM*
mmw [expr $addr + 0x08] 0 0x00008000
# SDRCR -- refresh rate (171 MHz * 7.8usec)
mww [expr $addr + 0x0c] 1336
########################
# ASYNC EMIF
set addr [dict get $dm355 a_emif]
# slow/pessimistic timings
set nand_timings 0x40400204
# fast (25% faster page reads)
#set nand_timings 0x0400008c
# AWCCR
mww [expr $addr + 0x04] 0xff
# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
mww [expr $addr + 0x10] $nand_timings
# CS1 == dm9000 Ethernet
mww [expr $addr + 0x14] 0x00a00505
# NANDFCR -- only CS0 has NAND
mww [expr $addr + 0x60] 0x01
# default: both chipselects to the NAND socket are used
nand probe 0
nand probe 1
########################
# UART0
set addr [dict get $dm355 uart0]
# PWREMU_MGNT -- rx + tx in reset
mww [expr $addr + 0x30] 0
# DLL, DLH -- 115200 baud
mwb [expr $addr + 0x20] 0x0d
mwb [expr $addr + 0x24] 0x00
# FCR - clear and disable FIFOs
mwb [expr $addr + 0x08] 0x07
mwb [expr $addr + 0x08] 0x00
# IER - disable IRQs
mwb [expr $addr + 0x04] 0x00
# LCR - 8-N-1
mwb [expr $addr + 0x0c] 0x03
# MCR - no flow control or loopback
mwb [expr $addr + 0x10] 0x00
# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
mww [expr $addr + 0x30] 0xe001
########################
# turn on icache - set I bit in cp15 register c1
arm mcr 15 0 0 1 0 0x00051078
}
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
#
# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
set _FLASHNAME $_CHIPNAME.boot
nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
set _FLASHNAME $_CHIPNAME.flash
nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
# FIXME
# - support writing UBL with its header (new layout only with new ROMs)
# - support writing ABL/U-Boot with its header (new layout)

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# DM365 EVM board -- Beta
# http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
# http://support.spectrumdigital.com/boards/evmdm365
source [find target/ti_dm365.cfg]
# NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
# connector, so it doesn't affect generation of the reset signal.
# Accordingly, resets require something else. ICEpick could do it;
# but its docs aren't generally available.
#
# At this writing, newer boards aren't available ... so assume no SRST.
# Also ICEpick docs aren't available ... so we must use watchdog reset,
# and hope the CPU isn't wedged or in a WFI loop (either of which can
# block access to CPU and thus watchdog registers).
reset_config trst_only
$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
# SW5.1 routes CS0: NAND vs OneNAND.
# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
# for boot-from-flash, those must agree with SW4.3:1 settings.
if { [info exists CS0MODE] } {
# NAND or OneNAND
set CS0 $CS0MODE
} else {
set CS0 ""
echo "WARNING: CS0 configuration not known"
proc cs0_setup {a_emif} {}
proc flashprobe {} {}
}
set a_emif [dict get $dm365 a_emif]
# As shipped: boot from NAND.
if { $CS0 == "NAND" } {
echo "CS0 NAND"
# NAND socket has two chipselects. Default MT29F16G08FAA chip
# has 1GByte on each one.
# NOTE: "hwecc4" here presumes that you're not updating anything
# that needs infix layout (e.g. UBL, old U-Boot, etc)
nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
proc cs0_setup {a_emif} {
global dm365
# 8 bit EMIF
davinci_pinmux $dm365 2 0x00000016
# slow/pessimistic timings
set nand_timings 0x40400204
# fast (25% faster page reads)
#set nand_timings 0x0400008c
# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
mww [expr $a_emif + 0x10] $nand_timings
# NANDFCR -- CS0 has NAND
mww [expr $a_emif + 0x60] 0x01
}
proc flashprobe {} {
nand probe 0
nand probe 1
}
} elseif { $CS0 == "OneNAND" } {
echo "CS0 OneNAND"
# No support for this OneNAND in OpenOCD (yet) or Linux ...
# REVISIT OneNAND timings not verified to work!
echo "WARNING -- OneNAND not yet tested!"
proc cs0_setup {a_emif} {
global dm365
# 16 bit EMIF
davinci_pinmux $dm365 2 0x00000055
# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
mww [expr $a_emif + 0x10] 0x00000001
# ONENANDCTRL -- CS0 has OneNAND, enable sync reads
mww [expr $a_emif + 0x5c] 0x0441
}
proc flashprobe {} { }
}
# NOTE: disable or replace this call to dm365evm_init if you're
# debugging new UBL/NANDboot code from SRAM.
$_TARGETNAME configure -event reset-init { dm365evm_init }
#
# This post-reset init is called when the MMU isn't active, all IRQs
# are disabled, etc. It should do most of what a UBL does, except for
# loading code (like U-Boot) into DRAM and running it.
#
proc dm365evm_init {} {
global dm365
echo "Initialize DM365 EVM board"
# CLKIN = 24 MHz ... can't talk quickly to ARM yet
adapter_khz 1500
# FIXME -- PLL init
########################
# PINMUX setup
davinci_pinmux $dm365 0 0x00fd0000
davinci_pinmux $dm365 1 0x00145555
# mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
davinci_pinmux $dm365 3 0x375affff
davinci_pinmux $dm365 4 0x55556555
########################
# PSC setup (minimal)
# DDR EMIF/13, AEMIF/14, UART0/19
psc_enable 13
psc_enable 14
psc_enable 19
psc_go
# FIXME setup DDR2 (needs PLL)
########################
# ASYNC EMIF
set a_emif [dict get $dm365 a_emif]
# AWCCR
mww [expr $a_emif + 0x04] 0xff
# CS0 == NAND or OneNAND
cs0_setup $a_emif
# CS1 == CPLD
mww [expr $a_emif + 0x14] 0x00a00505
# FIXME setup UART0
flashprobe
}

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# DM6446 EVM board
# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
# http://c6000.spectrumdigital.com/davincievm/
# EVM is just the board; buy that at Spectrum.
# The "kit" from TI also has: video camera, LCD video monitor, more.
source [find target/ti_dm6446.cfg]
# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
# S3.3 controls AEMIF bus width.
if { [info exists J4_OPTION] } {
# NOR, NAND, SRAM, ...
set CS2_MODE $J4_OPTION
} else {
set CS2_MODE ""
}
# ARM boot:
# S3.1 = 0, S3.2 = 0 ==> ROM/UBL boot via NAND (J4 == NAND)
# S3.1 = 1, S3.2 = 0 ==> AEMIF boot (J4 == NOR or SRAM)
# S3.1 = 0, S3.2 = 1 ==> ROM/UBL boot via HPI
# S3.1 = 1, S3.2 = 1 ==> ROM/UBL boot via UART (J4 == don't care)
# AEMIF bus width:
# S3.3 = 0 ==> 8 bit bus width
# S3.3 = 1 ==> 16 bit bus width
# DSP boot:
# S3.4 = 0 ==> controlled by ARM
if { $CS2_MODE == "NOR" } {
# 16 Mbytes address space; 16 bit bus width
# (older boards used 32MB parts, with upper 16 MB unusable)
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
proc flashprobe {} { flash probe 0 }
} elseif { $CS2_MODE == "NAND" } {
# 64 Mbyte small page; 8 bit bus width
nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
proc flashprobe {} { nand probe 0 }
} elseif { $CS2_MODE == "SRAM" } {
# 4 Mbyte address space; 16 bit bus width
# loaded via JTAG or HPI
proc flashprobe {} {}
} else {
# maybe it's HPI boot? can't tell...
echo "WARNING: CS2/flash configuration not recognized"
proc flashprobe {} {}
}
# NOTE: disable or replace this call to dm6446evm_init if you're
# debugging new UBL code from SRAM (for NAND boot).
$_TARGETNAME configure -event reset-init { dm6446evm_init }
#
# This post-reset init is called when the MMU isn't active, all IRQs
# are disabled, etc. It should do most of what a UBL does, except for
# loading code (like U-Boot) into DRAM and running it.
#
proc dm6446evm_init {} {
echo "Initialize DM6446 EVM board"
# FIXME initialize everything:
# - PLL1
# - PLL2
# - PINMUX
# - PSC
# - DDR
# - AEMIF
# - UART0
# - icache
flashprobe
}

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debuggers/openocd/tcl/board/efikamx.cfg Normal file
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# Genesi USA EfikaMX
# http://www.genesi-usa.com/products/efika
# Fall back to 6MHz if RTCK is not supported
jtag_rclk 6000
source [find target/imx51.cfg]
reset_config trst_only

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debuggers/openocd/tcl/board/eir.cfg Normal file
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# Elector Internet Radio board
# http://www.ethernut.de/en/hardware/eir/index.html
source [find target/sam7se512.cfg]
$_TARGETNAME configure -event reset-init {
# WDT_MR, disable watchdog
mww 0xFFFFFD44 0x00008000
# RSTC_MR, enable user reset
mww 0xfffffd08 0xa5000001
# CKGR_MOR
mww 0xFFFFFC20 0x00000601
sleep 10
# CKGR_PLLR
mww 0xFFFFFC2C 0x00481c0e
sleep 10
# PMC_MCKR
mww 0xFFFFFC30 0x00000007
sleep 10
# PMC_IER
mww 0xFFFFFF60 0x00480100
#
# Enable SDRAM interface.
#
# Enable SDRAM control at PIO A.
mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
# Enable address bus (A0, A2-A11, A13-A17) at PIO B
mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
# Enable 16 bit data bus at PIO C
mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
# Enable SDRAM chip select
mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
# Set SDRAM characteristics in configuration register.
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
sleep 10
# Issue 16 bit SDRAM command: NOP
mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Precharge all
mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 8 auto-refresh cycles
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000000
# Issue 16 bit SDRAM command: Set mode register
mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
mww 0x20000014 0xcafedede
# Set refresh rate count ???
mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
# Issue 16 bit SDRAM command: Normal mode
mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
mww 0x20000000 0x00000180
#
# Enable external reset key.
#
mww 0xfffffd08 0xa5000001
}

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debuggers/openocd/tcl/board/ek-lm3s1968.cfg Normal file
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#
# TI/Luminary Stellaris LM3S1968 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s1968
#
# NOTE: to use J-Link instead of the on-board interface,
# you may also need to reduce adapter_khz to be about 1200.
# source [find interface/jlink.cfg]
# include the FT2232 interface config for on-board JTAG interface
# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
# so is using in JTAG mode, as done here.
source [find interface/luminary.cfg]
# include the target config
set WORKAREASIZE 0x2000
set CHIPNAME lm3s1968
source [find target/stellaris.cfg]

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debuggers/openocd/tcl/board/ek-lm3s3748.cfg Normal file
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#
# TI/Luminary Stellaris lm3s3748 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s3748
#
# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
# so is using it in JTAG mode, as done here.
source [find interface/luminary.cfg]
# 20k working area
set WORKAREASIZE 0x4000
set CHIPNAME lm3s3748
source [find target/stellaris.cfg]

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#
# TI/Luminary Stellaris LM3S6965 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s6965
#
# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
# so is using it in JTAG mode, as done here.
source [find interface/luminary.cfg]
# 20k working area
set WORKAREASIZE 0x5000
set CHIPNAME lm3s6965
# include the target config
source [find target/stellaris.cfg]

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debuggers/openocd/tcl/board/ek-lm3s811-revb.cfg Normal file
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#
# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)
#
# http://www.ti.com/tool/ek-lm3s811
#
# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.
# use board/ek-lm3s811.cfg
source [find interface/luminary-lm3s811.cfg]
# include the target config
set WORKAREASIZE 0x2000
set CHIPNAME lm3s811
source [find target/stellaris.cfg]

15
debuggers/openocd/tcl/board/ek-lm3s811.cfg Normal file
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#
# TI/Luminary Stellaris LM3S811 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s811
#
# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
# so is using it in JTAG mode, as done here.
# NOTE: older '811-EK boards (before rev C) shouldn't use this.
source [find interface/luminary.cfg]
# include the target config
set WORKAREASIZE 0x2000
set CHIPNAME lm3s811
source [find target/stellaris.cfg]

15
debuggers/openocd/tcl/board/ek-lm3s8962.cfg Normal file
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#
# TI/Luminary Stellaris LM3S8962 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s8962
#
# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
# so is using it in JTAG mode, as done here.
source [find interface/luminary.cfg]
# 64k working area
set WORKAREASIZE 0x10000
set CHIPNAME lm3s8962
# include the target config
source [find target/stellaris.cfg]

14
debuggers/openocd/tcl/board/ek-lm3s9b9x.cfg Normal file
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#
# TI/Luminary Stellaris LM3S9B9x Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s9b90
# http://www.ti.com/tool/ek-lm3s9b92
#
# NOTE: using the bundled FT2232 JTAG/SWD/SWO interface is optional!
# so is using in JTAG mode, as done here.
source [find interface/luminary-icdi.cfg]
set WORKAREASIZE 0x4000
set CHIPNAME lm3s9b9x
source [find target/stellaris.cfg]

14
debuggers/openocd/tcl/board/ek-lm3s9d92.cfg Normal file
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#
# TI/Luminary Stellaris LM3S9D92 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm3s9d92
#
# NOTE: using the bundled FT2232 JTAG/SWD/SWO interface is optional!
# so is using in JTAG mode, as done here.
source [find interface/luminary-icdi.cfg]
# 64k working area
set WORKAREASIZE 0x10000
set CHIPNAME lm3s9d92
source [find target/stellaris.cfg]

15
debuggers/openocd/tcl/board/ek-lm4f120xl.cfg Normal file
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#
# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
#
# http://www.ti.com/tool/ek-lm4f120xl
#
#
# NOTE: using the bundled ICDI interface is optional!
# This interface is not ftdi based as previous boards were
#
source [find interface/ti-icdi.cfg]
set WORKAREASIZE 0x8000
set CHIPNAME lm4f120h5qr
source [find target/stellaris_icdi.cfg]

15
debuggers/openocd/tcl/board/ek-lm4f232.cfg Normal file
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#
# TI Stellaris LM4F232 Evaluation Kits
#
# http://www.ti.com/tool/ek-lm4f232
#
#
# NOTE: using the bundled ICDI interface is optional!
# This interface is not ftdi based as previous boards were
#
source [find interface/ti-icdi.cfg]
set WORKAREASIZE 0x8000
set CHIPNAME lm4f23x
source [find target/stellaris_icdi.cfg]

154
debuggers/openocd/tcl/board/embedded-artists_lpc2478-32.cfg Normal file
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# Embedded Artists eval board for LPC2478
# http://www.embeddedartists.com/
# Target device: LPC2478
set CCLK 72000
source [find target/lpc2478.cfg]
# Helper
#
proc read_register {register} {
set result ""
mem2array result 32 $register 1
return $result(0)
}
proc init_board {} {
# Delays on reset lines
adapter_nsrst_delay 500
jtag_ntrst_delay 1
# Adaptive JTAG clocking through RTCK.
#
jtag_rclk 20
global _TARGETNAME
global _CHIPNAME
# A working area will help speeding the flash programming
$_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
# Event handlers
#
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
jtag_rclk 20
}
$_TARGETNAME configure -event reset-init {
arm core_state arm
arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
arm7_9 fast_memory_access enable
# Peripheral clocks
mww 0xE01FC0C4 0x04280FFE ;# PCONP: (reset value)
# Map the user flash to the vector table area (0x00...0x3F)
mww 0xE01FC040 0x00000001 ;# MEMMAP: User flash
# Memory accelerator module
mww 0xE01FC004 0x00000003 ;# MAMTIM: 3 clock cycles
mww 0xE01FC000 0x00000002 ;# MAMCR: fully enabled
# Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
mww 0xE002C014 0x55010115 ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
# P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
# P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
mww 0xE002C018 0x55555555 ;# PINSEL6: P3.0...P3.15=D0...D15
mww 0xE002C01C 0x55555555 ;# PINSEL7: P3.16...P3.31=D16...D31
mww 0xE002C020 0x55555555 ;# PINSEL8: P4.0...P4.15=A0...A15
mww 0xE002C024 0x50051555 ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
# P4.25=WE, P4.30=CS0, P4.31=CS1
mww 0xFFE08000 0x00000001 ;# EMCControl: Enable EMC
# Start PLL, then use faster JTAG clock
enable_pll
jtag_rclk 3000
# 16-bit flash @ CS0 (SST39VF3201-70)
mww 0xFFE08200 0x00080081 ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
mww 0xFFE08204 0x00000000 ;# EMCStaticWaitWen0
mww 0xFFE08208 0x00000000 ;# EMCStaticWaitOen0
mww 0xFFE0820C 0x00000005 ;# EMCStaticWaitRd0
mww 0xFFE08210 0x00000005 ;# EMCStaticWaitPage0
mww 0xFFE08214 0x00000003 ;# EMCStaticWaitWr0
mww 0xFFE08218 0x00000001 ;# EMCStaticWaitTurn0
# 8-bit NAND @ CS1
# TODO
# 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
mww 0xFFE08028 0x00000001 ;# EMCDynamicReadConfig
mww 0xFFE08030 0x00000001 ;# EMCDynamicRP
mww 0xFFE08034 0x00000003 ;# EMCDynamicRAS
mww 0xFFE08038 0x00000005 ;# EMCDynamicSREX
mww 0xFFE0803C 0x00000001 ;# EMCDynamicAPR
mww 0xFFE08040 0x00000005 ;# EMCDynamicDAL
mww 0xFFE08044 0x00000001 ;# EMCDynamicWR
mww 0xFFE08048 0x00000005 ;# EMCDynamicRC
mww 0xFFE0804C 0x00000005 ;# EMCDynamicRFC
mww 0xFFE08050 0x00000005 ;# EMCDynamicXSR
mww 0xFFE08054 0x00000001 ;# EMCDynamicRRD
mww 0xFFE08058 0x00000001 ;# EMCDynamicMRD
#
mww 0xFFE08104 0x00000202 ;# EMCDynamicRasCas0
mww 0xFFE08100 0x00005488 ;# EMCDynamicConfig0
sleep 100
mww 0xFFE08020 0x00000183 ;# EMCDynamicControl: Clock on continuously, NOP
sleep 10
mww 0xFFE08020 0x00000103 ;# EMCDynamicControl: PRECHARGE-ALL
mww 0xFFE08024 0x00000046 ;# EMCDynamicRefresh
sleep 100
mww 0xFFE08020 0x00000083 ;# EMCDynamicControl: MODE
mdw 0xA0011000 1 ;# Set SDRAM mode register
mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL
mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
}
$_TARGETNAME configure -event gdb-attach {
# Without this gdb-attach will first time as probe will fail
reset init
}
}
# Enable the PLL.
# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
# Note: The PLL output runs at a frequency N times the desired CPU clock.
# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
# the initialization!
# Here: N=4
# Note that if the PLL is already active at the time this script is
# called, the effective value of N is the value of CCLKCFG at that time!
#
proc enable_pll {} {
# Disconnect PLL in case it is already connected
if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
# Disconnect it, but leave it enabled
# (This MUST be done in two steps)
mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
# Disable PLL (as it might already be enabled at this time!)
mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
# Setup PLL to generate 288 MHz from internal RC oscillator
mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
sleep 100
mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}

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debuggers/openocd/tcl/board/ethernut3.cfg Normal file
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#
# Ethernut 3 board configuration file
#
# http://www.ethernut.de/en/hardware/enut3/
# AT91R40008-66AU ARM7TDMI Microcontroller
# 256kB internal RAM
source [find target/at91r40008.cfg]
# AT49BV322A-70TU NOR Flash
# 2M x 16 mode at address 0x10000000
# Common flash interface supported
#
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
# Micrel MIC2775-29YM5 Supervisor
# Reset output will remain active for 280ms (maximum)
#
adapter_nsrst_delay 300
jtag_ntrst_delay 300
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
adapter_khz 16000
# Target events
#
$_TARGETNAME configure -event reset-init { board_init }
# Initialize board hardware
#
proc board_init { } {
board_remap
flash probe 0
}
# Memory remap
#
proc board_remap {{VERBOSE 0}} {
# CS0: NOR flash
# 16MB @ 0x10000000
# 16-bit data bus
# 4 wait states
#
mww 0xffe00000 0x1000212d
# CS1: Ethernet controller
# 1MB @ 0x20000000
# 16-bit data bus
# 2 wait states
# Byte select access
#
mww 0xffe00004 0x20003025
# CS2: CPLD registers
# 1MB @ 0x21000000
# 8-bit data bus
# 2 wait states
#
mww 0xffe00008 0x21002026
# CS3: Expansion bus
# 1MB @ 0x22000000
# 8-bit data bus
# 8 wait states
#
mww 0xffe00010 0x22002e3e
# Remap command
#
mww 0xffe00020 0x00000001
if {$VERBOSE != 0} {
echo "0x00000000 RAM"
echo "0x10000000 Flash"
echo "0x20000000 Ethernet"
echo "0x21000000 CPLD"
echo "0x22000000 Expansion"
}
}

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debuggers/openocd/tcl/board/glyn_tonga2.cfg Normal file
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#
# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
#
# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
#
# Hardware on the S0-DIMM module:
# - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
# - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
# - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
# - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
#
source [find target/tmpa900.cfg]
########################
# Target configuration #
########################
# Initial JTAG speed should not exceed 1/6 of the initial CPU clock
# frequency (24MHz). Be conservative and use 1/8 of the frequency.
# (24MHz / 8 = 3MHz)
adapter_khz 3000
$_TARGETNAME configure -event reset-start {
# Upon reset, set the JTAG frequency to 3MHz again, see above.
echo "Setting JTAG speed to 3MHz until clocks are initialized."
adapter_khz 3000
# Halt the CPU.
halt
# Disable faster memory access for now.
arm7_9 fast_memory_access disable
}
$_TARGETNAME configure -event reset-init {
# Setup clocks, and initialize SRAM and DDR SDRAM.
tonga2_init
# At this point the CPU is running at 192MHz, increase JTAG speed.
# Tests showed that 15MHz works OK, higher speeds can cause problems,
# though. Not sure if this is a CPU issue or JTAG adapter issue.
echo "Increasing JTAG speed to 15MHz."
adapter_khz 15000
# Enable faster memory access.
arm7_9 fast_memory_access enable
}
proc tonga2_init { } {
######################
# PLL initialization #
######################
# Clock overview (see datasheet chapter 3.5.2, page 57):
# - fs: Low-frequency oscillator
# - fOSCH: High-frequency oscillator (24MHz on this board)
# - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
# - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
# - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
#
# We select multiplier = 8 and gear = 1, so
# fFCLK = fOSCH * 8 / 1 = 192MHz.
# SYSCR3 (System Control Register 3): Disable and configure PLL.
# - PLL operation control: off
# - PLL constant value setting 1: always 0, as per datasheet
# - PLL constant value setting 2: x8 (multiplier = 8)
mww 0xf005000c 0x00000007
# SYSCR4 (System Control Register 4): Configure PLL.
# - PLL constant value setting 3: 140MHz or more
# - PLL constant value setting 4: always 1, as per datasheet
# - PLL constant value setting 5: 140MHz or more
mww 0xf0050010 0x00000065
# SYSCR3 (System Control Register 3): Enable PLL.
# - PLL operation control: on
# - All other bits remain set as above.
mww 0xf005000c 0x00000087
# Wait for PLL to stabilize.
sleep 10
# SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
# - Selection of the PLL output clock: fPLL
mww 0xf0050008 0x00000002
# SYSCR1 (System Control Register 1):
# - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
mww 0xf0050004 0x00000000
# CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
# says the bits are reserved, but also recommends "Write as one".
mww 0xf0050054 0x00000048
##############################################################
# Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
##############################################################
# PMC (Power Management Controller):
# PMCDRV (External Port "Driverbility" control register):
# Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
mww 0xf0020260 0x00000003 ;# Select 1.8V +/- 0.1V
# Setup DDR SDRAM timing parameters for our specific chip.
mww 0xf4310014 0x00000004 ;# cas_latency = 2
mww 0xf4310018 0x00000001 ;# t_dqss = 1
mww 0xf431001c 0x00000002 ;# t_mrd = 2
mww 0xf4310020 0x0000000a ;# t_ras = 10
mww 0xf4310024 0x0000000a ;# t_rc = 10
mww 0xf4310028 0x00000013 ;# t_rcd = 3, schedule_rcd = 2
mww 0xf431002c 0x0000010a ;# t_rfc = 10, schedule_rfc = 8
mww 0xf4310030 0x00000013 ;# t_rp = 3, schedule_rp = 2
mww 0xf4310034 0x00000002 ;# t_rrd = 2
mww 0xf4310038 0x00000002 ;# t_wr = 2
mww 0xf431003c 0x00000001 ;# t_wtr = 1
mww 0xf4310040 0x0000000a ;# t_xp = 10
mww 0xf4310044 0x0000000c ;# t_xsr = 12
mww 0xf4310048 0x00000014 ;# t_esr = 20
# dmc_memory_cfg_5 (DMC Memory Configuration register):
# Set memory configuration:
# column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
# auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
mww 0xf431000c 0x00010012
# dmc_user_config_5 (DMC user_config register):
# Data bus width of DDR SDRAM: 16 bit
mww 0xf4310304 0x00000058
# dmc_refresh_prd_5 (DMC Refresh Period register):
# Auto refresh: every 2656 (0xa60) DMCSCLK periods.
mww 0xf4310010 0x00000a60
# dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
# - SDRAM address structure: bank, row, column
# - address_match = 01000000 (start address [31:24])
# - address_mask = 11111100 (start address [31:24] mask value)
mww 0xf4310200 0x000140fc
# Initialize the DDR SDRAM chip.
# dmc_direct_cmd_5 (DMC Direct Command register).
# See datasheet chapter 3.10.5.1, page 268.
mww 0xf4310008 0x000c0000 ;# RAM init: NOP
mww 0xf4310008 0x00000000 ;# RAM init: Precharge all
mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh
mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh
mww 0xf4310008 0x00080032 ;# RAM init: addr_13_to_0 = 0x32
mww 0xf4310008 0x000c0000 ;# RAM init: NOP
mww 0xf4310008 0x000a0000 ;# RAM init: bank_addr = bank 2
# dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
# Set min./max. QoS values.
# - 0x5: Enable QoS, max. QoS = 1
# - 0xb: Enable QoS, min. QoS = 2
mww 0xf4310100 0x00000005 ;# AHB0: CPU Data
mww 0xf4310104 0x00000005 ;# AHB1: CPU Inst
mww 0xf4310108 0x0000000b ;# AHB2: LCDC
mww 0xf431010c 0x00000005 ;# AHB3: LCDDA, USB
mww 0xf4310110 0x00000005 ;# AHB4: DMA1
mww 0xf4310114 0x00000005 ;# AHB5: DMA2
# dmc_memc_cmd_5 (DMC Memory Controller Command register):
# Change DMC state to ready.
mww 0xf4310004 0x00000000 ;# memc_cmd = "Go"
# EBI: SMC Timeout register
mww 0xf00a0050 0x00000001 ;# smc_timeout = 1
########################################################
# Static Memory Controller (SMC) / SRAM initialization #
########################################################
# smc_set_cycles_5 (SMC Set Cycles register):
# tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
mww 0xf4311014 0x0004afaa
# smc_set_opmode_5 (SMC Set Opmode register):
# Memory data bus width = 16 bits, async read mode, read burst
# length = 1 beat, async write mode, write burst length = 1 beat,
# byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
# split setting = burst can cross any address boundary
mww 0xf4311018 0x00000001
# smc_direct_cmd_5 (SMC Direct Command register):
# cmd_type = UpdateRegs, chip_select = CS1
mww 0xf4311010 0x00c00000
echo "Clocks, SRAM, and DDR SDRAM are now initialized."
}
#######################
# Flash configuration #
#######################
# TODO: Implement NAND support.

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debuggers/openocd/tcl/board/hammer.cfg Normal file
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# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
# http://www.tincantools.com
source [find target/samsung_s3c2410.cfg]
$_TARGETNAME configure -event reset-init {
# Reset Script for the TinCanTools S3C2410 Based Hammer Module
# http://www.tincantools.com
#
# Setup primary clocks and initialize the SDRAM
mww 0x53000000 0x00000000
mww 0x4a000008 0xffffffff
mww 0x4a00000c 0x000007ff
mww 0x4c000000 0x00ffffff
mww 0x4c000014 0x00000003
mww 0x4c000004 0x000a1031
mww 0x48000000 0x11111122
mww 0x48000004 0x00000700
mww 0x48000008 0x00000700
mww 0x4800000c 0x00000700
mww 0x48000010 0x00000700
mww 0x48000014 0x00000700
mww 0x48000018 0x00000700
mww 0x4800001c 0x00018005
mww 0x48000020 0x00018005
mww 0x48000024 0x009c0459
mww 0x48000028 0x000000b2
mww 0x4800002c 0x00000030
mww 0x48000030 0x00000030
flash probe 0
}
#flash configuration
#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> [driver_options ...]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 $_TARGETNAME

40
debuggers/openocd/tcl/board/hilscher_nxdb500sys.cfg Normal file
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################################################################################
# Author: Michael Trensch (MTrensch@googlemail.com)
################################################################################
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
adapter_nsrst_delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME configure -event reset-init {
halt
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
sdram_fix
puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
mww 0x00100140 0
mww 0x00100144 0x03C13261
mww 0x00100140 0x030D0121
puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)"
mww 0x00100100 0x0201000E
flash probe 0
}
#####################
# Flash configuration
#####################
#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME
init
reset init

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debuggers/openocd/tcl/board/hilscher_nxeb500hmi.cfg Normal file
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################################################################################
# Author: Michael Trensch (MTrensch@googlemail.com)
################################################################################
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
adapter_nsrst_delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME configure -event reset-init {
halt
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads disable
sdram_fix
puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
mww 0x00100140 0
mww 0x00100144 0x03C23251
mww 0x00100140 0x030D0111
puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)"
mww 0x00100100 0x0101000E
flash probe 0
}
#####################
# Flash configuration
#####################
#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
init
reset init

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debuggers/openocd/tcl/board/hilscher_nxhx10.cfg Normal file
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################################################################################
# Author: Michael Trensch (MTrensch@googlemail.com)
################################################################################
source [find target/hilscher_netx10.cfg]
# Usually it is not needed to set srst_pulls_trst
# but sometimes it does not work without it. If you encounter
# problems try to line below
# reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst
adapter_nsrst_delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
# Par. Flash can only be accessed if DIP switch on the board is set in proper
# position and init_sdrambus was called. Don't call these functions if the DIP
# switch is in invalid position, as some outputs may collide. This is why this
# function is not called automatically
proc flash_init { } {
puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
mww 0x101C0100 0x01010008
flash probe 0
}
proc mread32 {addr} {
set value(0) 0
mem2array value 32 $addr 1
return $value(0)
}
proc init_clocks { } {
puts "Enabling all clocks "
set accesskey [mread32 0x101c0070]
mww 0x101c0070 [expr $accesskey]
mww 0x101c0028 0x00007511
}
proc init_sdrambus { } {
puts "Initializing external SDRAM Bus 16 Bit "
set accesskey [mread32 0x101c0070]
mww 0x101c0070 [expr $accesskey]
mww 0x101c0C40 0x00000050
puts "Configuring SDRAM controller for K4S561632E (32MB) "
mww 0x101C0140 0
sleep 100
#mww 0x101C0144 0x00a13262
mww 0x101C0144 0x00a13251
mww 0x101C0148 0x00000033
mww 0x101C0140 0x030d0121
}
$_TARGETNAME configure -event reset-init {
halt
wait_halt 1000
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
init_clocks
# init_sdrambus
puts ""
puts "-------------------------------------------------"
puts "Call 'init_clocks' to enable all clocks"
puts "Call 'init_sdrambus' to enable external SDRAM bus"
puts "-------------------------------------------------"
}
#####################
# Flash configuration
#####################
#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
init
reset init

40
debuggers/openocd/tcl/board/hilscher_nxhx50.cfg Normal file
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################################################################################
# Author: Michael Trensch (MTrensch@googlemail.com)
################################################################################
source [find target/hilscher_netx50.cfg]
reset_config trst_and_srst
adapter_nsrst_delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME configure -event reset-init {
halt
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
sdram_fix
puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
mww 0x1C000140 0
mww 0x1C000144 0x00A12151
mww 0x1C000140 0x030D0001
puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
mww 0x1C000100 0x01010008
flash probe 0
}
#####################
# Flash configuration
#####################
#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
init
reset init

42
debuggers/openocd/tcl/board/hilscher_nxhx500.cfg Normal file
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################################################################################
# Author: Michael Trensch (MTrensch@googlemail.com)
################################################################################
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
adapter_nsrst_delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME configure -event reset-init {
halt
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
sleep 100
sdram_fix
puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
mww 0x00100140 0
mww 0x00100144 0x03C23251
mww 0x00100140 0x030D0001
puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
mww 0x00100100 0x01010008
flash probe 0
}
#####################
# Flash configuration
#####################
#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
init
reset init

29
debuggers/openocd/tcl/board/hilscher_nxsb100.cfg Normal file
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################################################################################
# Author: Michael Trensch (MTrensch@googlemail.com)
################################################################################
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
adapter_nsrst_delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME configure -event reset-init {
halt
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
sdram_fix
puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
mww 0x00100140 0
mww 0x00100144 0x03C23251
mww 0x00100140 0x030D0001
}
init
reset init

15
debuggers/openocd/tcl/board/hitex_lpc1768stick.cfg Normal file
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# Hitex LPC1768 Stick
#
# http://www.hitex.com/?id=1602
#
reset_config trst_and_srst
source [find interface/ftdi/hitex_lpc1768stick.cfg]
source [find target/lpc1768.cfg]
# startup @ 500kHz
adapter_khz 500

106
debuggers/openocd/tcl/board/hitex_lpc2929.cfg Normal file
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# Hitex eval board for LPC2929/LPC2939
# http://www.hitex.com/
# Delays on reset lines
adapter_nsrst_delay 50
jtag_ntrst_delay 1
# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# Adaptive clocking through RTCK is not supported.
adapter_khz 2000
# Target device: LPC29xx with ETB
# The following variables are used by the LPC2900 script:
# HAS_ETB Must be set to 1. The CPU on this board has ETB.
# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz)
set HAS_ETB 1
set FLASH_CLOCK 112000
source [find target/lpc2900.cfg]
# A working area will help speeding the flash programming
#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
# Event handlers
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
adapter_khz 2000
}
# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
set _FLASHNAME $_CHIPNAME.extflash
flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
$_TARGETNAME configure -event reset-init {
# Flash
mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
# Use PLL
mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
mww 0xFFFF8070 0x01000000 ;# SYS_CLK_CONF: Crystal
mww 0xFFFF8028 0x00000005 ;# PLL: (power down)
mww 0xFFFF8028 0x01060004 ;# PLL: M=7, 2P=2 (power up)
# --> f=112 MHz, fcco=224 MHz
sleep 100
mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
# Increase JTAG speed
adapter_khz 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
mww 0xE0001138 0x0000001F ;# P1.14 = D0
mww 0xE000113C 0x0000001F ;# P1.15 = D1
mww 0xE0001140 0x0000001F ;# P1.16 = D2
mww 0xE0001144 0x0000001F ;# P1.17 = D3
mww 0xE0001148 0x0000001F ;# P1.18 = D4
mww 0xE000114C 0x0000001F ;# P1.19 = D5
mww 0xE0001150 0x0000001F ;# P1.20 = D6
mww 0xE0001154 0x0000001F ;# P1.21 = D7
mww 0xE0001200 0x0000001F ;# P2.0 = D8
mww 0xE0001204 0x0000001F ;# P2.1 = D9
mww 0xE0001208 0x0000001F ;# P2.2 = D10
mww 0xE000120C 0x0000001F ;# P2.3 = D11
mww 0xE0001210 0x0000001F ;# P2.4 = D12
mww 0xE0001214 0x0000001F ;# P2.5 = D13
mww 0xE0001218 0x0000001F ;# P2.6 = D14
mww 0xE000121C 0x0000001F ;# P2.7 = D15
mww 0xE0001104 0x00000007 ;# P1.1 = A1
mww 0xE0001108 0x00000007 ;# P1.2 = A2
mww 0xE000110C 0x00000007 ;# P1.3 = A3
mww 0xE0001110 0x00000007 ;# P1.4 = A4
mww 0xE0001114 0x00000007 ;# P1.5 = A5
mww 0xE0001118 0x00000007 ;# P1.6 = A6
mww 0xE000111C 0x00000007 ;# P1.7 = A7
mww 0xE0001028 0x00000007 ;# P0.10 = A8
mww 0xE000102C 0x00000007 ;# P0.11 = A9
mww 0xE0001030 0x00000007 ;# P0.12 = A10
mww 0xE0001034 0x00000007 ;# P0.13 = A11
mww 0xE0001038 0x00000007 ;# P0.14 = A12
mww 0xE000103C 0x00000007 ;# P0.15 = A13
mww 0xE0001048 0x00000007 ;# P0.18 = A14
mww 0xE000104C 0x00000007 ;# P0.19 = A15
mww 0xE0001050 0x00000007 ;# P0.20 = A16
mww 0xE0001054 0x00000007 ;# P0.21 = A17
mww 0xE0001058 0x00000007 ;# P0.22 = A18
mww 0xE000105C 0x00000007 ;# P0.23 = A19
mww 0xE0001238 0x00000007 ;# P2.14 = BLS0
mww 0xE000123C 0x00000007 ;# P2.15 = BLS1
mww 0xE0001300 0x00000007 ;# P3.0 = CS6
mww 0xE0001304 0x00000007 ;# P3.1 = CS7
mww 0xE0001130 0x00000007 ;# P1.12 = OE_N
mww 0xE0001134 0x00000007 ;# P1.13 = WE_N
mww 0x600000BC 0x00000041 ;# Bank6 16-bit mode, RBLE=1
mww 0x600000B4 0x00000000 ;# Bank6 WSTOEN=0
mww 0x600000AC 0x00000005 ;# Bank6 WST1=5
mww 0x600000B8 0x00000001 ;# Bank6 WSTWEN=1
mww 0x600000B0 0x00000006 ;# Bank6 WST2=6
mww 0x600000A8 0x00000002 ;# Bank6 IDCY=2
mww 0x600000D8 0x00000041 ;# Bank7 16-bit mode, RBLE=1
mww 0x600000D0 0x00000000 ;# Bank7 WSTOEN=0
mww 0x600000C8 0x0000000A ;# Bank7 WST1=10
mww 0x600000D4 0x00000001 ;# Bank7 WSTWEN=1
mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2
}

16
debuggers/openocd/tcl/board/hitex_stm32-performancestick.cfg Normal file
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# Hitex stm32 performance stick
reset_config trst_and_srst
source [find interface/stm32-stick.cfg]
set CHIPNAME stm32_hitex
source [find target/stm32f1x.cfg]
# configure str750 connected to jtag chain
# FIXME -- source [find target/str750.cfg] after cleaning that up
jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
# for some reason this board like to startup @ 500kHz
adapter_khz 500

79
debuggers/openocd/tcl/board/hitex_str9-comstick.cfg Normal file
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# Hitex STR9-comStick
# http://www.hitex.com/index.php?id=383
# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
source [find interface/hitex_str9-comstick.cfg]
# set jtag speed
adapter_khz 3000
adapter_nsrst_delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
#
# FIXME use the standard str912 target config; that script might need
# updating to "-ignore-version" for the boundary scan TAP
#
# source [find target/str912.cfg]
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME str912
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists FLASHTAPID] } {
set _FLASHTAPID $FLASHTAPID
} else {
set _FLASHTAPID 0x04570041
}
jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x25966041
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
if { [info exists BSTAPID] } {
set _BSTAPID $BSTAPID
} else {
# Found on STR9-comStick, revision STR912CS-A1
set _BSTAPID1 0x1457f041
# Found on STR9-comStick, revision STR912CS-A2
set _BSTAPID2 0x2457f041
}
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
#jtag_rclk 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
mww 0x5C002034 0x0191
str9x flash_config 0 4 2 0 0x80000
flash protect 0 0 7 off
}
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
#flash bank <driver> <base> <size> <chip_width> <bus_width>
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0

17
debuggers/openocd/tcl/board/iar_lpc1768.cfg Normal file
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# Board from IAR KickStart Kit for LPC1768
# See www.iar.com and also
# http://www.olimex.com/dev/lpc-1766stk.html
#
source [find target/lpc1768.cfg]
# The chip has just been reset.
#
$_TARGETNAME configure -event reset-init {
# FIXME update the core clock to run at 100 MHz;
# and update JTAG clocking similarly; then
# make CCLK match,
flash probe 0
}

3
debuggers/openocd/tcl/board/iar_str912_sk.cfg Normal file
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# The IAR str912-sk evaluation kick start board has an str912
source [find target/str912.cfg]

444
debuggers/openocd/tcl/board/icnova_imx53_sodimm.cfg Normal file
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#################################################################################################
# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
# Kiwigrid GmbH ;#
# Generated for In-Circuit i.MX53 SO-Dimm ;#
#################################################################################################
# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
source [find target/imx53.cfg]
# Helper for common memory read/modify/write procedures
source [find mem_helper.tcl]
echo "i.MX53 SO-Dimm board lodaded."
# Set reset type
#reset_config srst_only
adapter_khz 3000
$_TARGETNAME configure -event "reset-assert" {
echo "Reseting ...."
#cortex_a dbginit
}
$_TARGETNAME configure -event reset-init { sodimm_init }
global AIPS1_BASE_ADDR
set AIPS1_BASE_ADDR 0x53F00000
global AIPS2_BASE_ADDR
set AIPS2_BASE_ADDR 0x63F00000
proc sodimm_init { } {
echo "Reset-init..."
; # halt the CPU
halt
echo "HW version [format %x [mrw 0x48]]"
dap apsel 1
DCD
; # ARM errata ID #468414
set tR [arm mrc 15 0 1 0 1]
arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
init_l2cc
init_aips
init_clock
dap apsel 0
; # Force ARM state
; #reg cpsr 0x000001D3
arm core_state arm
jtag_rclk 3000
# adapter_khz 3000
}
# L2CC Cache setup/invalidation/disable
proc init_l2cc { } {
; #/* explicitly disable L2 cache */
; #mrc 15, 0, r0, c1, c0, 1
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
; #add r0, r0, #0x4 /* data RAM */
; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
; #orr r0, r0, #(1 << 22) /* disable write allocate */
; #mcr 15, 1, r0, c9, c0, 2
arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
}
# AIPS setup - Only setup MPROTx registers.
# The PACR default values are good.
proc init_aips { } {
; # Set all MPROTx to be non-bufferable, trusted for R/W,
; # not forced to user-mode.
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
set VAL 0x77777777
# dap apsel 1
mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
# dap apsel 0
}
proc init_clock { } {
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
set CLKCTL_CCSR 0x0C
set CLKCTL_CBCDR 0x14
set CLKCTL_CBCMR 0x18
set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
set CLKCTL_CSCMR1 0x1C
set CLKCTL_CDHIPR 0x48
set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
set CLKCTL_CSCDR1 0x24
set CLKCTL_CCDR 0x04
; # Switch ARM to step clock
mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
return
echo "not returned"
setup_pll $PLL1_BASE_ADDR 800
setup_pll $PLL3_BASE_ADDR 400
; # Switch peripheral to PLL3
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
setup_pll $PLL2_BASE_ADDR 400
; # Switch peripheral to PLL2
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
; # change uart clk parent to pll2
mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
; # make sure change is effective
while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
setup_pll $PLL3_BASE_ADDR 216
setup_pll $PLL4_BASE_ADDR 455
; # Set the platform clock dividers
mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
mww [expr $CCM_BASE_ADDR + 0x10] 0
; # Switch ARM back to PLL 1.
mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
; # make uart div=6
mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
; # Restore the default values in the Gate registers
mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
; # for cko - for ARM div by 8
mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
}
proc setup_pll { PLL_ADDR CLK } {
set PLL_DP_CTL 0x00
set PLL_DP_CONFIG 0x04
set PLL_DP_OP 0x08
set PLL_DP_HFS_OP 0x1C
set PLL_DP_MFD 0x0C
set PLL_DP_HFS_MFD 0x20
set PLL_DP_MFN 0x10
set PLL_DP_HFS_MFN 0x24
if {$CLK == 1000} {
set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (12 - 1)]
set DP_MFN 5
} elseif {$CLK == 850} {
set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (48 - 1)]
set DP_MFN 41
} elseif {$CLK == 800} {
set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (3 - 1)]
set DP_MFN 1
} elseif {$CLK == 700} {
set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (24 - 1)]
set DP_MFN 7
} elseif {$CLK == 600} {
set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (4 - 1)]
set DP_MFN 1
} elseif {$CLK == 665} {
set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (96 - 1)]
set DP_MFN 89
} elseif {$CLK == 532} {
set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (24 - 1)]
set DP_MFN 13
} elseif {$CLK == 455} {
set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
set DP_MFD [expr (48 - 1)]
set DP_MFN 71
} elseif {$CLK == 400} {
set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
set DP_MFD [expr (3 - 1)]
set DP_MFN 1
} elseif {$CLK == 216} {
set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
set DP_MFD [expr (4 - 1)]
set DP_MFN 3
} else {
error "Error (setup_dll): clock not found!"
}
mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
}
proc CPU_2_BE_32 { L } {
return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
}
# Device Configuration Data
proc DCD { } {
# dap apsel 1
#*========================================================================================== ======
# Initialization script for 32 bit DDR3 (CS0+CS1)
#*========================================================================================== ======
# Remux D24/D25 to perform Flash-access
mww 0x53fa818C 0x00000000 ; #EIM_RW
mww 0x53fa8180 0x00000000 ; #EIM_CS0
mww 0x53fa8188 0x00000000 ; #EIM_OE
mww 0x53fa817C 0x00000000 ; #A16
mww 0x53fa8178 0x00000000 ; #A17
mww 0x53fa8174 0x00000000 ; #A18
mww 0x53fa8170 0x00000000 ; #A19
mww 0x53fa816C 0x00000000 ; #A20
mww 0x53fa8168 0x00000000 ; #A21
mww 0x53fa819C 0x00000000 ; #DA0
mww 0x53fa81A0 0x00000000 ; #DA1
mww 0x53fa81A4 0x00000000 ; #DA2
mww 0x53fa81A8 0x00000000 ; #DA3
mww 0x53fa81AC 0x00000000 ; #DA4
mww 0x53fa81B0 0x00000000 ; #DA5
mww 0x53fa81B4 0x00000000 ; #DA6
mww 0x53fa81B8 0x00000000 ; #DA7
mww 0x53fa81BC 0x00000000 ; #DA8
mww 0x53fa81C0 0x00000000 ; #DA9
mww 0x53fa81C4 0x00000000 ; #DA10
mww 0x53fa81C8 0x00000000 ; #DA11
mww 0x53fa81CC 0x00000000 ; #DA12
mww 0x53fa81D0 0x00000000 ; #DA13
mww 0x53fa81D4 0x00000000 ; #DA14
mww 0x53fa81D8 0x00000000 ; #DA15
mww 0x53fa8118 0x00000000 ; #D16
mww 0x53fa811C 0x00000000 ; #D17
mww 0x53fa8120 0x00000000 ; #D18
mww 0x53fa8124 0x00000000 ; #D19
mww 0x53fa8128 0x00000000 ; #D20
mww 0x53fa812C 0x00000000 ; #D21
mww 0x53fa8130 0x00000000 ; #D22
mww 0x53fa8134 0x00000000 ; #D23
mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
mww 0x53fa8144 0x00000000 ; #D26
mww 0x53fa8148 0x00000000 ; #D27
mww 0x53fa814C 0x00000000 ; #D28
mww 0x53fa8150 0x00000000 ; #D29
mww 0x53fa8154 0x00000000 ; #D30
mww 0x53fa8158 0x00000000 ; #D31
# DDR3 IOMUX configuration
#* Global pad control options */
mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
# mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
# mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
# mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
# mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
# mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
#* Data bus byte lane pad drive strength control options */
# mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
# mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
# mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
# mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
# mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
# mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
# mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
# mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
# mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
# mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
# mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
# mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
#* SDCLK pad drive strength control options */
# mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
# mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
#* Control and addr bus pad drive strength control options */
# mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
# mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
# mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
# mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
# mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
# mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
# Initialize DDR3 memory - Micron MT41J128M16-187Er
#** Keep for now, same setting as CPU3 board **#
mww 0x63fd901c 0x00008000
# mww 0x63fd904c 0x01680172 ; #write leveling reg 0
# mww 0x63fd9050 0x0021017f ; #write leveling reg 1
mww 0x63fd9088 0x32383535 ; #read delay lines
mww 0x63fd9090 0x40383538 ; #write delay lines
# mww 0x63fd90F8 0x00000800 ; #Measure unit
mww 0x63fd907c 0x0136014d ; #DQS gating 0
mww 0x63fd9080 0x01510141 ; #DQS gating 1
#* CPU3 Board settingr
# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
# mww 0x63fd9018 0x00091740 ; #Misc register:
#* Quick Silver board setting
# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
mww 0x63fd9018 0x00011740 ; #Misc register
# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
# mww 0x63fd9000 0xc3190000 ; #Main control register
# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
mww 0x63fd9000 0x83190000 ; #Main control register
# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
mww 0x63fd902c 0x000026d2 ; #command delay (default)
mww 0x63fd9030 0x009f0e21 ; #out of reset delays
# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
mww 0x63fd9008 0x12273030 ; #ODT timings
# tCKE=3; tCKSRX=5; tCKSRE=5
mww 0x63fd9004 0x0002002d
#Power down control
#**********************************
#DDR device configuration:
#**********************************
#**********************************
# CS0:
#**********************************
mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
# Full array self refresh
# Rtt_WR disabled (no ODT at IO CMOS operation)
# Manual self refresh
# CWS=5
mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
# out impedance = RZQ/7
# Rtt_nom disabled (no ODT at IO CMOS operation)
# Aditive latency off
# write leveling disabled
# tdqs (differential?) disabled
mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
#**********************************
# CS1:
#**********************************
# mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
# mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
# mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
# mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
# mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
#**********************************
mww 0x63fd9020 0x00001800 ; # Refresh control register
mww 0x63fd9040 0x04b80003 ; # ZQ HW control
mww 0x63fd9058 0x00022227 ; # ODT control register
mww 0x63fd901c 0x00000000
# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
# mww 0x53FA8314 = 0
# mww 0x53FA8320 0x4
# mww 0x53FD4060 0x01e900f0
# dap apsel 0
}
# IRAM
$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
# vim:filetype=tcl

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#################################################################################################
# #
# Author: Lars Poeschel (larsi@wh2.tu-dresden.de) #
# Generated for In-Circuit ICnova SAM9G45 SODIMM #
# http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova #
# #
#################################################################################################
# FIXME use some standard target config, maybe create one from this
#
# source [find target/...cfg]
source [find target/at91sam9g45.cfg]
# Set reset type.
# reset_config trst_and_srst
# adapter_nsrst_delay 200
# jtag_ntrst_delay 200
# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
# some powerful features, we want to have a special function that handles "reset init". To do this we declare
# an event handler where these special activities can take place.
scan_chain
$_TARGETNAME configure -event reset-init {at91sam9g45_init}
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
# Slow-speed oscillator enabled at reset, so run jtag speed slow.
$_TARGETNAME configure -event reset-start {at91sam9g45_start}
# NandFlash configuration and definition
# Future TBD
# Flash configuration
# flash bank cfi <base> <size> <chip width> <bus width> <target#>
set _FLASHNAME $_CHIPNAME.flash
# set _NANDNAME $_CHIPNAME.nand
flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800
proc read_register {register} {
set result ""
mem2array result 32 $register 1
return $result(0)
}
proc at91sam9g45_start { } {
# Make sure that the the jtag is running slow, since there are a number of different ways the board
# can be configured coming into this state that can cause communication problems with the jtag
# adapter. Also since this call can be made following a "reset init" where fast memory accesses
# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
# jtag speed without causing GDB keep alive problem.
arm7_9 fast_memory_access disable
# Slow-speed oscillator enabled at reset, so run jtag speed slow.
adapter_khz 4
# Make sure processor is halted, or error will result in following steps.
halt
wait_halt 10000
# RSTC_MR : enable user reset.
mww 0xfffffd08 0xa5000501
}
proc at91sam9g45_init { } {
# At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
# a number of steps that must be carefully performed. The process outline below follows the
# recommended procedure outlined in the AT91SAM9G45 technical manual.
#
# Several key and very important things to keep in mind:
# The SDRAM parts used currently on the board are -75 grade parts. This
# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
# Make sure processor is halted, or error will result in following steps.
halt
# RSTC_MR : enable user reset.
mww 0xfffffd08 0xa5000501
# WDT_MR : disable watchdog.
mww 0xfffffd44 0x00008000
# Enable the main 15.000 MHz oscillator in CKGR_MOR register.
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
#mww 0xfffffc28 0x202a3f01
mww 0xfffffc28 0x20c73f03
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert.
#mww 0xfffffc30 0x00000101
mww 0xfffffc30 0x00001301
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz
# -> PCLK = 396.288 MHz
# Switch over to adaptive clocking.
adapter_khz 6000
# Enable faster DCC downloads.
arm7_9 dcc_downloads enable
# To be able to use external SDRAM, several peripheral configuration registers must
# be modified. The first change is made to PIO_ASR to select peripheral functions
# for D15 through D31. The second change is made to the PIO_PDR register to disable
# this for D15 through D31.
# mww 0xfffff870 0xffff0000
# mww 0xfffff804 0xffff0000
# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
# using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
# mww 0xffffef1c 0x000100a
# The ICnova SAM9G45 SODIMM has built-in NandFlash. The exact physical timing characteristics
# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
# four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
# mww 0xffffec30 0x00020002
# mww 0xffffec34 0x04040404
# mww 0xffffec38 0x00070007
# mww 0xffffec3c 0x00030003
# Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
# nand probe 0
# SMC_SETUP0 : Setup SMC for NOR Flash
mww 0xffffe800 0x0012000a
# SMC_PULSE0
mww 0xffffe804 0x3b38343b
# SMC_CYCLE0
mww 0xffffe808 0x003f003f
# SMC_MODE0
mww 0xffffe80c 0x00001000
# Identify flash bank 0
flash probe 0
# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
# are based on 2 x Samsung K4T51083QG memory.
# 0. Enable DDR2 Clock
mww 0xfffffc00 0x4
# 1. Program memory device type
# 1.1 configure the DDR controller
mww 0xffffe620 0x16
# 1.2 program the DDR controller
mww 0xffffe608 0x3d
# 2. program memory device features
# 2.1 assume timings for 7.5ns min clock period
mww 0xffffe60c 0x21128226
# 2.2 pSDDRC->HDDRSDRC2_T1PR
mww 0xffffe610 0x02c8100e
# 2.3 pSDDRC->HDDRSDRC2_T2PR
mww 0xffffe614 0x01000702
# 3. NOP
mww 0xffffe600 0x1
mww 0x70000000 0x1
# 3.1 delay 200us
sleep 1
# jim tcl alternative: after ms
# after 0.2
# 4. NOP
mww 0xffffe600 0x1
mww 0x70000000 0x1
# 4.1 delay 400ns
# 5. set all bank precharge
mww 0xffffe600 0x2
mww 0x70000000 0x1
# 5.1 delay 400ns
# 6. set EMR operation (EMRS2)
mww 0xffffe600 0x5
mww 0x74000000 0x1
# 6.1 delay 2 cycles
# 7. set EMR operation (EMRS3)
mww 0xffffe600 0x5
mww 0x76000000 0x1
# 7.1 delay 2 cycles
# 8. set EMR operation (EMRS1)
mww 0xffffe600 0x5
mww 0x72000000 0x1
# 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s)
sleep 1
# 9. Enable DLL Reset (set DLL bit)
set CR [expr [read_register 0xffffe608] | 0x80]
mww 0xffffe608 $CR
# 10. mode register cycle to reset the DLL
mww 0xffffe600 0x5
mww 0x70000000 0x1
# 10.1 delay 2 cycles
# 11. set all bank precharge
mww 0xffffe600 0x2
mww 0x70000000 0x1
# 11.1 delay 400 ns
# 12. two auto-refresh (CBR) cycles are provided.
mww 0xffffe600 0x4
mww 0x70000000 0x1
# 12.1 delay 10 cycles
# 12.2 2nd cycle (schreiben des Mode Register sparen wir uns)
mww 0x70000000 0x1
# 12.3 delay 10 cycles
# 13. disable DLL reset (clear DLL bit)
set CR [expr [read_register 0xffffe608] & 0xffffff7f]
mww 0xffffe608 $CR
# 14. mode register set cycle
mww 0xffffe600 0x3
mww 0x70000000 0x1
# 15. program OCD field (set OCD bits)
set CR [expr [read_register 0xffffe608] | 0x7000]
mww 0xffffe608 $CR
# 16. (EMRS1)
mww 0xffffe600 0x5
mww 0x72000000 0x1
# 16.1 delay 2 cycles
# 17. disable OCD field (clear OCD bits)
set CR [expr [read_register 0xffffe608] & 0xffff8fff]
mww 0xffffe608 $CR
# 18. (EMRS1)
mww 0xffffe600 0x5
mww 0x76000000 0x1
# 18.1 delay 2 cycles
# 19. normal mode command
mww 0xffffe600 0x0
mww 0x70000000 0x1
# 20. perform write to any address
#mww 0x70000000 0x1
# 21. write refresh rate into the count field of the refresh rate register
mww 0xffffe604 0x24b
# 21.1 delay (500 * 6 cycles)
arm7_9 fast_memory_access enable
}

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# The IMX27 ADS eval board has a single IMX27 chip
# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
source [find target/imx27.cfg]
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { imx27ads_init }
# The IMX27 ADS board has a NOR flash on CS0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
proc imx27ads_init { } {
# This setup puts RAM at 0xA0000000
# reset the board correctly
reset run
reset halt
mww 0x10000000 0x20040304
mww 0x10020000 0x00000000
mww 0x10000004 0xDFFBFCFB
mww 0x10020004 0xFFFFFFFF
sleep 100
# ========================================
# Configure DDR on CSD0 -- initial reset
# ========================================
mww 0xD8001010 0x00000008
# ========================================
# Configure PSRAM on CS5
# ========================================
mww 0xd8002050 0x0000dcf6
mww 0xd8002054 0x444a4541
mww 0xd8002058 0x44443302
# ========================================
# Configure16 bit NorFlash on CS0
# ========================================
mww 0xd8002000 0x0000CC03
mww 0xd8002004 0xa0330D01
mww 0xd8002008 0x00220800
# ========================================
# Configure CPLD on CS4
# ========================================
mww 0xd8002040 0x0000DCF6
mww 0xd8002044 0x444A4541
mww 0xd8002048 0x44443302
# ========================================
# Configure DDR on CSD0 -- wait 5000 cycle
# ========================================
mww 0x10027828 0x55555555
mww 0x10027830 0x55555555
mww 0x10027834 0x55555555
mww 0x10027838 0x00005005
mww 0x1002783C 0x15555555
mww 0xD8001010 0x00000004
mww 0xD8001004 0x00795729
mww 0xD8001000 0x92200000
mww 0xA0000F00 0x0
mww 0xD8001000 0xA2200000
mww 0xA0000F00 0x0
mww 0xA0000F00 0x0
mww 0xD8001000 0xB2200000
mwb 0xA0000033 0xFF
mwb 0xA1000000 0xAA
mww 0xD8001000 0x82228085
}

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debuggers/openocd/tcl/board/imx27lnst.cfg Normal file
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# The Linuxstamp-mx27 is board has a single IMX27 chip
# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
source [find target/imx27.cfg]
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { imx27lnst_init }
proc imx27lnst_init { } {
# This setup puts RAM at 0xA0000000
# reset the board correctly
adapter_khz 500
reset run
reset halt
mww 0x10000000 0x20040304
mww 0x10020000 0x00000000
mww 0x10000004 0xDFFBFCFB
mww 0x10020004 0xFFFFFFFF
sleep 100
# ========================================
# Configure DDR on CSD0 -- initial reset
# ========================================
mww 0xD8001010 0x00000008
sleep 100
# ========================================
# Configure DDR on CSD0 -- wait 5000 cycle
# ========================================
mww 0x10027828 0x55555555
mww 0x10027830 0x55555555
mww 0x10027834 0x55555555
mww 0x10027838 0x00005005
mww 0x1002783C 0x15555555
mww 0xD8001010 0x00000004
mww 0xD8001004 0x00795729
#mww 0xD8001000 0x92200000
mww 0xD8001000 0x91120000
mww 0xA0000F00 0x0
#mww 0xD8001000 0xA2200000
mww 0xD8001000 0xA1120000
mww 0xA0000F00 0x0
mww 0xA0000F00 0x0
#mww 0xD8001000 0xB2200000
mww 0xD8001000 0xB1120000
mwb 0xA0000033 0xFF
mwb 0xA1000000 0xAA
#mww 0xD8001000 0x82228085
mww 0xD8001000 0x81128080
}

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debuggers/openocd/tcl/board/imx28evk.cfg Normal file
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# The IMX28EVK eval board has a IMX28 chip
# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD
# Date: 201-02-01
# Authors: James Robinson & Fabio Estevam
source [find target/imx28.cfg]
$_TARGETNAME configure -event gdb-attach { imx28evk_init }
$_TARGETNAME configure -event reset-init { imx28evk_init }
proc imx28evk_init { } {
halt
#****************************
# VDDD setting
#****************************
# set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e
mww 0x80044010 0x0003F503
mww 0x80044040 0x0002041E
#****************************
# CLOCK set up
#****************************
# Power up PLL0 HW_CLKCTRL_PLL0CTRL0
mww 0x80040000 0x00020000
# Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0
# EMI - first set DIV_EMI to div-by-2 before programming frac divider
mww 0x800400F0 0x80000002
# CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
mww 0x800401B0 0x92921613
# Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR
mww 0x800401D8 0x00040080
# HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2
mww 0x80040060 0x00000002
#****************************
# POWER up DCDD_VDDA (DDR2)
#****************************
# Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC
mww 0x80044050 0x0000270C
#****************************
# DDR2 DCDD_VDDA
#****************************
# First set up pin muxing and drive strength
# Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR
mww 0x80018008 0xC0000000
#****************************
# EMI PAD setting
#****************************
# Set up drive strength for EMI pins
mww 0x80019B80 0x00030000
#IOMUXC_SW_PAD_CTL_GRP_CTLDS
# Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13
mww 0x800181A8 0xFFFFFFFF
mww 0x800181B8 0xFFFFFFFF
mww 0x800181C8 0xFFFFFFFF
mww 0x800181D8 0xFFFFFFFF
#** Ungate EMI clock in CCM
mww 0x800400F0 0x00000002
#============================================================================
# DDR Controller Registers
#============================================================================
# Manufacturer: Elpida
# Device Part Number: EDE1116AEBG
# Clock Freq.: 200MHz
# Density: 1Gb
# Chip Selects: 1
# Number of Banks: 8
# Row address: 13
# Column address: 10
#============================================================================
mww 0x800E0000 0x00000000
mww 0x800E0040 0x00000000
mww 0x800E0054 0x00000000
mww 0x800E0058 0x00000000
mww 0x800E005C 0x00000000
mww 0x800E0060 0x00000000
mww 0x800E0064 0x00000000
mww 0x800E0068 0x00010101
mww 0x800E006C 0x01010101
mww 0x800E0070 0x000f0f01
mww 0x800E0074 0x0102020A
mww 0x800E007C 0x00010101
mww 0x800E0080 0x00000100
mww 0x800E0084 0x00000100
mww 0x800E0088 0x00000000
mww 0x800E008C 0x00000002
mww 0x800E0090 0x01010000
mww 0x800E0094 0x07080403
mww 0x800E0098 0x06005003
mww 0x800E009C 0x0A0000C8
mww 0x800E00A0 0x02009C40
mww 0x800E00A4 0x0002030C
mww 0x800E00A8 0x0036B009
mww 0x800E00AC 0x031A0612
mww 0x800E00B0 0x02030202
mww 0x800E00B4 0x00C8001C
mww 0x800E00C0 0x00011900
mww 0x800E00C4 0xffff0303
mww 0x800E00C8 0x00012100
mww 0x800E00CC 0xffff0303
mww 0x800E00D0 0x00012100
mww 0x800E00D4 0xffff0303
mww 0x800E00D8 0x00012100
mww 0x800E00DC 0xffff0303
mww 0x800E00E0 0x00000003
mww 0x800E00E8 0x00000000
mww 0x800E0108 0x00000612
mww 0x800E010C 0x01000f02
mww 0x800E0114 0x00000200
mww 0x800E0118 0x00020007
mww 0x800E011C 0xf4004a27
mww 0x800E0120 0xf4004a27
mww 0x800E012C 0x07400300
mww 0x800E0130 0x07400300
mww 0x800E013C 0x00000005
mww 0x800E0140 0x00000000
mww 0x800E0144 0x00000000
mww 0x800E0148 0x01000000
mww 0x800E014C 0x01020408
mww 0x800E0150 0x08040201
mww 0x800E0154 0x000f1133
mww 0x800E015C 0x00001f04
mww 0x800E0160 0x00001f04
mww 0x800E016C 0x00001f04
mww 0x800E0170 0x00001f04
mww 0x800E0288 0x00010000
mww 0x800E028C 0x00030404
mww 0x800E0290 0x00000003
mww 0x800E02AC 0x01010000
mww 0x800E02B0 0x01000000
mww 0x800E02B4 0x03030000
mww 0x800E02B8 0x00010303
mww 0x800E02BC 0x01020202
mww 0x800E02C0 0x00000000
mww 0x800E02C4 0x02030303
mww 0x800E02C8 0x21002103
mww 0x800E02CC 0x00061200
mww 0x800E02D0 0x06120612
mww 0x800E02D4 0x04420442
# Mode register 0 for CS1 and CS0, ok to program CS1 even if not used
mww 0x800E02D8 0x00000000
# Mode register 0 for CS2 and CS3, not supported in this processor
mww 0x800E02DC 0x00040004
# Mode register 1 for CS1 and CS0, ok to program CS1 even if not used
mww 0x800E02E0 0x00000000
# Mode register 1 for CS2 and CS3, not supported in this processor
mww 0x800E02E4 0x00000000
# Mode register 2 for CS1 and CS0, ok to program CS1 even if not used
mww 0x800E02E8 0x00000000
# Mode register 2 for CS2 and CS3, not supported in this processor
mww 0x800E02EC 0x00000000
# Mode register 3 for CS1 and CS0, ok to program CS1 even if not used
mww 0x800E02F0 0x00000000
# Mode register 3 for CS2 and CS3, not supported in this processor
mww 0x800E02F4 0xffffffff
#** start controller **#
mww 0x800E0040 0x00000001
# bit[0]: start
}

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# The IMX31PDK eval board has a single IMX31 chip
source [find target/imx31.cfg]
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { imx31pdk_init }
proc self_test {} {
echo "Running 100 iterations of test."
dump_image /ram/test 0x80000000 0x40000
for {set i 0} {$i < 100} {set i [expr $i+1]} {
echo "Iteration $i"
reset init
mww 0x80000000 0x12345678 0x10000
load_image /ram/test 0x80000000 bin
verify_image /ram/test 0x80000000 bin
}
}
# Slow fallback frequency
# measure_clk indicates ca. 3-4MHz.
jtag_rclk 1000
proc imx31pdk_init { } {
imx3x_reset
# This setup puts RAM at 0x80000000
mww 0x53FC0000 0x040
mww 0x53F80000 0x074B0B7D
# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
#mww 0x53F80004 0xFF871D50
#mww 0x53F80010 0x00271C1B
# Start 16 bit NorFlash Initialization on CS0
mww 0xb8002000 0x0000CC03
mww 0xb8002004 0xa0330D01
mww 0xb8002008 0x00220800
# Configure CPLD on CS4
mww 0xb8002040 0x0000DCF6
mww 0xb8002044 0x444A4541
mww 0xb8002048 0x44443302
# SDCLK
mww 0x43FAC26C 0
# CAS
mww 0x43FAC270 0
# RAS
mww 0x43FAC274 0
# CS2 (CSD0)
mww 0x43FAC27C 0x1000
# DQM3
mww 0x43FAC284 0
# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
mww 0x43FAC288 0
mww 0x43FAC28C 0
mww 0x43FAC290 0
mww 0x43FAC294 0
mww 0x43FAC298 0
mww 0x43FAC29C 0
mww 0x43FAC2A0 0
mww 0x43FAC2A4 0
mww 0x43FAC2A8 0
mww 0x43FAC2AC 0
mww 0x43FAC2B0 0
mww 0x43FAC2B4 0
mww 0x43FAC2B8 0
mww 0x43FAC2BC 0
mww 0x43FAC2C0 0
mww 0x43FAC2C4 0
mww 0x43FAC2C8 0
mww 0x43FAC2CC 0
mww 0x43FAC2D0 0
mww 0x43FAC2D4 0
mww 0x43FAC2D8 0
mww 0x43FAC2DC 0
# Initialization script for 32 bit DDR on MX31 ADS
mww 0xB8001010 0x00000004
mww 0xB8001004 0x006ac73a
mww 0xB8001000 0x92100000
mww 0x80000f00 0x12344321
mww 0xB8001000 0xa2100000
mww 0x80000000 0x12344321
mww 0x80000000 0x12344321
mww 0xB8001000 0xb2100000
mwb 0x80000033 0xda
mwb 0x81000000 0xff
mww 0xB8001000 0x82226080
mww 0x80000000 0xDEADBEEF
mww 0xB8001010 0x0000000c
}

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debuggers/openocd/tcl/board/imx35pdk.cfg Normal file
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# The IMX35PDK eval board has a single IMX35 chip
source [find target/imx35.cfg]
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { imx35pdk_init }
# Stick to *really* low clock rate or reset will fail
# without RTCK / RCLK
jtag_rclk 10
proc imx35pdk_init { } {
imx3x_reset
mww 0x43f00040 0x00000000
mww 0x43f00044 0x00000000
mww 0x43f00048 0x00000000
mww 0x43f0004C 0x00000000
mww 0x43f00050 0x00000000
mww 0x43f00000 0x77777777
mww 0x43f00004 0x77777777
mww 0x53f00040 0x00000000
mww 0x53f00044 0x00000000
mww 0x53f00048 0x00000000
mww 0x53f0004C 0x00000000
mww 0x53f00050 0x00000000
mww 0x53f00000 0x77777777
mww 0x53f00004 0x77777777
# clock setup
mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
#=================================================
# WEIM config
#=================================================
# CS0U
mww 0xB8002000 0x0000CC03
# CS0L
mww 0xB8002004 0xA0330D01
# CS0A
mww 0xB8002008 0x00220800
# CS5U
mww 0xB8002050 0x0000dcf6
# CS5L
mww 0xB8002054 0x444a4541
# CS5A
mww 0xB8002058 0x44443302
# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
mww 0x43FAC368 0x00000006
mww 0x43FAC36C 0x00000006
mww 0x43FAC370 0x00000006
mww 0x43FAC374 0x00000006
mww 0x43FAC378 0x00000006
mww 0x43FAC37C 0x00000006
mww 0x43FAC380 0x00000006
mww 0x43FAC384 0x00000006
mww 0x43FAC388 0x00000006
mww 0x43FAC38C 0x00000006
mww 0x43FAC390 0x00000006
mww 0x43FAC394 0x00000006
mww 0x43FAC398 0x00000006
mww 0x43FAC39C 0x00000006
mww 0x43FAC3A0 0x00000006
mww 0x43FAC3A4 0x00000006
mww 0x43FAC3A8 0x00000006
mww 0x43FAC3AC 0x00000006
mww 0x43FAC3B0 0x00000006
mww 0x43FAC3B4 0x00000006
mww 0x43FAC3B8 0x00000006
mww 0x43FAC3BC 0x00000006
mww 0x43FAC3C0 0x00000006
mww 0x43FAC3C4 0x00000006
mww 0x43FAC3C8 0x00000006
mww 0x43FAC3CC 0x00000006
mww 0x43FAC3D0 0x00000006
mww 0x43FAC3D4 0x00000006
mww 0x43FAC3D8 0x00000006
# DDR data bus SD 0 through 31
mww 0x43FAC3DC 0x00000082
mww 0x43FAC3E0 0x00000082
mww 0x43FAC3E4 0x00000082
mww 0x43FAC3E8 0x00000082
mww 0x43FAC3EC 0x00000082
mww 0x43FAC3F0 0x00000082
mww 0x43FAC3F4 0x00000082
mww 0x43FAC3F8 0x00000082
mww 0x43FAC3FC 0x00000082
mww 0x43FAC400 0x00000082
mww 0x43FAC404 0x00000082
mww 0x43FAC408 0x00000082
mww 0x43FAC40C 0x00000082
mww 0x43FAC410 0x00000082
mww 0x43FAC414 0x00000082
mww 0x43FAC418 0x00000082
mww 0x43FAC41c 0x00000082
mww 0x43FAC420 0x00000082
mww 0x43FAC424 0x00000082
mww 0x43FAC428 0x00000082
mww 0x43FAC42c 0x00000082
mww 0x43FAC430 0x00000082
mww 0x43FAC434 0x00000082
mww 0x43FAC438 0x00000082
mww 0x43FAC43c 0x00000082
mww 0x43FAC440 0x00000082
mww 0x43FAC444 0x00000082
mww 0x43FAC448 0x00000082
mww 0x43FAC44c 0x00000082
mww 0x43FAC450 0x00000082
mww 0x43FAC454 0x00000082
mww 0x43FAC458 0x00000082
# DQM setup
mww 0x43FAC45c 0x00000082
mww 0x43FAC460 0x00000082
mww 0x43FAC464 0x00000082
mww 0x43FAC468 0x00000082
mww 0x43FAC46c 0x00000006
mww 0x43FAC470 0x00000006
mww 0x43FAC474 0x00000006
mww 0x43FAC478 0x00000006
mww 0x43FAC47c 0x00000006
mww 0x43FAC480 0x00000006 ;# CSD0
mww 0x43FAC484 0x00000006 ;# CSD1
mww 0x43FAC488 0x00000006
mww 0x43FAC48c 0x00000006
mww 0x43FAC490 0x00000006
mww 0x43FAC494 0x00000006
mww 0x43FAC498 0x00000006
mww 0x43FAC49c 0x00000006
mww 0x43FAC4A0 0x00000006
mww 0x43FAC4A4 0x00000006 ;# RAS
mww 0x43FAC4A8 0x00000006 ;# CAS
mww 0x43FAC4Ac 0x00000006 ;# SDWE
mww 0x43FAC4B0 0x00000006 ;# SDCKE0
mww 0x43FAC4B4 0x00000006 ;# SDCKE1
mww 0x43FAC4B8 0x00000002 ;# SDCLK
# SDQS0 through SDQS3
mww 0x43FAC4Bc 0x00000082
mww 0x43FAC4C0 0x00000082
mww 0x43FAC4C4 0x00000082
mww 0x43FAC4C8 0x00000082
# *==================================================
# Initialization script for 32 bit DDR2 on RINGO 3DS
# *==================================================
#--------------------------------------------
# Init CCM
#--------------------------------------------
mww 0x53F80028 0x7D000028
#--------------------------------------------
# Init IOMUX for JTAG
#--------------------------------------------
mww 0x43FAC5EC 0x000000C3
mww 0x43FAC5F0 0x000000C3
mww 0x43FAC5F4 0x000000F3
mww 0x43FAC5F8 0x000000F3
mww 0x43FAC5FC 0x000000F3
mww 0x43FAC600 0x000000F3
mww 0x43FAC604 0x000000F3
# ESD_MISC : enable DDR2
mww 0xB8001010 0x00000304
#--------------------------------------------
# Init 32-bit DDR2 memeory on CSD0
# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
#--------------------------------------------
# ESD_ESDCFG0 : set timing paramters
mww 0xB8001004 0x007ffC2f
# ESD_ESDCTL0 : select Prechare-All mode
mww 0xB8001000 0x92220000
# DDR2 : Prechare-All
mww 0x80000400 0x12345678
# ESD_ESDCTL0 : select Load-Mode-Register mode
mww 0xB8001000 0xB2220000
# DDR2 : Load reg EMR2
mwb 0x84000000 0xda
# DDR2 : Load reg EMR3
mwb 0x86000000 0xda
# DDR2 : Load reg EMR1 -- enable DLL
mwb 0x82000400 0xda
# DDR2 : Load reg MR -- reset DLL
mwb 0x80000333 0xda
# ESD_ESDCTL0 : select Prechare-All mode
mww 0xB8001000 0x92220000
# DDR2 : Prechare-All
mwb 0x80000400 0x12345678
# ESD_ESDCTL0 : select Manual-Refresh mode
mww 0xB8001000 0xA2220000
# DDR2 : Manual-Refresh 2 times
mww 0x80000000 0x87654321
mww 0x80000000 0x87654321
# ESD_ESDCTL0 : select Load-Mode-Register mode
mww 0xB8001000 0xB2220000
# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
mwb 0x80000233 0xda
# DDR2 : Load reg EMR1 -- OCD default
mwb 0x82000780 0xda
# DDR2 : Load reg EMR1 -- OCD exit
mwb 0x82000400 0xda ;# ODT disabled
# ESD_ESDCTL0 : select normal-operation mode
# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
# disable PWT & PRCT
# disable Auto-Refresh
mww 0xB8001000 0x82220080
## ESD_ESDCTL0 : enable Auto-Refresh
mww 0xB8001000 0x82228080
## ESD_ESDCTL1 : enable Auto-Refresh
mww 0xB8001008 0x00002000
#***********************************************
# Adjust the ESDCDLY5 register
#***********************************************
# Vary DQS_ABS_OFFSET5 for writes
mww 0xB8001020 0x00F48000 ;# this is the default value
mww 0xB8001024 0x00F48000 ;# this is the default value
mww 0xB8001028 0x00F48000 ;# this is the default value
mww 0xB800102c 0x00F48000 ;# this is the default value
#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
mww 0xB8001010 0x00000384
# wait a while
sleep 1000
# now clear the force measurement bit
mww 0xB8001010 0x00000304
# dummy write to DDR memory to set DQS low
mww 0x80000000 0x00000000
mww 0x30000100 0x0
mww 0x30000104 0x31024
}

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debuggers/openocd/tcl/board/imx53loco.cfg Normal file
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##################################################################################
# Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #
# Kiwigrid GmbH #
##################################################################################
# The IMX53LOCO (QSB) board has a single IMX53 chip
source [find target/imx53.cfg]
# Helper for common memory read/modify/write procedures
source [find mem_helper.tcl]
echo "iMX53 Loco board lodaded."
# Set reset type
#reset_config srst_only
adapter_khz 3000
#jtag_nsrst_delay 200
#jtag_ntrst_delay 200
$_TARGETNAME configure -event "reset-assert" {
echo "Reseting ...."
#cortex_a dbginit
}
$_TARGETNAME configure -event reset-init { loco_init }
global AIPS1_BASE_ADDR
set AIPS1_BASE_ADDR 0x53F00000
global AIPS2_BASE_ADDR
set AIPS2_BASE_ADDR 0x63F00000
proc loco_init { } {
echo "Reset-init..."
; # halt the CPU
halt
echo "HW version [format %x [mrw 0x48]]"
dap apsel 1
DCD
; # ARM errata ID #468414
set tR [arm mrc 15 0 1 0 1]
arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
init_l2cc
init_aips
init_clock
dap apsel 0
; # Force ARM state
; #reg cpsr 0x000001D3
arm core_state arm
jtag_rclk 3000
# adapter_khz 3000
}
# L2CC Cache setup/invalidation/disable
proc init_l2cc { } {
; #/* explicitly disable L2 cache */
; #mrc 15, 0, r0, c1, c0, 1
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
; #add r0, r0, #0x4 /* data RAM */
; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
; #orr r0, r0, #(1 << 22) /* disable write allocate */
; #mcr 15, 1, r0, c9, c0, 2
arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
}
# AIPS setup - Only setup MPROTx registers.
# The PACR default values are good.
proc init_aips { } {
; # Set all MPROTx to be non-bufferable, trusted for R/W,
; # not forced to user-mode.
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
set VAL 0x77777777
# dap apsel 1
mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
# dap apsel 0
}
proc init_clock { } {
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
set CLKCTL_CCSR 0x0C
set CLKCTL_CBCDR 0x14
set CLKCTL_CBCMR 0x18
set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
set CLKCTL_CSCMR1 0x1C
set CLKCTL_CDHIPR 0x48
set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
set CLKCTL_CSCDR1 0x24
set CLKCTL_CCDR 0x04
; # Switch ARM to step clock
mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
return
echo "not returned"
setup_pll $PLL1_BASE_ADDR 800
setup_pll $PLL3_BASE_ADDR 400
; # Switch peripheral to PLL3
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
setup_pll $PLL2_BASE_ADDR 400
; # Switch peripheral to PLL2
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
; # change uart clk parent to pll2
mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
; # make sure change is effective
while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
setup_pll $PLL3_BASE_ADDR 216
setup_pll $PLL4_BASE_ADDR 455
; # Set the platform clock dividers
mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
mww [expr $CCM_BASE_ADDR + 0x10] 0
; # Switch ARM back to PLL 1.
mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
; # make uart div=6
mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
; # Restore the default values in the Gate registers
mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
; # for cko - for ARM div by 8
mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
}
proc setup_pll { PLL_ADDR CLK } {
set PLL_DP_CTL 0x00
set PLL_DP_CONFIG 0x04
set PLL_DP_OP 0x08
set PLL_DP_HFS_OP 0x1C
set PLL_DP_MFD 0x0C
set PLL_DP_HFS_MFD 0x20
set PLL_DP_MFN 0x10
set PLL_DP_HFS_MFN 0x24
if {$CLK == 1000} {
set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (12 - 1)]
set DP_MFN 5
} elseif {$CLK == 850} {
set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (48 - 1)]
set DP_MFN 41
} elseif {$CLK == 800} {
set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (3 - 1)]
set DP_MFN 1
} elseif {$CLK == 700} {
set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (24 - 1)]
set DP_MFN 7
} elseif {$CLK == 600} {
set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (4 - 1)]
set DP_MFN 1
} elseif {$CLK == 665} {
set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (96 - 1)]
set DP_MFN 89
} elseif {$CLK == 532} {
set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
set DP_MFD [expr (24 - 1)]
set DP_MFN 13
} elseif {$CLK == 455} {
set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
set DP_MFD [expr (48 - 1)]
set DP_MFN 71
} elseif {$CLK == 400} {
set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
set DP_MFD [expr (3 - 1)]
set DP_MFN 1
} elseif {$CLK == 216} {
set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
set DP_MFD [expr (4 - 1)]
set DP_MFN 3
} else {
error "Error (setup_dll): clock not found!"
}
mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
}
proc CPU_2_BE_32 { L } {
return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
}
# Device Configuration Data
proc DCD { } {
# dap apsel 1
mww 0x53FA8554 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
mww 0x53FA8558 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
mww 0x53FA8560 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
mww 0x53FA8564 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
mww 0x53FA8568 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
mww 0x53FA8570 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
mww 0x53FA8574 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
mww 0x53FA8578 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
mww 0x53FA857c 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
mww 0x53FA8580 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
mww 0x53FA8584 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
mww 0x53FA8588 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
mww 0x53FA8590 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
mww 0x53FA8594 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
mww 0x53FA86f0 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
mww 0x53FA86f4 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
mww 0x53FA86fc 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
mww 0x53FA8714 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
mww 0x53FA8718 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B0DS
mww 0x53FA871c 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B1DS
mww 0x53FA8720 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
mww 0x53FA8724 0x04000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
mww 0x53FA8728 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B2DS
mww 0x53FA872c 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B3DS
# Initialize DDR2 memory
mww 0x63FD9088 0x35343535 ;# ESDCTL_RDDLCTL
mww 0x63FD9090 0x4d444c44 ;# ESDCTL_WRDLCTL
mww 0x63FD907c 0x01370138 ;# ESDCTL_DGCTRL0
mww 0x63FD9080 0x013b013c ;# ESDCTL_DGCTRL1
mww 0x63FD9018 0x00011740 ;# ESDCTL_ESDMISC
mww 0x63FD9000 0xc3190000 ;# ESDCTL_ESDCTL
mww 0x63FD900c 0x9f5152e3 ;# ESDCTL_ESDCFG0
mww 0x63FD9010 0xb68e8a63 ;# ESDCTL_ESDCFG1
mww 0x63FD9014 0x01ff00db ;# ESDCTL_ESDCFG2
mww 0x63FD902c 0x000026d2 ;# ESDCTL_ESDRWD
mww 0x63FD9030 0x009f0e21 ;# ESDCTL_ESDOR
mww 0x63FD9008 0x12273030 ;# ESDCTL_ESDOTC
mww 0x63FD9004 0x0002002d ;# ESDCTL_ESDPDC
mww 0x63FD901c 0x00008032 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x00008033 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x00028031 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x052080b0 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x04008040 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x0000803a ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x0000803b ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x00028039 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x05208138 ;# ESDCTL_ESDSCR
mww 0x63FD901c 0x04008048 ;# ESDCTL_ESDSCR
mww 0x63FD9020 0x00005800 ;# ESDCTL_ESDREF
mww 0x63FD9040 0x04b80003 ;# ESDCTL_ZQHWCTRL
mww 0x63FD9058 0x00022227 ;# ESDCTL_ODTCTRL
mww 0x63FD901C 0x00000000 ;# ESDCTL_ESDSCR
# dap apsel 0
}
# vim:filetype=tcl

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#
# Keil MCB1700 eval board
#
# http://www.keil.com/mcb1700/picture.asp
#
source [find target/lpc1768.cfg]

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debuggers/openocd/tcl/board/keil_mcb2140.cfg Normal file
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#
# Keil MCB2140 eval board
#
# http://www.keil.com/mcb2140/picture.asp
#
source [find target/lpc2148.cfg]

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debuggers/openocd/tcl/board/kwikstik.cfg Normal file
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#
# Freescale KwikStik development board
#
#
# JLINK interface is onboard
#
source [find interface/jlink.cfg]
jtag_rclk 100
source [find target/k40.cfg]
reset_config trst_and_srst
#
# Bank definition for the 'program flash' (instructions and/or data)
#
flash bank $_CHIPNAME.pflash kinetis 0x00000000 0x40000 0 4 $_TARGETNAME

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debuggers/openocd/tcl/board/linksys_nslu2.cfg Normal file
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# This is for the LinkSys (CISCO) NSLU2 board
# It is an Intel XSCALE IXP420 CPU.
source [find target/ixp42x.cfg]
# The _TARGETNAME is set by the above.
$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0

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# the Lost Illusions Serendipitous Autopilot
# http://paparazzi.enac.fr/wiki/Lisa
# Work-area size (RAM size) = 20kB for STM32F103RB device
set WORKAREASIZE 0x5000
source [find target/stm32f1x.cfg]

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debuggers/openocd/tcl/board/logicpd_imx27.cfg Normal file
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# The LogicPD Eval IMX27 eval board has a single IMX27 chip
source [find target/imx27.cfg]
# The Logic PD board has a NOR flash on CS0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
#
# FIX ME, Add support to
#
# (A) hard reset the board.
# (B) Initialize the SDRAM on the board
#

18
debuggers/openocd/tcl/board/lpc1850_spifi_generic.cfg Normal file
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#
# Generic LPC1850 board w/ SPIFI flash.
# This config file is intended as an example of how to
# use the lpcspifi flash driver, but it should be functional
# for most LPC1850 boards utilizing SPIFI flash.
set CHIPNAME lpc1850
source [find target/lpc1850.cfg]
#A large working area greatly reduces flash write times
set _WORKAREASIZE 0x4000
$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
#Configure the flash bank; 0x14000000 is the base address for
#lpc43xx/lpc18xx family micros.
flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3

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debuggers/openocd/tcl/board/lpc4350_spifi_generic.cfg Normal file
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#
# Generic LPC4350 board w/ SPIFI flash.
# This config file is intended as an example of how to
# use the lpcspifi flash driver, but it should be functional
# for most LPC4350 boards utilizing SPIFI flash.
set CHIPNAME lpc4350
source [find target/lpc4350.cfg]
#A large working area greatly reduces flash write times
set _WORKAREASIZE 0x2000
$_CHIPNAME.m4 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
#Configure the flash bank; 0x14000000 is the base address for
#lpc43xx/lpc18xx family micros.
flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4

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debuggers/openocd/tcl/board/lubbock.cfg Normal file
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# Intel "Lubbock" Development Board with PXA255 (dbpxa255)
# Obsolete; this was Intel's original PXA255 development system
# Board also had CPU cards for SA1100, PXA210, PXA250, and more.
source [find target/pxa255.cfg]
adapter_nsrst_delay 250
jtag_ntrst_delay 250
# NOTE: until after pinmux and such are set up, only CS0 is
# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
# each bank is 32-bits wide, two 16-bit chips in parallel
set _FLASHNAME $_CHIPNAME.flash0
flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
# CS2 low -- FPGA registers
# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
$_TARGETNAME configure -work-area-phys 0x0a0f0000
$_TARGETNAME configure -event reset-assert-pre \
"$_TARGETNAME configure -work-area-size 0"
# Make the hex led display a number, assuming CS2 is set up
# and all digits have been enabled through the FPGA.
proc hexled {u32} {
mww 0x08000010 $u32
}
# CS3 -- Ethernet
# CS4 -- SA1111
# CS5 -- PCMCIA
# NOTE: system console normally uses the FF UART connector
proc lubbock_init {target} {
echo "Initialize PXA255 Lubbock board"
# (1) pinmux
# GPSR0..GPSR2
mww 0x40e00018 0x00008000
mww 0x40e0001c 0x00FC0382
mww 0x40e00020 0x0001FFFF
# GPDR0..GPDR2
mww 0x40e0000c 0x0060A800
mww 0x40e00010 0x00FF0382
mww 0x40e00014 0x0001C000
# GAFR0_[LU]..GAFR2_[LU]
mww 0x40e00054 0x98400000
mww 0x40e00058 0x00002950
mww 0x40e0005c 0x000A9558
mww 0x40e00060 0x0005AAAA
mww 0x40e00064 0xA0000000
mww 0x40e00068 0x00000002
# write PSSR, enable GPIOs
mww 0x40f00000 0x00000020
# write LED ctrl register ... ones disable
# high byte, 8 hex leds; low byte, 8 discretes
mwh 0x08000040 0xf0ff
hexled 0x0000
# (2) Address space setup
# MSC0/MSC1/MSC2
mww 0x48000008 0x23f223f2
mww 0x4800000c 0x3ff1a441
mww 0x48000010 0x7ff97ff1
# pcmcia/cf
mww 0x48000014 0x00000000
mww 0x48000028 0x00010504
mww 0x4800002c 0x00010504
mww 0x48000030 0x00010504
mww 0x48000034 0x00010504
mww 0x48000038 0x00004715
mww 0x4800003c 0x00004715
hexled 0x1111
# (3) SDRAM setup
# REVISIT this looks dubious ... no refresh cycles
mww 0x48000004 0x03CA4018
mww 0x48000004 0x004B4018
mww 0x48000004 0x000B4018
mww 0x48000004 0x000BC018
mww 0x48000000 0x00001AC8
mww 0x48000000 0x00001AC9
mww 0x48000040 0x00000000
# FIXME -- setup:
# CLOCKS (and faster JTAG)
# enable icache
# FIXME SRAM isn't working
# $target configure -work-area-size 0x10000
hexled 0x2222
flash probe 0
flash probe 1
hexled 0xcafe
}
$_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"

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debuggers/openocd/tcl/board/mcb1700.cfg Normal file
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# Keil MCB1700 PCB with 1768
#
# Reset init script sets it to 100MHz
set CCLK 100000
source [find target/lpc1768.cfg]
global MCB1700_CCLK
set MCB1700_CCLK $CCLK
$_TARGETNAME configure -event reset-start {
# Start *real slow* as we do not know the
# state the boot rom left the clock in
adapter_khz 10
}
# Set up 100MHz clock to CPU
$_TARGETNAME configure -event reset-init {
# PLL0CON: Disable PLL
mww 0x400FC080 0x00000000
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
# CCLK=PLL/4 (=100 MHz)
mww 0x400FC104 0x00000003
# CLKSRCSEL: Clock source = internal RC oscillator
mww 0x400FC10C 0x00000000
# PLL0CFG: M=50,N=1 -> PLL=400 MHz
mww 0x400FC084 0x00000031
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
# PLL0CON: Enable PLL
mww 0x400FC080 0x00000001
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
sleep 50
# PLL0CON: Connect PLL
mww 0x400FC080 0x00000003
# PLLFEED
mww 0x400FC08C 0x000000AA
# PLLFEED
mww 0x400FC08C 0x00000055
# Dividing CPU clock by 8 should be pretty conservative
#
#
global MCB1700_CCLK
adapter_khz [expr $MCB1700_CCLK / 8]
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
# and reside in flash instead).
#
# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
# Bit Symbol Value Description Reset
# value
# 0 MAP Memory map control. 0
# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
# 1 User mode. The on-chip Flash memory is mapped to address 0.
# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
#
# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
mww 0x400FC040 0x01
}

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debuggers/openocd/tcl/board/microchip_explorer16.cfg Normal file
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# Microchip Explorer 16 with PIC32MX360F512L PIM module.
# http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858
# TAPID for PIC32MX360F512L
set CPUTAPID 0x30938053
# use 32k working area
set WORKAREASIZE 32768
source [find target/pic32mx.cfg]

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debuggers/openocd/tcl/board/mini2440.cfg Normal file
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#-------------------------------------------------------------------------
# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
# 64 MB NAND (Samsung K9D1208V0M)
# B Findlay 08/09
#
# ----------- Important notes to help you on your way ----------
# README:
# NOR/NAND Boot Switch - I have not read the vivi source, but from
# what I could tell from reading the registers it appears that vivi
# loads itself into DRAM and then flips NFCONT (0x4E000004) bits
# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
# FLASH at the bottom 64MB of memory. This essentially takes the
# NOR Flash out of the circuit so you can't trash it.
#
# I adapted the samsung_s3c2440.cfg file which is why I did not
# include "source [find target/samsung_s3c2440.cfg]". I believe
# the -work-area-phys 0x200000 is incorrect, but also had to pad
# some additional resets. I didn't modify it as if it is working
# for someone, the work-area-phys is not used by most.
#
# JTAG ADAPTER SPECIFIC
# IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
# FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
# necessary to FORCE setting the clock. Normally this should be configured
# in the openocd.cfg file, but was placed here as it can be a tough
# problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified
# the openOCD driver jlink.c and posted it here. It may eventually end
# up changed in openOCD, but its a hack in the driver and really should
# be in the jtag layer (core.c me thinks), but haven't done it yet. My
# hack for jlink.c may be found here.
#
# http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
#
# Note: Also if you have a USB JTAG, you will need the USB library installed
# on your system "libusb-dev" or the make of openocd will fail. I *think*
# it's apt-get install libusb-dev. When I made my config I only included
# --enable-jlink and --enable-usbdevs
#
# I HAVE NOT Tested this throughly, so there could still be problems.
# But it should get you way ahead of the game from where I started.
# If you find problems (and fixes) please post them to
# openocd-development@lists.berlios.de and join the developers and
# check in fixes to this and anything else you find. I do not
# provide support, but if you ask really nice and I see anything
# obvious I will tell you.. mostly just dig, fix, and submit to openocd.
#
# best! brfindla@yahoo.com Nashua, NH USA
#
# Recommended resources:
# - first two are the best Mini2440 resources anywhere
# - maintained by buserror... thanks guy!
#
# http://bliterness.blogspot.com/
# http://code.google.com/p/mini2440/
#
# others....
#
# http://forum.sparkfun.com/viewforum.php?f=18
# http://labs.kernelconcepts.de/Publications/Micro24401/
# http://www.friendlyarm.net/home
# http://www.amontec.com/jtag_pinout.shtml
#
#-------------------------------------------------------------------------
#
#
# Your openocd.cfg file should contain:
# source [find interface/<yourjtag>.cfg]
# source [find board/mini2440.cfg]
#
#
#
# FIXME use some standard target config, maybe create one from this
#
# source [find target/...cfg]
#-------------------------------------------------------------------------
# Target configuration for the Samsung 2440 system on chip
# Tested on a S3C2440 Evaluation board by keesj
# Processor : ARM920Tid(wb) rev 0 (v4l)
# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
# (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
#-------------------------------------------------------------------------
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME s3c2440
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a bigendian
set _ENDIAN little
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0032409d
}
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
#-------------------------------------------------------------------------
# JTAG ADAPTER SPECIFIC
# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------
adapter_khz 12000
jtag interface
#-------------------------------------------------------------------------
# GDB Setup
#-------------------------------------------------------------------------
gdb_breakpoint_override hard
#------------------------------------------------
# ARM SPECIFIC
#------------------------------------------------
targets
# arm7_9 dcc_downloads enable
# arm7_9 fast_memory_access enable
nand device s3c2440 0
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
init
echo " "
echo "-------------------------------------------"
echo "--- login with - telnet localhost 4444 ---"
echo "--- then type help_2440 ---"
echo "-------------------------------------------"
echo " "
#------------------------------------------------
# Processor Initialialization
# Note: Processor writes can only occur when
# the state is in SYSTEM. When you call init_2440
# one of the first lines will tell you what state
# you are in. If a linux image is booting
# when you run this, it will not work
# a vivi boot loader will run with this just
# fine. The reg values were obtained by a combination
# of figuring them out fromt the manual, and looking
# at post vivi values with the debugger. Don't
# place too much faith in them, but seem to work.
#------------------------------------------------
proc init_2440 { } {
halt
s3c2440.cpu curstate
#-----------------------------------------------
# Set Processor Clocks - mini2440 xtal=12mHz
# we set main clock for 405mHZ
# we set the USB Clock for 48mHz
# OM2 OM3 pulled to ground so main clock and
# usb clock are off 12mHz xtal
#-----------------------------------------------
mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg
mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register
mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg
mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
# BWSCON configures all banks, NAND, NOR, DRAM
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width
mww phys 0x48000010 0x00001112 ;# BANKCON4 - ?
mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM
mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM
mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM
mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM
mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM
mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
mww phys 0x56000000 0x007FFFFF ;# GPACON
mww phys 0x56000010 0x00295559 ;# GPBCON
mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE)
mww phys 0x56000014 0x000007C2 ;# GPBDAT
mww phys 0x56000020 0xAAAAA6AA ;# GPCCON
mww phys 0x56000028 0x0000FFFF ;# GPCUP
mww phys 0x56000024 0x00000020 ;# GPCDAT
mww phys 0x56000030 0xAAAAAAAA ;# GPDCON
mww phys 0x56000038 0x0000FFFF ;# GPDUP
mww phys 0x56000040 0xAAAAAAAA ;# GPECON
mww phys 0x56000048 0x0000FFFF ;# GPEUP
mww phys 0x56000050 0x00001555 ;# GPFCON
mww phys 0x56000058 0x0000007F ;# GPFUP
mww phys 0x56000054 0x00000000 ;# GPFDAT
mww phys 0x56000060 0x00150114 ;# GPGCON
mww phys 0x56000068 0x0000007F ;# GPGUP
mww phys 0x56000070 0x0015AAAA ;# GPHCON
mww phys 0x56000078 0x000003FF ;# GPGUP
}
proc flash_config { } {
#-----------------------------------------
# Finish Flash Configuration
#-----------------------------------------
halt
#flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
nand probe 0
nand list
}
proc flash_uboot { } {
# flash the u-Boot binary and reboot into it
init_2440
flash_config
nand erase 0 0x0 0x40000
nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
resume
}
proc load_uboot { } {
echo " "
echo " "
echo "----------------------------------------------------------"
echo "---- Load U-Boot into RAM and execute it. ---"
echo "---- NOTE: loads, partially runs, and hangs ---"
echo "---- U-Boot is fine, this image runs from vivi. ---"
echo "---- I burned u-boot into NAND so I didn't finish ---"
echo "---- debugging it. I am leaving this here as it is ---"
echo "---- part of the way there if you want to fix it. ---"
echo "---- ---"
echo "---- mini2440 U-boot here: ---"
echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---"
echo "---- Also this: ---"
echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
echo "----------------------------------------------------------"
init_2440
echo "Loading /tftpboot/u-boot-nand512.bin"
load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
echo "Verifying image...."
verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
echo "jumping to u-boot"
#bp 0x33f80068 4 hw
reg 0 0
reg 1 0
reg 2 0
reg 3 0
reg 4 0x33f80000
resume 0x33f80000
}
# this may help a little bit debugging the load_uboot
proc s {} {
step
reg
arm disassemble 0x33F80068 0x10
}
proc help_2440 {} {
echo " "
echo " "
echo "-----------------------------------------------------------"
echo "---- The following mini2440 funcs are supported ----"
echo "---- init_2440 - initialize clocks, DRAM, IO ----"
echo "---- flash_config - configures nand flash ----"
echo "---- load_uboot - loads uboot into ram ----"
echo "---- flash_uboot - flashes uboot to nand (untested) ----"
echo "---- help_2440 - this help display ----"
echo "-----------------------------------------------------------"
echo " "
echo " "
}
#----------------------------------------------------------------------------
#----------------------------------- END ------------------------------------
#----------------------------------------------------------------------------

112
debuggers/openocd/tcl/board/mini6410.cfg Normal file
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# Target configuration for the Samsung s3c6410 system on chip
# Tested on a tiny6410
# Processor : ARM1176
# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
source [find target/samsung_s3c6410.cfg]
proc init_6410 {} {
halt
reg cpsr 0x1D3
arm mcr 15 0 15 2 4 0x70000013
#-----------------------------------------------
# Clock and Timer Setting
#-----------------------------------------------
mww 0x7e004000 0 ;# WATCHDOG - Disable
mww 0x7E00F120 0x0003 ;# MEM_SYS_CFG - CS0:8 bit, Mem1:32bit, CS2=NAND
#mww 0x7E00F120 0x1000 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=SROMC
#mww 0x7E00F120 0x1002 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=OND
mww 0x7E00F900 0x805e ;# OTHERS - Change SYNCMUX[6] to “1”
sleep 1000
mww 0x7E00F900 0x80de ;# OTHERS - Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
sleep 1000 ;# - Others[11:8] to 0xF
mww 0x7E00F000 0xffff ;# APLL_LOCK - APLL LockTime
mww 0x7E00F004 0xffff ;# MPLL_LOCK - MPLL LockTime
mww 0x7E00F020 0x1047310 ;# CLK_DIV0 - ARMCLK:HCLK:PCLK = 1:4:16
mww 0x7E00F00c 0x81900302 ;# APLL_CON - A:400, P:3, S:2 => 400MHz
mww 0x7E00F010 0x81900303 ;# MPLL_CON - M:400, P:3, S:3 => 200MHz
mww 0x7E00F01c 0x3 ;# CLK_SRC - APLL,MPLL Clock Select
#-----------------------------------------------
# DRAM initialization
#-----------------------------------------------
mww 0x7e001004 0x4 ;# P1MEMCCMD - Enter the config state
mww 0x7e001010 0x30C ;# P1REFRESH - Refresh Period register (7800ns), 100MHz
# mww 0x7e001010 0x40e ;# P1REFRESH - Refresh Period register (7800ns), 133MHz
mww 0x7e001014 0x6 ;# P1CASLAT - CAS Latency = 3
mww 0x7e001018 0x1 ;# P1T_DQSS
mww 0x7e00101c 0x2 ;# P1T_MRD
mww 0x7e001020 0x7 ;# P1T_RAS - 45 ns
mww 0x7e001024 0xA ;# P1T_RC - 67.5 ns
mww 0x7e001028 0xC ;# P1T_RCD - 22.5 ns
mww 0x7e00102C 0x10B ;# P1T_RFC - 80 ns
mww 0x7e001030 0xC ;# P1T_RP - 22.5 ns
mww 0x7e001034 0x3 ;# P1T_RRD - 15 ns
mww 0x7e001038 0x3 ;# P1T_WR - 15 ns
mww 0x7e00103C 0x2 ;# P1T_WTR
mww 0x7e001040 0x2 ;# P1T_XP
mww 0x7e001044 0x11 ;# P1T_XSR - 120 ns
mww 0x7e001048 0x11 ;# P1T_ESR
#-----------------------------------------------
# Memory Configuration Registers
#-----------------------------------------------
mww 0x7e00100C 0x00010012 ;# P1MEMCFG - 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
mww 0x7e00104C 0x0B41 ;# P1MEMCFG2 - Read delay 1 Cycle, mDDR, 32bit, Sync.
mww 0x7e001200 0x150F0 ;# CHIP_N_CFG - 0x150F0 for 256M, 0x150F8 for 128M
#-----------------------------------------------
# Memory Direct Commands
#-----------------------------------------------
mww 0x7e001008 0xc0000 ;# Chip0 Direct Command :NOP5
mww 0x7e001008 0x0 ;# Chip0 Direct Command :PreCharge al
mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
mww 0x7e001008 0xA0000 ;# EMRS, DS:Full, PASR:Full
mww 0x7e001008 0x80032 ;# MRS, CAS3, BL4
mww 0x7e001004 0x0 ;# Enable DMC1
}
proc install_6410_uboot {} {
# write U-boot magic number
mww 0x50000000 0x24564236
mww 0x50000004 0x20764316
load_image u-boot_nand-ram256.bin 0x50008000 bin
load_image u-boot_nand-ram256.bin 0x57E00000 bin
#Kick in
reg pc 0x57E00000
resume
}
proc init_6410_flash {} {
halt
nand probe 0
nand list
}
adapter_khz 1000
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
gdb_breakpoint_override hard
targets
nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
init
echo " "
echo " "
echo "-------------------------------------------------------------------"
echo "---- The following mini6410/tiny6410 functions are available: ----"
echo "---- init_6410 - initialize clock, timer, DRAM ----"
echo "---- init_6410_flash - initializes NAND flash support ----"
echo "---- install_6410_uboot - copies u-boot image into RAM and ----"
echo "---- runs it ----"
echo "-------------------------------------------------------------------"
echo " "
echo " "

14
debuggers/openocd/tcl/board/netgear-dg834v3.cfg Normal file
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#
# Netgear DG834v3 Router
# Internal 4Kb RAM (@0x80000000)
# Flash is located at 0x90000000 (CS0) and RAM is located at 0x94000000 (CS1)
#
source [find target/ti-ar7.cfg]
# External 16MB SDRAM - disabled as we use internal sram
#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
# External 4MB NOR Flash
set _FLASHNAME $_CHIPNAME.norflash
flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME

11
debuggers/openocd/tcl/board/olimex_LPC2378STK.cfg Normal file
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#####################################################
# Olimex LPC2378STK eval board
#
# http://olimex.com/dev/lpc-2378stk.html
#
# Author: Sten, debian@sansys-electronic.com
#####################################################
#
source [find target/lpc2378.cfg]

8
debuggers/openocd/tcl/board/olimex_lpc_h2148.cfg Normal file
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#
# Olimex LPC-H2148 eval board
#
# http://www.olimex.com/dev/lpc-h2148.html
#
source [find target/lpc2148.cfg]

4
debuggers/openocd/tcl/board/olimex_sam7_ex256.cfg Normal file
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# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
source [find target/sam7x256.cfg]

141
debuggers/openocd/tcl/board/olimex_sam9_l9260.cfg Normal file
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################################################################################
# Olimex SAM9-L9260 Development Board
#
# http://www.olimex.com/dev/sam9-L9260.html
#
# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
# PMC configured for external 18.432 MHz crystal
#
# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
# Dataflash : 1 x Atmel AT45DB161D, 16Mbit
#
################################################################################
source [find target/at91sam9260.cfg]
# NTRST_E jumper is enabled by default, so we don't need to override the reset
# config.
#reset_config srst_only
$_TARGETNAME configure -event reset-start {
# At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if
# RCLK is not supported.
jtag_rclk 5
halt
# RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
# be enabled... use physical address.
mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
##
# Clock configuration for 99.328 MHz main clock.
##
echo "Setting up clock"
mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
sleep 20 ;# wait 20 ms (need 15.6 ms for startup)
mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
sleep 10 ;# wait 10 ms
mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
sleep 20 ;# wait 20 ms (need 1.9 ms for startup)
mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
sleep 10 ;# wait 10 ms
mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
# Increase JTAG speed to 6 MHz if RCLK is not supported.
jtag_rclk 6000
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
##
# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
##
echo "Configuring SDRAM"
mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
mww 0xffffea00 0x1 ;# SDRAMC_MR : issue NOP command
mww 0x20000000 0
mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
mww 0xffffea04 0x2b6 ;# SDRAMC_TR : set refresh timer count to 7 us
##
# NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
##
echo "Configuring NAND flash"
mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
# 3 TDF cycles, no optimization
mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
nand probe at91sam9260.flash
##
# Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
##
echo "Setting up dataflash"
mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
# 2(SPI0_SPCK), and 11(SPI0_NPCS1)
mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
# 250ns delay before SPCK, 250ns b/n tx
mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
}
nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
at91sam9 cle 0 22
at91sam9 ale 0 21
at91sam9 rdy_busy 0 0xfffff800 13
at91sam9 ce 0 0xfffff800 14

7
debuggers/openocd/tcl/board/olimex_stm32_h103.cfg Normal file
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# Olimex STM32-H103 eval board
# http://olimex.com/dev/stm32-h103.html
# Work-area size (RAM size) = 20kB for STM32F103RB device
set WORKAREASIZE 0x5000
source [find target/stm32f1x.cfg]

10
debuggers/openocd/tcl/board/olimex_stm32_h107.cfg Normal file
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#
# Olimex STM32-H107
#
# http://olimex.com/dev/stm32-h107.html
#
# Work-area size (RAM size) = 64kB for STM32F107VC device
set WORKAREASIZE 0x10000
source [find target/stm32f1x.cfg]

10
debuggers/openocd/tcl/board/olimex_stm32_p107.cfg Normal file
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#
# Olimex STM32-P107
#
# http://olimex.com/dev/stm32-p107.html
#
# Work-area size (RAM size) = 64kB for STM32F107VC device
set WORKAREASIZE 0x10000
source [find target/stm32f1x.cfg]

12
debuggers/openocd/tcl/board/omap2420_h4.cfg Normal file
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# OMAP2420 SDP board ("H4")
source [find target/omap2420.cfg]
# NOTE: this assumes you're *NOT* using a TI-14 connector.
reset_config trst_and_srst separate
# Board configs can vary a *LOT* ... parts, jumpers, etc.
# This GP board boots from cs0 using NOR (2x32M), and also
# has 64M NAND on cs6.
flash bank h4.u10 cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
flash bank h4.u11 cfi 0x06000000 0x02000000 2 2 $_TARGETNAME

7
debuggers/openocd/tcl/board/open-bldc.cfg Normal file
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# Open Source Brush Less DC Motor Controller
# http://open-bldc.org
# Work-area size (RAM size) = 20kB for STM32F103RB device
set WORKAREASIZE 0x5000
source [find target/stm32.cfg]

123
debuggers/openocd/tcl/board/openrd.cfg Normal file
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# Marvell OpenRD
source [find interface/openrd.cfg]
source [find target/feroceon.cfg]
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \
-work-area-backup 0
arm7_9 dcc_downloads enable
# this assumes the hardware default peripherals location before u-Boot moves it
set _FLASHNAME $_CHIPNAME.flash
nand device $_FLASHNAME orion 0 0xd8000000
proc openrd_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
feroceon.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 ;# Dunit Control Low Register
mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
mww 0xD000140C 0x00000A33 ;# DDR SDRAM Timing (High) Register
mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
mww 0xD0001420 0x00000004 ;# DDR SDRAM Extended Mode Register
mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
mww 0xD0001428 0x00085520 ;# Dunit Control High Register
mww 0xD000147c 0x00008552 ;# Dunit Control High Register
mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
mww 0xD0001508 0x10000000 ;# CS1n Base Register
mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
mww 0xD0001514 0x00000000 ;# CS2n Size Register
mww 0xD000151C 0x00000000 ;# CS3n Size Register
mww 0xD0001494 0x00120012 ;# DDR2 SDRAM ODT Control (Low) Register
mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
mww 0xD000149C 0x0000E40F ;# DDR2 Dunit ODT Control Register
mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0010000 0x01111111 ;# MPP 0 to 7
mww 0xD0010004 0x11113322 ;# MPP 8 to 15
mww 0xD0010008 0x00001111 ;# MPP 16 to 23
mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
}
proc openrd_reflash_uboot { } {
# reflash the u-Boot binary and reboot into it
openrd_init
nand probe 0
nand erase 0 0x0 0xa0000
nand write 0 uboot.bin 0 oob_softecc_kw
resume
}
proc openrd_load_uboot { } {
# load u-Boot into RAM and execute it
openrd_init
load_image uboot.elf
verify_image uboot.elf
resume 0x00600000
}

34
debuggers/openocd/tcl/board/osk5912.cfg Normal file
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# http://omap.spectrumdigital.com/osk5912/
source [find target/omap5912.cfg]
# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE")
# JTAG connector, and accordingly have J1 connecting pins 1 & 2.
# The TI-14 pin needs "trst_only", and J1 connecting 2 & 3.
reset_config trst_and_srst separate
# NOTE: boards with XOMAP parts wire nSRST to nPWRON_RESET.
# That resets everything -- including JTAG and EmbeddedICE.
# So they must use "reset_config srst_pulls_trst".
# NOTE: an expansion board could add a trace connector ... if
# it does, change this appropriately. And reset_config too,
# assuming JTAG_DIS reroutes JTAG to that connector.
etm config $_TARGETNAME 8 demultiplexed full dummy
etm_dummy config $_TARGETNAME
# standard boards populate two 16 MB chips, but manufacturing
# options or an expansion board could change this config.
flash bank osk.u1 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
flash bank osk.u2 cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
proc osk5912_init {} {
omap5912_reset
# detect flash
flash probe 0
flash probe 1
}
$_TARGETNAME configure -event reset-init { osk5912_init }
arm7_9 dcc_downloads enable

12
debuggers/openocd/tcl/board/phone_se_j100i.cfg Normal file
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#
# Sony Ericsson J100I Phone
#
# more informations can be found on
# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
#
source [find target/ti_calypso.cfg]
# external flash
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x400000 2 2 $_TARGETNAME

88
debuggers/openocd/tcl/board/phytec_lpc3250.cfg Normal file
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source [find target/lpc3250.cfg]
adapter_nsrst_delay 200
jtag_ntrst_delay 1
adapter_khz 200
reset_config trst_and_srst separate
arm7_9 dcc_downloads enable
$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-start {
arm7_9 fast_memory_access disable
adapter_khz 200
}
$_TARGETNAME configure -event reset-end {
adapter_khz 6000
arm7_9 fast_memory_access enable
}
$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
# Bare-bones initialization of core clocks and SDRAM
proc phytec_lpc3250_init { } {
# Set clock dividers
# ARMCLK = 266.5 MHz
# HCLK = 133.25 MHz
# PERIPHCLK = 13.325 MHz
mww 0x400040BC 0
mww 0x40004050 0x140
mww 0x40004040 0x4D
mww 0x40004058 0x16250
# Init PLLs
mww 0x40004044 0x006
sleep 1 busy
mww 0x40004044 0x106
sleep 1 busy
mww 0x40004044 0x006
sleep 1 busy
mww 0x40004048 0x2
# Init SDRAM with 133 MHz timings
mww 0x40028134 0x00FFFFFF
mww 0x4002802C 0x00000008
mww 0x31080000 1
mww 0x31080008 0
mww 0x40004068 0x1C000
mww 0x31080028 0x11
mww 0x31080400 0
mww 0x31080440 0
mww 0x31080460 0
mww 0x31080480 0
# Delays
mww 0x31080030 1
mww 0x31080034 6
mww 0x31080038 10
mww 0x31080044 1
mww 0x31080048 9
mww 0x3108004C 12
mww 0x31080050 10
mww 0x31080054 1
mww 0x31080058 1
mww 0x3108005C 0
mww 0x31080100 0x5680
mww 0x31080104 0x302
# Init sequence
mww 0x31080020 0x193
sleep 1 busy
mww 0x31080024 1
mww 0x31080020 0x113
sleep 1 busy
mww 0x31080020 0x013
sleep 1 busy
mww 0x31080024 65
mww 0x31080020 0x093
mdw 0x80020000
mww 0x31080020 0x013
# SYS_CTRL remapping
mww 0x40004014 1
}

4
debuggers/openocd/tcl/board/pic-p32mx.cfg Normal file
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# The Olimex PIC-P32MX has a PIC32MX
set CPUTAPID 0x40916053
source [find target/pic32mx.cfg]

83
debuggers/openocd/tcl/board/propox_mmnet1001.cfg Normal file
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## Chip:
set CHIPNAME at91sam9260
set CPUTAPID 0x0792603f
set ENDIAN little
source [find target/at91sam9260.cfg]
$_TARGETNAME configure -event reset-init {at91sam_init}
proc at91sam_init { } {
# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
jtag_rclk 4
# Enable user reset and disable watchdog
mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
# Oscillator setup
mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
sleep 10 ;# wait 10 ms
# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
jtag_rclk 2000
mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
sleep 20 ;# wait 20 ms
mww 0xfffffc2c 0x207c3f0c ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
sleep 10 ;# wait 10 ms
mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
sleep 10 ;# wait 10 ms
mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
sleep 10 ;# wait 10 ms
# now we are running at 198.656 MHz kHz => full speed jtag
jtag_rclk 30000
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
# Configure PIO Controller for SDRAM data-lines D16-D31
# PC16-PC31 = Peripheral A: D16-D32
mww 0xfffff844 0xffff0000 ;# Interrupt Disable
mww 0xfffff854 0xffff0000 ;# Multi-Drive Disable
mww 0xfffff860 0xffff0000 ;# Pull-Up Disable
mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral A function for D15..D31
mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
mww 0xfffffc10 0x00000010 ;# Enable PIO-C Clock in PMC (PID=4)
# SD-Ram setup
mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
mww 0x20000000 0
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
mww 0x20000000 0
mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
mww 0xffffea00 0x0 ;# SDRAMC_MR : Normal Mode
mww 0x20000000 0
mww 0xFFFFEA04 0x30d ;# SDRAM Refresh Time Register
# datasheet: 8k refresh cycles / 64 ms
# MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
}

99
debuggers/openocd/tcl/board/pxa255_sst.cfg Normal file
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# A PXA255 test board with SST 39LF400A flash
#
# At reset the memory map is as follows. Note that
# the memory map changes later on as the application
# starts...
#
# RAM at 0x4000000
# Flash at 0x00000000
#
source [find target/pxa255.cfg]
# Target name is set by above
$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
proc pxa255_sst_init {} {
xscale cp15 15 0x00002001 ;#Enable CP0 and CP13 access
#
# setup GPIO
#
mww 0x40E00018 0x00008000 ;#CPSR0
sleep 20
mww 0x40E0001C 0x00000002 ;#GPSR1
sleep 20
mww 0x40E00020 0x00000008 ;#GPSR2
sleep 20
mww 0x40E0000C 0x00008000 ;#GPDR0
sleep 20
mww 0x40E00054 0x80000000 ;#GAFR0_L
sleep 20
mww 0x40E00058 0x00188010 ;#GAFR0_H
sleep 20
mww 0x40E0005C 0x60908018 ;#GAFR1_L
sleep 20
mww 0x40E0000C 0x0280E000 ;#GPDR0
sleep 20
mww 0x40E00010 0x821C88B2 ;#GPDR1
sleep 20
mww 0x40E00014 0x000F03DB ;#GPDR2
sleep 20
mww 0x40E00000 0x000F03DB ;#GPLR0
sleep 20
mww 0x40F00004 0x00000020 ;#PSSR
sleep 20
#
# setup memory controller
#
mww 0x48000008 0x01111998 ;#MSC0
sleep 20
mww 0x48000010 0x00047ff0 ;#MSC2
sleep 20
mww 0x48000014 0x00000000 ;#MECR
sleep 20
mww 0x48000028 0x00010504 ;#MCMEM0
sleep 20
mww 0x4800002C 0x00010504 ;#MCMEM1
sleep 20
mww 0x48000030 0x00010504 ;#MCATT0
sleep 20
mww 0x48000034 0x00010504 ;#MCATT1
sleep 20
mww 0x48000038 0x00004715 ;#MCIO0
sleep 20
mww 0x4800003C 0x00004715 ;#MCIO1
sleep 20
#
mww 0x48000004 0x03CA4018 ;#MDREF
sleep 20
mww 0x48000004 0x004B4018 ;#MDREF
sleep 20
mww 0x48000004 0x000B4018 ;#MDREF
sleep 20
mww 0x48000004 0x000BC018 ;#MDREF
sleep 20
mww 0x48000000 0x00001AC8 ;#MDCNFG
sleep 20
sleep 20
mww 0x48000000 0x00001AC9 ;#MDCNFG
sleep 20
mww 0x48000040 0x00000000 ;#MDMRS
sleep 20
}
$_TARGETNAME configure -event reset-init {pxa255_sst_init}
reset_config trst_and_srst
adapter_nsrst_delay 200
jtag_ntrst_delay 200
#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address

1
debuggers/openocd/tcl/board/redbee.cfg Normal file
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source [find target/mc13224v.cfg]

66
debuggers/openocd/tcl/board/rsc-w910.cfg Normal file
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# Avalue RSC-W8910 sbc
# http://www.avalue.com.tw/products/RSC-W910.cfm
# 2MB NOR Flash
# 64MB SDRAM
# 128MB NAND Flash
# Based on Nuvoton nuc910
source [find target/nuc910.cfg]
#
# reset only behaves correctly if we use srst_pulls_trst
#
reset_config trst_and_srst srst_pulls_trst
adapter_khz 1000
adapter_nsrst_delay 100
jtag_ntrst_delay 100
$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
set _NANDNAME $_CHIPNAME.nand
nand device $_NANDNAME nuc910 $_TARGETNAME
#
# Target events
#
$_TARGETNAME configure -event reset-start {adapter_khz 1000}
$_TARGETNAME configure -event reset-init {
# switch on PLL for 200MHz operation
# running from 15MHz input clock
mww 0xB0000200 0x00000030 ;# CLKEN
mww 0xB0000204 0x00000f3c ;# CLKSEL
mww 0xB0000208 0x05007000 ;# CLKDIV
mww 0xB000020C 0x00004f24 ;# PLLCON0
mww 0xB0000210 0x00002b63 ;# PLLCON1
mww 0xB000000C 0x08817fa6 ;# MFSEL
sleep 10
# we are now running @ 200MHz
# enable all openocd speed tweaks
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
adapter_khz 15000
# map nor flash to 0x20000000
# map sdram to 0x00000000
mww 0xb0001000 0x000530c1 ;# EBICON
mww 0xb0001004 0x40030084 ;# ROMCON
mww 0xb0001008 0x000010ee ;# SDCONF0
mww 0xb000100C 0x00000000 ;# SDCONF1
mww 0xb0001010 0x0000015b ;# SDTIME0
mww 0xb0001014 0x0000015b ;# SDTIME1
mww 0xb0001018 0x00000000 ;# EXT0CON
mww 0xb000101C 0x00000000 ;# EXT1CON
mww 0xb0001020 0x00000000 ;# EXT2CON
mww 0xb0001024 0x00000000 ;# EXT3CON
mww 0xb000102c 0x00ff0048 ;# CKSKEW
}

134
debuggers/openocd/tcl/board/sheevaplug.cfg Normal file
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# Marvell SheevaPlug
source [find interface/sheevaplug.cfg]
source [find target/feroceon.cfg]
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \
-work-area-backup 0
arm7_9 dcc_downloads enable
# this assumes the hardware default peripherals location before u-Boot moves it
set _FLASHNAME $_CHIPNAME.flash
nand device $_FLASHNAME orion 0 0xd8000000
proc sheevaplug_init { } {
# We need to assert DBGRQ while holding nSRST down.
# However DBGACK will be set only when nSRST is released.
# Furthermore, the JTAG interface doesn't respond at all when
# the CPU is in the WFI (wait for interrupts) state, so it is
# possible that initial tap examination failed. So let's
# re-examine the target again here when nSRST is asserted which
# should then succeed.
jtag_reset 0 1
feroceon.cpu arp_examine
halt 0
jtag_reset 0 0
wait_halt
arm mcr 15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 ;# Dunit Control Low Register
mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
mww 0xD0001428 0x00085520 ;# Dunit Control High Register
mww 0xD000147c 0x00008552 ;# Dunit Control High Register
mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
mww 0xD0001508 0x10000000 ;# CS1n Base Register
mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
mww 0xD0001514 0x00000000 ;# CS2n Size Register
mww 0xD000151C 0x00000000 ;# CS3n Size Register
mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0020204 0x00000000 ;# "
mww 0xD0010000 0x01111111 ;# MPP 0 to 7
mww 0xD0010004 0x11113322 ;# MPP 8 to 15
mww 0xD0010008 0x00001111 ;# MPP 16 to 23
mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
}
proc sheevaplug_reflash_uboot { } {
# reflash the u-Boot binary and reboot into it
sheevaplug_init
nand probe 0
nand erase 0 0x0 0xa0000
nand write 0 uboot.bin 0 oob_softecc_kw
resume
}
proc sheevaplug_reflash_uboot_env { } {
# reflash the u-Boot environment variables area
sheevaplug_init
nand probe 0
nand erase 0 0xa0000 0x40000
nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw
resume
}
proc sheevaplug_load_uboot { } {
# load u-Boot into RAM and execute it
sheevaplug_init
load_image uboot.elf
verify_image uboot.elf
resume 0x00600000
}

9
debuggers/openocd/tcl/board/smdk6410.cfg Normal file
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# Target configuration for the Samsung s3c6410 system on chip
# Tested on a SMDK6410
# Processor : ARM1176
# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
source [find target/samsung_s3c6410.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe

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