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debuggers: import openocd-0.7.0

Browse Source 
Initial check-in of openocd-0.7.0 as it can be downloaded from
http://sourceforge.net/projects/openocd/files/openocd/0.7.0/

Any modifications will follow.

Change-Id: I6949beaefd589e046395ea0cb80f4e1ab1654d55
This commit is contained in:
Lars Rademacher
2013-10-21 00:50:02 +02:00
parent 85fffe007e
commit 83d72a091e
1148 changed files with 571445 additions and 0 deletions
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57
debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_intel_16.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrh r4, [r0], #2
strh r3, [r1]
strh r4, [r1]
busy:
ldrh r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #2
b loop
done:
b done
.end

57
debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_intel_32.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldr r4, [r0], #4
str r3, [r1]
str r4, [r1]
busy:
ldr r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #4
b loop
done:
b done
.end

57
debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_intel_8.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrb r4, [r0], #1
strb r3, [r1]
strb r4, [r1]
busy:
ldrb r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #1
b loop
done:
b done
.end

75
debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_span_16.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end

66
debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, #0x80
bne busy
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end

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debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_span_32.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldr r5, [r0], #4
str r9, [r8]
str r11, [r10]
str r3, [r8]
str r5, [r1]
nop
busy:
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #4 /* 0x4 */
b code
done:
b done
.end

75
debuggers/openocd/contrib/loaders/flash/armv4_5_cfi_span_8.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrb r5, [r0], #1
strb r9, [r8]
strb r11, [r10]
strb r3, [r8]
strb r5, [r1]
nop
busy:
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #1 /* 0x1 */
b code
done:
b done
.end

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debuggers/openocd/contrib/loaders/flash/armv7m_cfi_span_16.s Normal file
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/***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end

60
debuggers/openocd/contrib/loaders/flash/armv7m_io.s Normal file
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/***************************************************************************
* Copyright (C) 2013 by Henrik Nilsson *
* henrik.nilsson@bytequest.se *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 4
/* Inputs:
* r0 buffer address
* r1 NAND data address (byte wide)
* r2 buffer length
*/
read:
ldrb r3, [r1]
strb r3, [r0], #1
subs r2, r2, #1
bne read
done_read:
bkpt #0
.align 4
/* Inputs:
* r0 NAND data address (byte wide)
* r1 buffer address
* r2 buffer length
*/
write:
ldrb r3, [r1], #1
strb r3, [r0]
subs r2, r2, #1
bne write
done_write:
bkpt #0
.end

114
debuggers/openocd/contrib/loaders/flash/efm32.S Normal file
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/***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (word-32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
/* offsets of registers from flash reg base */
#define EFM32_MSC_WRITECTRL_OFFSET 0x008
#define EFM32_MSC_WRITECMD_OFFSET 0x00c
#define EFM32_MSC_ADDRB_OFFSET 0x010
#define EFM32_MSC_WDATA_OFFSET 0x018
#define EFM32_MSC_STATUS_OFFSET 0x01c
#define EFM32_MSC_LOCK_OFFSET 0x03c
/* unlock MSC */
ldr r6, =#0x1b71
str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
/* set WREN to 1 */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
/* store address in MSC_ADDRB */
str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
/* set LADDRIM bit */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
/* check status for INVADDR and/or LOCKED */
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #6
tst r6, r7
bne error
/* wait for WDATAREADY */
wait_wdataready:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #8
tst r6, r7
beq wait_wdataready
/* load data to WDATA */
ldr r6, [r5]
str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
/* set WRITEONCE bit */
movs r6, #8
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
adds r5, #4 /* rp++ */
adds r4, #4 /* target_address++ */
/* wait until BUSY flag is reset */
busy:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #1
tst r6, r7
bne busy
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0

176
debuggers/openocd/contrib/loaders/flash/lpcspifi_erase.S Normal file
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/***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = start address, status (out)
* r1 = count
* r2 = erase command
* r3 = block size
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
erase:
bl cs_down
mov.w r9, r2 /* Send the erase command */
bl write_data
write_address:
lsr r9, r0, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r0, #8
bl write_data
mov.w r9, r0
bl write_data
bl cs_up
wait_flash_busy: /* Wait for the flash to finish the previous erase */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
subs r1, r1, #1 /* decrement count */
cbz r1, exit /* Exit if we have written everything */
add r0, r3 /* Move the address up by the block size */
b write_enable /* Start a new block erase */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
exit:
bkpt #0x00
.end

102
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/***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
/***************************************************************************
* This is an algorithm for the LPC43xx family (and probably the LPC18xx *
* family as well, though they have not been tested) that will initialize *
* memory-mapped SPI flash accesses. Unfortunately NXP has published *
* neither the ROM source code that performs this initialization nor the *
* register descriptions necessary to do so, so this code is necessary to *
* call into the ROM SPIFI API. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/*
* Params :
* r0 = spifi clock speed
*/
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
#define SPIFI_ROM_TABLE_BASE_LOW 0x0118
code:
mov.w r8, r0
sub sp, #0x84
add r7, sp, #0x0
/* Initialize SPIFI pins */
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0xf3
str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #IOCONFIG_BASE_LOW
movt r2, #IOCONFIG_BASE_HIGH
mov.w r1, #IOCONFIG_BASE_LOW
movt r1, #IOCONFIG_BASE_HIGH
mov.w r0, #IOCONFIG_BASE_LOW
movt r0, #IOCONFIG_BASE_HIGH
mov.w r4, #0xd3
str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
mov r0, r4
str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
mov r1, r0
str.w r1, [r2, #IOCONFIG_WP_OFFSET]
str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0x13
str.w r2, [r3, #IOCONFIG_CS_OFFSET]
/* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
/* on initialization arguments. */
movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
ldr r3, [r3, #0x0]
ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
/* Set up function arguments */
movw r0, #0x3b4
movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
mov.w r3, r8 /* SPIFI clock speed (12MHz) */
blx r4 /* Call the init function */
b done
done:
bkpt #0
.end

210
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/***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - temp
* r11 - current page end address
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
mov.w r11, #0x00
find_next_page_boundary:
add r11, r4 /* Increment to the next page */
cmp r11, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
page_program:
bl cs_down
mov.w r9, #0x02 /* Send the page program command */
bl write_data
write_address:
lsr r9, r2, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r2, #8
bl write_data
mov.w r9, r2
bl write_data
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cbz r3, exit /* Exit if we have written everything */
add r2, #1 /* Increment flash address by 1 */
cmp r11, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
bl cs_up /* Otherwise, end the command and keep going w/ the next page */
add r11, r4 /* Move up the end-of-page address by the page size*/
wait_flash_busy: /* Wait for the flash to finish the previous page write */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
b write_enable /* If it is done, start a new page write */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6
bkpt #0x00
.end

132
debuggers/openocd/contrib/loaders/flash/pic32mx.s Normal file
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/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arch m4k
.set noreorder
.set noat
/* params:
* $a0 src adr - ram + result
* $a1 dest adr - flash
* $a2 count (32bit words)
* vars
*
* temps:
* $t0, $t1, $t2, $t3, $t4, $t5
* $s0, $s1, $s3, $s4, $s5
*/
.type main, @function
.global main
.ent main
main:
/* setup constants */
lui $t0, 0xaa99
ori $t0, 0x6655 /* NVMKEY1 */
lui $t1, 0x5566
ori $t1, 0x99AA /* NVMKEY2 */
lui $t2, 0xBF80
ori $t2, 0xF400 /* NVMCON */
ori $t3, $zero, 0x4003 /* NVMCON row write cmd */
ori $t4, $zero, 0x8000 /* NVMCON start cmd */
write_row:
/* can we perform a row write: 128 32bit words */
sltiu $s3, $a2, 128
bne $s3, $zero, write_word
ori $t5, $zero, 0x4000 /* NVMCON clear cmd */
/* perform row write 512 bytes */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
sw $a0, 64($t2) /* set NVMSRCADDR with src addr - real addr */
bal progflash
addiu $a0, $a0, 512
addiu $a1, $a1, 512
beq $zero, $zero, write_row
addiu $a2, $a2, -128
write_word:
/* write 32bit words */
lui $s5, 0xa000
ori $s5, 0x0000
or $a0, $a0, $s5 /* convert to virtual addr */
beq $zero, $zero, next_word
ori $t3, $zero, 0x4001 /* NVMCON word write cmd */
prog_word:
lw $s4, 0($a0) /* load data - from virtual addr */
sw $s4, 48($t2) /* set NVMDATA with data */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
bal progflash
addiu $a0, $a0, 4
addiu $a1, $a1, 4
addiu $a2, $a2, -1
next_word:
bne $a2, $zero, prog_word
nop
done:
beq $zero, $zero, exit
addiu $a0, $zero, 0
error:
/* save result to $a0 */
addiu $a0, $s1, 0
exit:
sdbbp
.end main
.type progflash, @function
.global progflash
.ent progflash
progflash:
sw $t3, 0($t2) /* set NVMWREN */
sw $t0, 16($t2) /* write NVMKEY1 */
sw $t1, 16($t2) /* write NVMKEY2 */
sw $t4, 8($t2) /* start operation */
waitflash:
lw $s0, 0($t2)
and $s0, $s0, $t4
bne $s0, $zero, waitflash
nop
/* following is to comply with errata #34
* 500ns delay required */
nop
nop
nop
nop
/* check for errors */
lw $s1, 0($t2)
andi $s1, $zero, 0x3000
bne $s1, $zero, error
sw $t5, 4($t2) /* clear NVMWREN */
jr $ra
nop
.end progflash

78
debuggers/openocd/contrib/loaders/flash/stellaris.s Normal file
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/***************************************************************************
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start
* r1 = workarea end
* r2 = target address
* r3 = count (32bit words)
*
* Clobbered:
* r4 = pFLASH_CTRL_BASE
* r5 = FLASHWRITECMD
* r7 - rp
* r8 - wp, tmp
*/
write:
ldr r4, pFLASH_CTRL_BASE
ldr r5, FLASHWRITECMD
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
mainloop:
str r2, [r4, #0] /* FMA - write address */
add r2, r2, #4 /* increment target address */
ldr r8, [r7], #4
str r8, [r4, #4] /* FMD - write data */
str r5, [r4, #8] /* FMC - enable write */
busy:
ldr r8, [r4, #8]
tst r8, #1
bne busy
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement word count */
cbz r3, exit /* loop if not done */
b wait_fifo
exit:
bkpt #0
pFLASH_CTRL_BASE: .word 0x400FD000
FLASHWRITECMD: .word 0xA4420001

76
debuggers/openocd/contrib/loaders/flash/stm32f1x.S Normal file
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/***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (halfword-16bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldrh r6, [r5] /* "*target_address++ = *rp++" */
strh r6, [r4]
adds r5, #2
adds r4, #2
busy:
ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
movs r7, #1
tst r6, r7
bne busy
movs r7, #0x14 /* check the error bits */
tst r6, r7
bne error
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement halfword count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0

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debuggers/openocd/contrib/loaders/flash/stm32f2x.S Normal file
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/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (16bit words)
* r4 = flash base
*
* Clobbered:
* r6 - temp
* r7 - rp
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
ldr r6, STM32_PROG16
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
bne error /* fail... */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement halfword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/

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debuggers/openocd/contrib/loaders/flash/stm32lx.S Normal file
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/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2011 Clement Burin des Roziers *
* clement.burin-des-roziers@hikob.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
// Build : arm-eabi-gcc -c stm32lx.S
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
.global write
/*
r0 - destination address
r1 - source address
r2 - count
*/
// Set 0 to r3
movs r3, #0
// Go to compare
b.n test_done
write_word:
// Load one word from address in r0, increment by 4
ldr.w ip, [r1], #4
// Store the word to address in r1, increment by 4
str.w ip, [r0], #4
// Increment r3
adds r3, #1
test_done:
// Compare r3 and r2
cmp r3, r2
// Loop if not zero
bcc.n write_word
// Set breakpoint to exit
bkpt #0x00

59
debuggers/openocd/contrib/loaders/flash/str7x.s Normal file
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/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv4t
.section .init
/*
r0 source address
r1 address
r2 FLASH_CR0
r3 dword count
r4 result
r5 busy mask
*/
write:
mov r4, #0x10000000 /* set DWPG bit */
str r4, [r2, #0x0] /* FLASH_CR0 */
str r1, [r2, #0x10] /* FLASH_AR */
ldr r4, [r0], #4 /* load data */
str r4, [r2, #0x8] /* FLASH_DR0 */
ldr r4, [r0], #4 /* load data */
str r4, [r2, #0xc] /* FLASH_DR1 */
mov r4, #0x90000000 /* set DWPG and WMS bits */
str r4, [r2, #0x0] /* FLASH_CR0 */
busy:
ldr r4, [r2, #0x0] /* FLASH_CR0 */
tst r4, r5
bne busy
ldr r4, [r2, #0x14] /* FLASH_ER */
tst r4, #0xff /* do we have errors */
tsteq r4, #0x100 /* write protection set */
bne exit
add r1, r1, #0x8 /* next 8 bytes */
subs r3, r3, #1 /* decremment dword count */
bne write
exit:
b exit
.end

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debuggers/openocd/contrib/loaders/flash/str9x.s Normal file
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/***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
.text
.arm
.arch armv5t
.section .init
/*
r0 source address (in)
r1 target address (in)
r2 word count (in)
r3 result (out)
*/
write:
bic r4, r1, #3 /* word address */
mov r3, #0x40 /* write command */
strh r3, [r4, #0]
ldrh r3, [r0], #2 /* read data */
strh r3, [r1], #2 /* write data */
mov r3, #0x70 /* status command */
strh r3, [r4, #0]
busy:
ldrb r3, [r4, #0] /* status */
tst r3, #0x80
beq busy
mov r5, #0x50 /* clear status command */
strh r5, [r4, #0]
mov r5, #0xFF /* read array */
strh r5, [r4, #0]
tst r3, #0x12
bne exit
subs r2, r2, #1 /* decremment word count */
bne write
exit:
bkpt #0
.end