diff --git a/src/core/sal/bochs/BochsCPU.cc b/src/core/sal/bochs/BochsCPU.cc
index 63f03e84..237cdd4a 100644
--- a/src/core/sal/bochs/BochsCPU.cc
+++ b/src/core/sal/bochs/BochsCPU.cc
@@ -11,68 +11,68 @@ regdata_t BochsCPU::getRegisterContent(const Register* reg) const
 	// TODO: BX_CPU(0) *always* correct?
 
 	if (reg->getId() == RID_FLAGS) { // EFLAGS register?
-		return static_cast<regdata_t>(BX_CPU(id)->read_eflags());
+		return static_cast<regdata_t>(BX_CPU(m_Id)->read_eflags());
 	}
 
 	// untested
 	if (reg->getId() == RID_CR0) { // CR0 register?
-		return static_cast<regdata_t>(BX_CPU(id)->read_CR0());
+		return static_cast<regdata_t>(BX_CPU(m_Id)->read_CR0());
 	}
 
 	// untested
 	if (reg->getId() == RID_CR2) { // CR2 register?
-		return static_cast<regdata_t>(BX_CPU(id)->cr2);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->cr2);
 	}
 
 	if (reg->getId() == RID_CR3) { // CR3 register?
-		return static_cast<regdata_t>(BX_CPU(id)->cr3);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->cr3);
 	}
 
 	// untested
 	if (reg->getId() == RID_CR4) { // CR4 register?
-		return static_cast<regdata_t>(BX_CPU(id)->read_CR4());
+		return static_cast<regdata_t>(BX_CPU(m_Id)->read_CR4());
 	}
 
 	// untested
 	if (reg->getId() == RID_CS) { // CS register?
-		return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_CS].selector.value);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_CS].selector.value);
 	}
 
 	// untested
 	if (reg->getId() == RID_DS) { // DS register?
-		return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_DS].selector.value);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_DS].selector.value);
 	}
 
 	// untested
 	if (reg->getId() == RID_ES) { // ES register?
-		return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_ES].selector.value);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_ES].selector.value);
 	}
 
 	// untested
 	if (reg->getId() == RID_FS) { // FS register?
-		return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_FS].selector.value);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_FS].selector.value);
 	}
 
 	// untested
 	if (reg->getId() == RID_GS) { // GS register?
-		return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_GS].selector.value);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_GS].selector.value);
 	}
 
 	// untested
 	if (reg->getId() == RID_SS) { // SS register?
-		return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_SS].selector.value);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->sregs[BX_SEG_REG_SS].selector.value);
 	}
 
 #ifdef SIM_SUPPORT_64
 	if (reg->getId() == RID_PC) // program counter?
-		return static_cast<regdata_t>(BX_CPU(id)->gen_reg[BX_64BIT_REG_RIP].rrx);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[BX_64BIT_REG_RIP].rrx);
 	else // 64 bit general purpose registers
-		return static_cast<regdata_t>(BX_CPU(id)->gen_reg[reg->getId()].rrx);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[reg->getId()].rrx);
 #else // 32 bit mode
 	if (reg->getId() == RID_PC)
-		return static_cast<regdata_t>(BX_CPU(id)->gen_reg[BX_32BIT_REG_EIP].dword.erx);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[BX_32BIT_REG_EIP].dword.erx);
 	else // 32 bit general purpose registers
-		return static_cast<regdata_t>(BX_CPU(id)->gen_reg[reg->getId()].dword.erx);
+		return static_cast<regdata_t>(BX_CPU(m_Id)->gen_reg[reg->getId()].dword.erx);
 #endif // SIM_SUPPORT_64
 }
 
@@ -85,72 +85,72 @@ void BochsCPU::setRegisterContent(const Register* reg, regdata_t value)
 	  #ifdef SIM_SUPPORT_64
 		// We are in 64 bit mode: Just assign the lower 32 bits!
 		regdata_t regdata = getRegisterContent(reg);
-		BX_CPU(id)->writeEFlags((regdata & 0xFFFFFFFF00000000ULL) | (value & 0xFFFFFFFFULL),
+		BX_CPU(m_Id)->writeEFlags((regdata & 0xFFFFFFFF00000000ULL) | (value & 0xFFFFFFFFULL),
 								0xffffffff);
 	  #else
-		BX_CPU(id)->writeEFlags(value, 0xffffffff);
+		BX_CPU(m_Id)->writeEFlags(value, 0xffffffff);
 	  #endif
-		BX_CPU(id)->force_flags();
+		BX_CPU(m_Id)->force_flags();
 		return;
 	}
 
 	#ifndef __puma
 	// untested
 	if (reg->getId() == RID_CR0) { // CR0 register?
-		BX_CPU(id)->SetCR0(value);
+		BX_CPU(m_Id)->SetCR0(value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_CR2) { // CR2 register?
-		BX_CPU(id)->cr2 = value;
+		BX_CPU(m_Id)->cr2 = value;
 		return;
 	}
 
 	if (reg->getId() == RID_CR3) { // CR3 register?
-		BX_CPU(id)->SetCR3(value);
+		BX_CPU(m_Id)->SetCR3(value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_CR4) { // CR4 register?
-		BX_CPU(id)->SetCR4(value);
+		BX_CPU(m_Id)->SetCR4(value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_CS) { // CS register?
-		BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_CS], value);
+		BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_CS], value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_DS) { // DS register?
-		BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_DS], value);
+		BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_DS], value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_ES) { // ES register?
-		BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_ES], value);
+		BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_ES], value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_FS) { // FS register?
-		BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_FS], value);
+		BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_FS], value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_GS) { // GS register?
-		BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_GS], value);
+		BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_GS], value);
 		return;
 	}
 
 	// untested
 	if (reg->getId() == RID_SS) { // SS register?
-		BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_SS], value);
+		BX_CPU(m_Id)->load_seg_reg(&BX_CPU(m_Id)->sregs[BX_SEG_REG_SS], value);
 		return;
 	}
 	#endif
@@ -158,14 +158,14 @@ void BochsCPU::setRegisterContent(const Register* reg, regdata_t value)
 	regdata_t* pData;
 #ifdef SIM_SUPPORT_64
 	if (reg->getId() == RID_PC) // program counter?
-		pData = &(BX_CPU(id)->gen_reg[BX_64BIT_REG_RIP].rrx);
+		pData = &(BX_CPU(m_Id)->gen_reg[BX_64BIT_REG_RIP].rrx);
 	else // 64 bit general purpose registers
-		pData = &(BX_CPU(id)->gen_reg[reg->getId()].rrx);
+		pData = &(BX_CPU(m_Id)->gen_reg[reg->getId()].rrx);
 #else // 32 bit mode
 	if (reg->getId() == RID_PC)
-		pData = &(BX_CPU(id)->gen_reg[BX_32BIT_REG_EIP].dword.erx);
+		pData = &(BX_CPU(m_Id)->gen_reg[BX_32BIT_REG_EIP].dword.erx);
 	else // 32 bit general purpose registers
-		pData = &(BX_CPU(id)->gen_reg[reg->getId()].dword.erx);
+		pData = &(BX_CPU(m_Id)->gen_reg[reg->getId()].dword.erx);
 #endif // SIM_SUPPORT_64
 	*pData = value;
 }
diff --git a/src/core/sal/bochs/BochsCPU.hpp b/src/core/sal/bochs/BochsCPU.hpp
index 353a9095..6663a390 100644
--- a/src/core/sal/bochs/BochsCPU.hpp
+++ b/src/core/sal/bochs/BochsCPU.hpp
@@ -67,41 +67,41 @@ public:
 	 * Returns \c true if the corresponding flag is set, or \c false
 	 * otherwise.
 	 */
-	bool getCarryFlag() const             { return BX_CPU(0)->get_CF();   }
-	bool getParityFlag() const            { return BX_CPU(0)->get_PF();   }
-	bool getZeroFlag() const              { return BX_CPU(0)->get_ZF();   }
-	bool getSignFlag() const              { return BX_CPU(0)->get_SF();   }
-	bool getOverflowFlag() const          { return BX_CPU(0)->get_OF();   }
-	bool getTrapFlag() const              { return BX_CPU(0)->get_TF();   }
-	bool getInterruptFlag() const         { return BX_CPU(0)->get_IF();   }
-	bool getDirectionFlag() const         { return BX_CPU(0)->get_DF();   }
-	unsigned getIOPrivilegeLevel() const  { return BX_CPU(0)->get_IOPL(); }
-	bool getNestedTaskFlag() const        { return BX_CPU(0)->get_NT();   }
-	bool getResumeFlag() const            { return BX_CPU(0)->get_RF();   }
-	bool getVMFlag() const                { return BX_CPU(0)->get_VM();   }
-	bool getAlignmentCheckFlag() const    { return BX_CPU(0)->get_AC();   }
-	bool getVInterruptFlag() const        { return BX_CPU(0)->get_VIF();  }
-	bool getVInterruptPendingFlag() const { return BX_CPU(0)->get_VIP();  }
-	bool getIdentificationFlag() const    { return BX_CPU(0)->get_ID();   }
+	bool getCarryFlag() const             { return BX_CPU(m_Id)->get_CF();   }
+	bool getParityFlag() const            { return BX_CPU(m_Id)->get_PF();   }
+	bool getZeroFlag() const              { return BX_CPU(m_Id)->get_ZF();   }
+	bool getSignFlag() const              { return BX_CPU(m_Id)->get_SF();   }
+	bool getOverflowFlag() const          { return BX_CPU(m_Id)->get_OF();   }
+	bool getTrapFlag() const              { return BX_CPU(m_Id)->get_TF();   }
+	bool getInterruptFlag() const         { return BX_CPU(m_Id)->get_IF();   }
+	bool getDirectionFlag() const         { return BX_CPU(m_Id)->get_DF();   }
+	unsigned getIOPrivilegeLevel() const  { return BX_CPU(m_Id)->get_IOPL(); }
+	bool getNestedTaskFlag() const        { return BX_CPU(m_Id)->get_NT();   }
+	bool getResumeFlag() const            { return BX_CPU(m_Id)->get_RF();   }
+	bool getVMFlag() const                { return BX_CPU(m_Id)->get_VM();   }
+	bool getAlignmentCheckFlag() const    { return BX_CPU(m_Id)->get_AC();   }
+	bool getVInterruptFlag() const        { return BX_CPU(m_Id)->get_VIF();  }
+	bool getVInterruptPendingFlag() const { return BX_CPU(m_Id)->get_VIP();  }
+	bool getIdentificationFlag() const    { return BX_CPU(m_Id)->get_ID();   }
 	/**
 	 * Sets/resets various status FLAGS.
 	 */
-	void setCarryFlag(bool bit)             { BX_CPU(0)->set_CF(bit);   }
-	void setParityFlag(bool bit)            { BX_CPU(0)->set_PF(bit);   }
-	void setZeroFlag(bool bit)              { BX_CPU(0)->set_ZF(bit);   }
-	void setSignFlag(bool bit)              { BX_CPU(0)->set_SF(bit);   }
-	void setOverflowFlag(bool bit)          { BX_CPU(0)->set_OF(bit);   }
-	void setTrapFlag(bool bit)              { BX_CPU(0)->set_TF(bit);   }
-	void setInterruptFlag(bool bit)         { BX_CPU(0)->set_IF(bit);   }
-	void setDirectionFlag(bool bit)         { BX_CPU(0)->set_DF(bit);   }
-	void setIOPrivilegeLevel(unsigned lvl)  { BX_CPU(0)->set_IOPL(lvl); }
-	void setNestedTaskFlag(bool bit)        { BX_CPU(0)->set_NT(bit);   }
-	void setResumeFlag(bool bit)            { BX_CPU(0)->set_RF(bit);   }
-	void setVMFlag(bool bit)                { BX_CPU(0)->set_VM(bit);   }
-	void setAlignmentCheckFlag(bool bit)    { BX_CPU(0)->set_AC(bit);   }
-	void setVInterruptFlag(bool bit)        { BX_CPU(0)->set_VIF(bit);  }
-	void setVInterruptPendingFlag(bool bit) { BX_CPU(0)->set_VIP(bit);  }
-	void setIdentificationFlag(bool bit)    { BX_CPU(0)->set_ID(bit);   }
+	void setCarryFlag(bool bit)             { BX_CPU(m_Id)->set_CF(bit);   }
+	void setParityFlag(bool bit)            { BX_CPU(m_Id)->set_PF(bit);   }
+	void setZeroFlag(bool bit)              { BX_CPU(m_Id)->set_ZF(bit);   }
+	void setSignFlag(bool bit)              { BX_CPU(m_Id)->set_SF(bit);   }
+	void setOverflowFlag(bool bit)          { BX_CPU(m_Id)->set_OF(bit);   }
+	void setTrapFlag(bool bit)              { BX_CPU(m_Id)->set_TF(bit);   }
+	void setInterruptFlag(bool bit)         { BX_CPU(m_Id)->set_IF(bit);   }
+	void setDirectionFlag(bool bit)         { BX_CPU(m_Id)->set_DF(bit);   }
+	void setIOPrivilegeLevel(unsigned lvl)  { BX_CPU(m_Id)->set_IOPL(lvl); }
+	void setNestedTaskFlag(bool bit)        { BX_CPU(m_Id)->set_NT(bit);   }
+	void setResumeFlag(bool bit)            { BX_CPU(m_Id)->set_RF(bit);   }
+	void setVMFlag(bool bit)                { BX_CPU(m_Id)->set_VM(bit);   }
+	void setAlignmentCheckFlag(bool bit)    { BX_CPU(m_Id)->set_AC(bit);   }
+	void setVInterruptFlag(bool bit)        { BX_CPU(m_Id)->set_VIF(bit);  }
+	void setVInterruptPendingFlag(bool bit) { BX_CPU(m_Id)->set_VIP(bit);  }
+	void setIdentificationFlag(bool bit)    { BX_CPU(m_Id)->set_ID(bit);   }
 	/**
 	 * Returns the current id of this CPU.
 	 * @return the current id