diff --git a/simulators/gem5/src/arch/arm/faults.cc b/simulators/gem5/src/arch/arm/faults.cc index 061392f5..ac8f1426 100644 --- a/simulators/gem5/src/arch/arm/faults.cc +++ b/simulators/gem5/src/arch/arm/faults.cc @@ -49,6 +49,9 @@ #include "debug/Faults.hh" #include "sim/full_system.hh" +#include "sal/SALInst.hpp" +#include "config/FailConfig.hpp" + namespace ArmISA { @@ -95,9 +98,25 @@ ArmFault::getVector(ThreadContext *tc) } -void +void ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) { + // DanceOS + #ifdef CONFIG_EVENT_TRAP + // GEM5 throws a reset trap during initialization. + // This happens before the startup function is called. + // This leads to problems because the startup function fills the m_CPUs list. + // m_CPUs is needed for the TrapListener. + // Therefore, we only react on traps after initialization. + // e.g. look at gem5/src/arch/arm/faults.cc -> ArmFault::invoke function. + if (fail::simulator.isInitialized()) { + fail::ConcreteCPU* cpu = &fail::simulator.getCPU(tc->cpuId()); + // Instead of a number to a trap the offset is returned for GEM5. + // see: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Babfeega.html + fail::simulator.onTrap(cpu, offset()); + } + #endif + // ARM ARM B1.6.3 FaultBase::invoke(tc); if (!FullSystem) diff --git a/simulators/gem5/src/cpu/simple/atomic.cc b/simulators/gem5/src/cpu/simple/atomic.cc index 5e05be93..4e70d77c 100644 --- a/simulators/gem5/src/cpu/simple/atomic.cc +++ b/simulators/gem5/src/cpu/simple/atomic.cc @@ -289,17 +289,9 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, } dcache_access = true; - // FAIL* - #ifdef CONFIG_EVENT_TRAP - if(pkt.isError()) { - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); - fail::simulator.onTrap(cpu, 0); - } - #endif - assert(!pkt.isError()); - // FAIL* + // DanceOS #ifdef CONFIG_EVENT_MEMREAD fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, instAddr()); @@ -405,17 +397,9 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, } dcache_access = true; - // FAIL* - #ifdef CONFIG_EVENT_TRAP - if(pkt.isError()) { - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); - fail::simulator.onTrap(cpu, 0); - } - #endif - assert(!pkt.isError()); - // FAIL* + // DanceOS #ifdef CONFIG_EVENT_MEMWRITE fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, instAddr()); @@ -525,15 +509,6 @@ AtomicSimpleCPU::tick() else icache_latency = icachePort.sendAtomic(&ifetch_pkt); - // FAIL* - #ifdef CONFIG_EVENT_TRAP - if(ifetch_pkt.isError()) - { - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); - fail::simulator.onTrap(cpu, 0); - } - #endif - assert(!ifetch_pkt.isError()); // ifetch_req is initialized to read the instruction directly diff --git a/simulators/gem5/src/cpu/simple/base.cc b/simulators/gem5/src/cpu/simple/base.cc index 5bb8a653..486280f3 100644 --- a/simulators/gem5/src/cpu/simple/base.cc +++ b/simulators/gem5/src/cpu/simple/base.cc @@ -332,10 +332,10 @@ BaseSimpleCPU::checkForInterrupts() Fault interrupt = interrupts->getInterrupt(tc); if (interrupt != NoFault) { - // FAIL* - #ifdef CONFIG_EVENT_INTERRUPT - fail::simulator.onInterrupt(dynamic_cast(interrupt.get())->offset(), false); - #endif + // DanceOS + #ifdef CONFIG_EVENT_INTERRUPT + fail::simulator.onInterrupt(dynamic_cast(interrupt.get())->offset(), false); + #endif fetchOffset = 0; interrupts->updateIntrInfo(tc); interrupt->invoke(tc); diff --git a/simulators/gem5/src/dev/arm/pl011.cc b/simulators/gem5/src/dev/arm/pl011.cc index 34565083..97e178ea 100644 --- a/simulators/gem5/src/dev/arm/pl011.cc +++ b/simulators/gem5/src/dev/arm/pl011.cc @@ -185,13 +185,8 @@ Pl011::write(PacketPtr pkt) switch (daddr) { case UART_DR: if ((data & 0xFF) == 0x04 && endOnEOT) { - // FAIL* - #ifdef CONFIG_EVENT_TRAP - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0); - fail::simulator.onTrap(cpu, 0); - #endif exitSimLoop("UART received EOT", 0); - } + } term->out(data & 0xFF); diff --git a/simulators/gem5/src/dev/isa_fake.cc b/simulators/gem5/src/dev/isa_fake.cc index 523fc8e8..1f5fdd77 100644 --- a/simulators/gem5/src/dev/isa_fake.cc +++ b/simulators/gem5/src/dev/isa_fake.cc @@ -116,14 +116,7 @@ IsaFake::write(PacketPtr pkt) data = pkt->get(); break; default: - // FAIL* - #ifdef CONFIG_EVENT_TRAP - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0); - fail::simulator.onTrap(cpu, 0); - #endif - panic("invalid access size!\n"); - - + panic("invalid access size!\n"); } warn("Device %s accessed by write to address %#x size=%d data=%#x\n", name(), pkt->getAddr(), pkt->getSize(), data); diff --git a/simulators/gem5/src/mem/bus.cc b/simulators/gem5/src/mem/bus.cc index 032e9a43..638086d6 100644 --- a/simulators/gem5/src/mem/bus.cc +++ b/simulators/gem5/src/mem/bus.cc @@ -294,11 +294,6 @@ BaseBus::findPort(Addr addr) // we should use the range for the default port and it did not // match, or the default port is not set - // FAIL* - #ifdef CONFIG_EVENT_TRAP - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(0); - fail::simulator.onTrap(cpu, 0); - #endif fatal("Unable to find destination for addr %#llx on bus %s\n", addr, name()); } diff --git a/simulators/gem5/src/sim/root.cc b/simulators/gem5/src/sim/root.cc index 9ac9c57f..18b000c2 100644 --- a/simulators/gem5/src/sim/root.cc +++ b/simulators/gem5/src/sim/root.cc @@ -129,11 +129,11 @@ Root::loadState(Checkpoint *cp) } -// FAIL* +// DanceOS void Root::startup() { - fail::simulator.startup(); + fail::simulator.startup(); } void