qemu: incomplete QEMUx86CPU implementation
Change-Id: I3598e420f95e75523895f8cf496f443a92a687ec
This commit is contained in:
19
src/core/sal/qemu/QEMUx86CPU.cc
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19
src/core/sal/qemu/QEMUx86CPU.cc
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#include "QEMUx86CPU.hpp"
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#include "../SALConfig.hpp"
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#include <cassert>
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namespace fail {
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regdata_t QEMUX86CPU::getRegisterContent(const Register* reg) const
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{
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// TODO
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return 0;
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}
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void QEMUX86CPU::setRegisterContent(const Register* reg, regdata_t value)
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{
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// TODO
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}
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} // end-of-namespace: fail
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113
src/core/sal/qemu/QEMUx86CPU.hpp
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src/core/sal/qemu/QEMUx86CPU.hpp
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#ifndef __QEMU_X86_CPU_HPP__
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#define __QEMU_X86_CPU_HPP__
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#include "../x86/X86Architecture.hpp"
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#include "../x86/X86CPUState.hpp"
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namespace fail {
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/**
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* \class QEMUX86CPU
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*
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* \c QEMUX86CPU is the concrete x86 CPU implementation for the QEMU processor
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* emulator. It implements the CPU interfaces \c X86Architecture and
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* \c X86CPUState.
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*/
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class QEMUX86CPU : public X86Architecture, public X86CPUState {
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private:
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unsigned int m_Id; //!< the numeric CPU identifier (ID)
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public:
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/**
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* Initializes the CPU with the provided \c id.
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* @param id the CPU identifier (the 1st CPU is CPU0 -> id = 0, and so forth)
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*/
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QEMUX86CPU(unsigned int id) : m_Id(id) { }
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/**
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* Virtual Destructor is required.
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*/
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virtual ~QEMUX86CPU() { }
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/**
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* Retrieves the content of the register \c reg.
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* @param reg the register pointer of interest (cannot be \c NULL)
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* @return the content of the register \c reg
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*/
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regdata_t getRegisterContent(const Register* reg) const;
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/**
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* Sets the content of the register \c reg to \c value.
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* @param reg the destination register object pointer (cannot be \c NULL)
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* @param value the new value to assign
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*/
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void setRegisterContent(const Register* reg, regdata_t value);
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/**
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* Returns the current instruction pointer (aka program counter).
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* @return the current (e)ip register content
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*/
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address_t getInstructionPointer() const { return getRegisterContent(getRegister(RID_PC)); }
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/**
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* Returns the current stack pointer.
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* @return the current (e)sp register content
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*/
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address_t getStackPointer() const { return getRegisterContent(getRegister(RID_CSP)); }
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/**
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* Returns the current base pointer.
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* @return the current (e)bp register content
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*/
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address_t getBasePointer() const { return getRegisterContent(getRegister(RID_CBP)); }
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/**
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* Returns the current (E)FLAGS.
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* @return the current (E)FLAGS processor register content
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*/
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regdata_t getFlagsRegister() const { return getRegisterContent(getRegister(RID_FLAGS)); }
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/**
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* Returns \c true if the corresponding flag is set, or \c false
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* otherwise.
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* TODO not implemented
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*/
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bool getCarryFlag() const { return false; }
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bool getParityFlag() const { return false; }
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bool getZeroFlag() const { return false; }
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bool getSignFlag() const { return false; }
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bool getOverflowFlag() const { return false; }
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bool getTrapFlag() const { return false; }
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bool getInterruptFlag() const { return false; }
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bool getDirectionFlag() const { return false; }
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unsigned getIOPrivilegeLevel() const { return false; }
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bool getNestedTaskFlag() const { return false; }
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bool getResumeFlag() const { return false; }
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bool getVMFlag() const { return false; }
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bool getAlignmentCheckFlag() const { return false; }
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bool getVInterruptFlag() const { return false; }
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bool getVInterruptPendingFlag() const { return false; }
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bool getIdentificationFlag() const { return false; }
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/**
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* Sets/resets various status FLAGS.
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* TODO not implemented
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*/
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void setCarryFlag(bool bit) { }
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void setParityFlag(bool bit) { }
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void setZeroFlag(bool bit) { }
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void setSignFlag(bool bit) { }
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void setOverflowFlag(bool bit) { }
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void setTrapFlag(bool bit) { }
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void setInterruptFlag(bool bit) { }
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void setDirectionFlag(bool bit) { }
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void setIOPrivilegeLevel(unsigned lvl) { }
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void setNestedTaskFlag(bool bit) { }
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void setResumeFlag(bool bit) { }
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void setVMFlag(bool bit) { }
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void setAlignmentCheckFlag(bool bit) { }
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void setVInterruptFlag(bool bit) { }
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void setVInterruptPendingFlag(bool bit) { }
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void setIdentificationFlag(bool bit) { }
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/**
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* Returns the current id of this CPU.
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* @return the current id
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*/
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unsigned int getId() const { return m_Id; }
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};
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typedef QEMUX86CPU ConcreteCPU; //!< the concrete QEMUX86CPU type
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} // end-of-namespace: fail
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#endif // __QEMU_X86_CPU_HPP__
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