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T32: Integrated Register read/write calls

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* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
hoffmann
2013-02-15 18:06:02 +00:00
parent a7e5d2373f
commit 39a6415001
30 changed files with 439 additions and 201 deletions
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2
src/core/sal/gem5/Gem5ArmCPU.hpp
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@ -10,7 +10,7 @@ namespace fail {
/**
* \class Gem5ArmCPU
*
*
* \c Gem5ArmCPU is the concrete CPU implementation for the gem5 ARM simulator. It
* implements the CPU interfaces \c ArmArchitecture and \c ArmCPUState.
* \c ArmArchitecture refers to architectural information (e.g. register \a count)