T32: Integrated Register read/write calls

* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/gem5/Gem5ArmCPU.hpp

@@ -10,7 +10,7 @@ namespace fail {
 
 /**
  * \class Gem5ArmCPU
- * 
+ *
  * \c Gem5ArmCPU is the concrete CPU implementation for the gem5 ARM simulator. It
  * implements the CPU interfaces \c ArmArchitecture and \c ArmCPUState.
  * \c ArmArchitecture refers to architectural information (e.g. register \a count)

src/core/sal/gem5/Gem5Controller.hpp

@@ -10,7 +10,7 @@ namespace fail {
 
 /**
  * \class Gem5Controller
- * 
+ *
  * Gem5-specific implementation of a SimulatorController.
  */
 class Gem5Controller : public SimulatorController {

src/core/sal/gem5/Gem5Memory.hpp

@@ -19,7 +19,7 @@ namespace fail {
 class Gem5MemoryManager : public MemoryManager {
 public:
 	Gem5MemoryManager(System* system) : m_System(system), m_Mem(&system->getPhysMem()) { }
-	
+
 	size_t getPoolSize() const { return m_Mem->totalSize(); }
 	host_address_t getStartAddr() const { return 0; }