coding style++, some TODOs added.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1967 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/CPU.hpp

@@ -1,5 +1,5 @@
 #ifndef __CPU_HPP__
-	#define __CPU_HPP__
+  #define __CPU_HPP__
 
 #include <cstring>
 #include <vector>
@@ -17,8 +17,7 @@ namespace fail {
  * directly derived from this are especially meant to be usable in campaigns, so they shouldn't
  * contain any backend specific code.
  */
-class CPUArchitecture
+class CPUArchitecture {
-{
 public:
 	/**
 	 * Retrieves the total number of registers over all homogeneous sets.
@@ -54,14 +53,12 @@ public:
 	 * Returns the set with register type \a t. The set can be used to
 	 * loop over all registers of type \a t.
 	 * @param t the type to check for
-	 * @return a pointer to the retrieved register set (if found), NULL
+	 * @return a pointer to the retrieved register set (if found), \c NULL otherwise
-	 *         otherwise
 	 */
 	UniformRegisterSet* getRegisterSetOfType(RegisterType t) const;
-
 protected:
-	std::vector< Register* > m_Registers;
+	std::vector<Register*> m_Registers;
-	std::vector< UniformRegisterSet* > m_RegisterSubsets;
+	std::vector<UniformRegisterSet*> m_RegisterSubsets;
 };
 
 } // end-of-namespace: fail

src/core/sal/CPUState.hpp

@@ -1,5 +1,5 @@
 #ifndef __CPU_STATE_HPP__
-	#define __CPU_STATE_HPP__
+  #define __CPU_STATE_HPP__
 
 #include <cstring>
 #include <vector>
@@ -11,11 +11,10 @@ namespace fail {
 /**
  * \class CPUArchitecture
  * This is the base class for the CPU state without any architecture specific additions. It contains
- * pure virtual functions for e.g. register acces and have to be overridden in the backend
+ * pure virtual functions for e.g. register access and have to be overridden in the backend
  * implementation.
  */
-class CPUState
+class CPUState {
-{
 public:
 	/**
 	 * Gets the content of the passed Register.
@@ -57,7 +56,6 @@ public:
 	 * @return \c true if sucessfully removed, \c false otherwise (not found)
 	 */
 	bool removeSuppressedInterrupt(unsigned interruptNum);
-
 protected:
 	std::vector<unsigned> m_SuppressedInterrupts;
 };
@@ -67,4 +65,4 @@ extern int interrupt_to_fire;
 
 } // end-of-namespace: fail
 
-#endif
+#endif // __CPU_STATE_HPP__

src/core/sal/ConcreteCPU.hpp

@@ -1,5 +1,5 @@
 #ifndef __CONCRETE_CPU_HPP__
-	#define __CONCRETE_CPU_HPP__
+  #define __CONCRETE_CPU_HPP__
 
 #if defined BUILD_BOCHS
   #include "bochs/BochsCPU.hpp"

src/core/sal/arm/arch.cc

@@ -12,8 +12,7 @@ void ArmArchitecture::fillRegisterList()
 {
 	// TODO: Add missing registers
 	// 16x 32-Bit GP Registers
-	for (int i=0; i<16; i++)
+	for (int i = 0; i < 16; i++) {
-	{
 		Register *reg = new Register(i, RT_GP, 32);
 		addRegister(reg);
 	}
@@ -22,8 +21,7 @@ void ArmArchitecture::fillRegisterList()
 ArmArchitecture::~ArmArchitecture()
 {
 	std::vector< Register* >::iterator it = m_Registers.begin();
-	while(it != m_Registers.end())
+	while (it != m_Registers.end()) {
-	{
 		delete *it;
 		it = m_Registers.erase(it);
 	}

src/core/sal/arm/arch.hpp

@@ -1,5 +1,5 @@
 #ifndef __ARM_ARCH_HPP__
-	#define __ARM_ARCH_HPP__
+  #define __ARM_ARCH_HPP__
 
 #include "../CPU.hpp"
 #include "../CPUState.hpp"
@@ -7,21 +7,18 @@
 namespace fail {
 /**
  * \class ArmArchitecture
- * This class adds ARM specific functionality to the base architecture. This can be used for every
+ * This class adds ARM specific functionality to the base architecture.
- * simulator backend that runs on ARM.
+ * This can be used for every simulator backend that runs on ARM.
  */
-class ArmArchitecture : public CPUArchitecture
+class ArmArchitecture : public CPUArchitecture {
-{
 public:
 	ArmArchitecture();
 	~ArmArchitecture();
-
 private:
 	void fillRegisterList();
 };
 
-class ArmCPUState : public CPUState
+class ArmCPUState : public CPUState {
-{
 public:
 	virtual regdata_t getRegisterContent(Register* reg) = 0;
 
@@ -34,8 +31,7 @@ public:
 	virtual address_t getLinkRegister() = 0;
 };
 
-enum GPRegIndex
+enum GPRegIndex {
-{
 	RI_R0,
 	RI_R1,
 	RI_R2,

src/core/sal/gem5/Gem5ArmCPU.cc

@@ -19,6 +19,7 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
 	}
 
 	// This shouldn't be reached if a valid register is passed
+	// TODO: assertion?
 	return 0;
 }
 
@@ -39,6 +40,7 @@ void Gem5ArmCPU::setRegisterContent(Register* reg, regdata_t value)
 	case RT_IP:
 		return setRegisterContent(getRegister(RI_IP), value);
 	}
+	// TODO: assertion?
 }
 
 address_t Gem5ArmCPU::getInstructionPointer()

src/core/sal/gem5/Gem5ArmCPU.hpp

@@ -1,5 +1,5 @@
 #ifndef __GEM5_ARM_CPU_HPP__
-	#define __GEM5_ARM_CPU_HPP__
+  #define __GEM5_ARM_CPU_HPP__
 
 #include "../arm/arch.hpp"
 
@@ -7,9 +7,9 @@
 
 namespace fail {
 
-class Gem5ArmCPU : public ArmArchitecture, public ArmCPUState
+class Gem5ArmCPU : public ArmArchitecture, public ArmCPUState {
-{
 public:
+	// TODO: comments
 	Gem5ArmCPU(unsigned int id, System* system) : m_Id(id), m_System(system) {}
 	regdata_t getRegisterContent(Register* reg);
 	void setRegisterContent(Register* reg, regdata_t value);