From 33c0584dda89300b43caa78bb233c10bce9aff90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Adrian=20B=C3=B6ckenkamp?= Date: Wed, 24 Apr 2013 13:06:44 +0200 Subject: [PATCH] gem5: revisited breakpoint implementation Now, the gem5 implementation equals the Bochs variant. Note that it's *not* necessary to enable CONFIG_EVENTS_BREAKPOINTS_RANGE in order to use range breakpoints. In addition, gem5 distinguishes between macro- and microops. With the new implementation, onBreakpoint() is only called when a macroop changes. Change-Id: Ib86d1802fc70c20d22ca1a1ece0e8d1221b2e7db --- simulators/gem5/src/cpu/simple/base.cc | 14 +++++++------ src/core/sal/gem5/Gem5Breakpoint.hpp | 18 ---------------- src/core/sal/gem5/Gem5Listener.ah | 29 -------------------------- src/core/sal/gem5/Gem5Wrapper.cc | 22 ------------------- src/core/sal/gem5/Gem5Wrapper.hpp | 6 ------ 5 files changed, 8 insertions(+), 81 deletions(-) delete mode 100644 src/core/sal/gem5/Gem5Breakpoint.hpp delete mode 100644 src/core/sal/gem5/Gem5Listener.ah diff --git a/simulators/gem5/src/cpu/simple/base.cc b/simulators/gem5/src/cpu/simple/base.cc index 1eb98e0d..2b8e16ee 100644 --- a/simulators/gem5/src/cpu/simple/base.cc +++ b/simulators/gem5/src/cpu/simple/base.cc @@ -377,12 +377,6 @@ BaseSimpleCPU::preExecute() TheISA::PCState pcState = thread->pcState(); - // FAIL* - #if defined(CONFIG_EVENT_BREAKPOINTS) && defined(CONFIG_EVENT_BREAKPOINTS_RANGE) - fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); - fail::simulator.onBreakpoint(cpu, instAddr(), -1); - #endif - if (isRomMicroPC(pcState.microPC())) { stayAtPC = false; curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), @@ -406,6 +400,14 @@ BaseSimpleCPU::preExecute() //Decode an instruction if one is ready. Otherwise, we'll have to //fetch beyond the MachInst at the current pc. instPtr = decoder->decode(pcState); + + // FAIL* + #if defined(CONFIG_EVENT_BREAKPOINTS) || defined(CONFIG_EVENT_BREAKPOINTS_RANGE) + fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId()); + fail::simulator.setMnemonic(instPtr->getName()); + fail::simulator.onBreakpoint(cpu, instAddr(), -1); + #endif + if (instPtr) { stayAtPC = false; thread->pcState(pcState); diff --git a/src/core/sal/gem5/Gem5Breakpoint.hpp b/src/core/sal/gem5/Gem5Breakpoint.hpp deleted file mode 100644 index 93da9e2f..00000000 --- a/src/core/sal/gem5/Gem5Breakpoint.hpp +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __GEM5_BREAKPOINT_HPP__ - #define __GEM5_BREAKPOINT_HPP__ - -#include "../SALConfig.hpp" -#include "cpu/pc_event.hh" - -namespace fail { - -class Gem5Breakpoint : public PCEvent { -public: - Gem5Breakpoint(PCEventQueue* queue, Addr ip) - : PCEvent(queue, "Fail* experiment breakpoint", ip) { } - virtual void process(ThreadContext *tc); -}; - -} // end-of-namespace: fail - -#endif // __GEM5_BREAKPOINT_HPP__ diff --git a/src/core/sal/gem5/Gem5Listener.ah b/src/core/sal/gem5/Gem5Listener.ah deleted file mode 100644 index e69a0d74..00000000 --- a/src/core/sal/gem5/Gem5Listener.ah +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef __GEM5_LISTENER_AH__ - #define __GEM5_LISTENER_AH__ - -#include "config/FailConfig.hpp" -#include "config/VariantConfig.hpp" - -#if defined(BUILD_GEM5) && defined(CONFIG_EVENT_BREAKPOINTS) && !defined(CONFIG_EVENT_BREAKPOINTS_RANGE) - -aspect Gem5Listener { - advice "fail::BPSingleListener" : slice class { - private: - Gem5Breakpoint* m_Breakpoint; - public: - virtual bool onAddition() - { - m_Breakpoint = OnBreakpointAddition(Gem5Breakpoint* bp, address_t watchInstrPtr) - return true; - } - virtual void onDeletion() - { - OnBreakpointDeletion(m_Breakpoint); - m_Breakpoint = 0; - } - }; -}; - -#endif // defined(BUILD_GEM5) && defined(CONFIG_EVENT_BREAKPOINTS) && !defined(CONFIG_EVENT_BREAKPOINTS_RANGE) - -#endif // __GEM5_LISTENER_AH__ diff --git a/src/core/sal/gem5/Gem5Wrapper.cc b/src/core/sal/gem5/Gem5Wrapper.cc index f0848531..65a8aaaf 100644 --- a/src/core/sal/gem5/Gem5Wrapper.cc +++ b/src/core/sal/gem5/Gem5Wrapper.cc @@ -1,6 +1,5 @@ #include "../SALInst.hpp" #include "Gem5Wrapper.hpp" -#include "Gem5Breakpoint.hpp" #include "sim/system.hh" #include "mem/packet.hh" @@ -61,27 +60,6 @@ void WriteMemory(System* sys, guest_address_t addr, size_t cnt, void const *src) size_t GetPoolSize(System* sys) { return sys->getPhysMem().totalSize(); } -// Breakpoint-related: -void Gem5Breakpoint::process(ThreadContext *tc) -{ - fail::simulator.onBreakpoint(&fail::simulator.getCPU(tc->cpuId()), this->evpc, fail::ANY_ADDR); -} - -Gem5Breakpoint* OnBreakpointAddition(address_t watchInstrPtr) -{ - System* sys = *System::systemList.begin(); - // FIXME: begin() vs. front() (see Gem5Controller::startup()) - // FIXME: Provide "sys" using the simulator-inst? - return new Gem5Breakpoint(&sys->pcEventQueue, watchInstrPtr); -} - -void OnBreakpointDeletion(Gem5Breakpoint* bp) -{ - if (bp) { - delete bp; // TODO: required? - } -} - // Controller-related: unsigned int GetCPUId(System* sys, int context) { diff --git a/src/core/sal/gem5/Gem5Wrapper.hpp b/src/core/sal/gem5/Gem5Wrapper.hpp index 141a87b6..c5ecfd21 100644 --- a/src/core/sal/gem5/Gem5Wrapper.hpp +++ b/src/core/sal/gem5/Gem5Wrapper.hpp @@ -9,8 +9,6 @@ class System; namespace fail { -class Gem5Breakpoint; - // Register-/Memory-related: regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx); void SetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx, @@ -19,10 +17,6 @@ void WriteMemory(System* sys, guest_address_t addr, size_t cnt, void const *src) void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest); size_t GetPoolSize(System* sys); -// Breakpoint-related: -Gem5Breakpoint* OnBreakpointAddition(address_t watchInstrPtr); -void OnBreakpointDeletion(Gem5Breakpoint* bp); - // Controller-related: unsigned int GetCPUId(System* sys, int context); System* GetSystemObject();