Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/ovp/test1/CMakeLists.txt

@@ -0,0 +1,13 @@
+add_definitions(" -m32 ${IMPERAS_VMIINC} ")
+
+set(SRCS
+	$ENV{IMPERAS_HOME}/ImpPublic/source/host/icm/icmCpuManager.cpp
+	platform/flakyMemory.cpp
+	platform/beforeInstruction.cpp
+	platform/platform.cpp
+)
+add_executable(ovp ${SRCS})
+add_dependencies(ovp msg)
+target_link_libraries(ovp ${SIM_LDFLAGS} )
+## OVP links all needed shared libraries via a runtimeloader
+set_target_properties(ovp PROPERTIES LINK_FLAGS " -m32 ")

simulators/ovp/test1/application/application.c

@@ -0,0 +1,20 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+int foo = 0x37;
+int bar = 34;
+
+int main() {
+    long i;
+    printf("\nHello\n\n");
+    
+    for (i=0; i<50000; i++) {
+        printf("%d\n", i);
+        foo = 0x37;
+        printf("foo: (0x%x) = 0x%x\n", &foo, foo);
+        bar = 34;
+        printf("bar: (0x%x) = %d\n\n", &bar, bar);
+    }
+    
+    return 0;
+}

simulators/ovp/test1/platform/beforeInstruction.cpp

@@ -0,0 +1,91 @@
+#include "beforeInstruction.hpp"
+
+Uns8 bpCount;
+Addr breakpoints[255];
+
+//Ignore warning: deprecated conversion from string constant to ‘char*’
+#pragma GCC diagnostic ignored "-Wwrite-strings"
+
+void printArmCortexM3Registers(icmProcessorObject processor) {
+    Uns32 registers[17];
+    icmPrintf("---------------\t\t---------------\n");
+    readRegister(processor, "R0",   registers[0]);
+    readRegister(processor, "R1",   registers[1]);
+    readRegister(processor, "R2",   registers[2]);
+    readRegister(processor, "R3",   registers[3]);
+    readRegister(processor, "R4",   registers[4]);
+    readRegister(processor, "R5",   registers[5]);
+    readRegister(processor, "R6",   registers[6]);
+    readRegister(processor, "R7",   registers[7]);
+    readRegister(processor, "R8",   registers[8]);
+    readRegister(processor, "R9",   registers[9]);
+    readRegister(processor, "R10",  registers[10]);
+    readRegister(processor, "R11",  registers[11]);
+    readRegister(processor, "R12",  registers[12]);
+    readRegister(processor, "SP",   registers[13]);
+    readRegister(processor, "LR",   registers[14]);
+    readRegister(processor, "PC",   registers[15]);
+    readRegister(processor, "CPSR", registers[16]);
+    icmPrintf("R0:  0x%08x\t\t",    registers[0]);
+    icmPrintf("R1:  0x%08x\n",      registers[1]);
+    icmPrintf("R2:  0x%08x\t\t",    registers[2]);
+    icmPrintf("R3:  0x%08x\n",      registers[3]);
+    icmPrintf("R4:  0x%08x\t\t",    registers[4]);
+    icmPrintf("R5:  0x%08x\n",      registers[5]);
+    icmPrintf("R6:  0x%08x\t\t",    registers[6]);
+    icmPrintf("R7:  0x%08x\n",      registers[7]);
+    icmPrintf("R8:  0x%08x\t\t",    registers[8]);
+    icmPrintf("R9:  0x%08x\n",      registers[9]);
+    icmPrintf("R10: 0x%08x\t\t",    registers[10]);
+    icmPrintf("R11: 0x%08x\n",      registers[11]);
+    icmPrintf("R12: 0x%08x\n\n",    registers[12]);
+    icmPrintf("SP:  0x%08x\t\t",    registers[13]);
+    icmPrintf("LR:  0x%08x\n",      registers[14]);
+    icmPrintf("PC:  0x%08x\n",      registers[15]);
+    icmPrintf("PSR: 0x%08x\n\n",    registers[16]);
+}
+
+Bool readRegister(icmProcessorObject processor, char *regName, Uns32 &value) {
+    if (regName[0] == 'P' && regName[1] == 'C') {
+        value = (Uns32)processor.getPC();
+        return True;
+    } else {
+        return processor.readReg(regName, &value);
+    }
+}
+
+Bool writeRegister(icmProcessorObject processor, char *regName, Uns32 &newValue) {
+    if (regName[0] == 'P' && regName[1] == 'C') {
+        processor.setPC((Addr)newValue);
+        return True;
+    } else {
+        return processor.writeReg(regName, &newValue);
+    }
+}
+
+
+void addBreakpoint(Addr breakAddr) {
+    if (breakAddr != 0x00 && bpCount != 255) {
+        breakpoints[bpCount] = breakAddr;
+        bpCount++;
+    }
+}
+
+Addr simulateUntilBP(icmProcessorObject processor) {
+    if (bpCount == 0) {
+        icmPlatform::Instance()->simulate();
+        return 0x00;
+    }
+    
+    Addr currentPC = 0x00;
+    while (processor.simulate(1) == ICM_SR_SCHED) {
+        currentPC = processor.getPC();
+        for (Uns8 u = 0; u < bpCount; u++) {
+            if (currentPC == breakpoints[u]) {
+                return currentPC;
+            }
+        }
+    }
+    
+    return 0x00;
+}

simulators/ovp/test1/platform/beforeInstruction.hpp

@@ -0,0 +1,46 @@
+#ifndef BEFORE_INSTRUCTION_HPP
+#define BEFORE_INSTRUCTION_HPP
+
+#include "icm/icmCpuManager.hpp"
+
+using namespace icmCpuManager;
+
+/**
+ * Prints all the registers for an ARM Cortex M3 processor.
+ * @param processor The processor (must be an ARM Cortex M3)
+ */
+void printArmCortexM3Registers(icmProcessorObject processor);
+
+/**
+ * Reads a register and stores its content in an Uns32 variable.
+ * @param processor The processor for which to read the register
+ * @param regName The name of the register as a string
+ * @param value The address of where to store the register's content
+ */
+Bool readRegister(icmProcessorObject processor, char *regName, Uns32 &value);
+
+/**
+ * Writes the value given as an Uns32 variable to a register.
+ * @param processor The processor for which to write the variable
+ * @param regName The name of the register as a string
+ * @param newValue The address of the new value to be written to the register
+ */
+Bool writeRegister(icmProcessorObject processor, char *regName, Uns32 &newValue);
+
+
+/**
+ * Adds a breakpoint for simulateUntilBreakpoint
+ * @param breakAddr The address to be added as a breakpoint
+ */
+void addBreakpoint(Addr breakAddr);
+
+/**
+ * Simulates until breakpoint,
+ * or the entire application file at once if no breakpoint was added.
+ * Returns the address of the next instruction,
+ * or zero if simulation did not stop at a breakpoint.
+ * @param processor The processor to run the simulation on
+ */
+Addr simulateUntilBP(icmProcessorObject processor);
+
+#endif

simulators/ovp/test1/platform/flakyMemory.cpp

@@ -0,0 +1,66 @@
+#include "flakyMemory.hpp"
+
+
+void createFlakyMem(
+    icmProcessorObject processor,
+    Addr lowAddr,
+    Addr highAddr,
+    const char *vlnvRoot
+) {
+    
+    icmBusObject *mainBus;
+    icmBusObject *interBus;
+    icmBusObject *mmcBus;
+    icmMmcObject *mmc1;
+    icmMemoryObject *memory1;
+    icmMemoryObject *memory2;
+    icmMemoryObject *memory3;
+    
+#if 0
+    // get location of mmc object file:
+    const char *flakyMem = icmGetVlnvString(
+        vlnvRoot,
+        "ovpworld.org",
+        "mmc",
+        "flakyMemory",
+        "1.0",
+        "model"
+    );
+#endif 
+    // create full MMC
+    mmc1 = new icmMmcObject("mmc1", "/srv/scratch/sirozipp/build/lib/libflaky.so", "modelAttrs", 0, False);
+    
+    // create the processor bus
+    mainBus = new icmBusObject("bus1", 32);
+    
+    // create the intermediate bus
+    interBus = new icmBusObject("bus2", 32);
+    
+    // create the bus connecting the mmc to the memory
+    mmcBus = new icmBusObject("bus3", 32);
+    
+    // connect mmc direct to processor ports
+    processor.connect(*mainBus, *mainBus);
+    
+    // connect master port of MMC to bus
+    mmc1->connect(*interBus, "sp1", False);
+    mmc1->connect(*mmcBus, "mp1", True);
+    
+    if (lowAddr != 0x00) {
+        memory1 = new icmMemoryObject("mem1", ICM_PRIV_RWX, lowAddr-1);
+        memory1->connect("memp1", *mainBus, 0x00);
+    }
+    memory2 = new icmMemoryObject("mem2", ICM_PRIV_RWX, highAddr-lowAddr);
+    memory2->connect("memp2", *mmcBus, lowAddr);
+    if (highAddr != 0xffffffff) {
+        memory3 = new icmMemoryObject("mem3", ICM_PRIV_RWX, 0xffffffff-(highAddr+1));
+        memory3->connect("memp3", *mainBus, highAddr+1);
+    }
+    
+    mainBus->newBridge(*interBus, "br1", "sp2", "mp2", lowAddr, highAddr, lowAddr);
+    
+    // show the bus connections
+    mainBus->printConnections();
+    interBus->printConnections();
+    mmcBus->printConnections();
+}

simulators/ovp/test1/platform/flakyMemory.hpp

@@ -0,0 +1,21 @@
+#ifndef FLAKY_MEMORY_HPP
+#define FLAKY_MEMORY_HPP
+
+#include "icm/icmCpuManager.hpp"
+
+using namespace icmCpuManager;
+
+/** Creates flaky memory by attaching an MMC for the specified address range.
+ * @param processor The processor on which to set up the MMC
+ * @param loAddr The lowest address for which to do on-the-fly manipulation.
+ * @param hiAddr The highest address for which to do manipulation.
+ */
+void createFlakyMem(
+    icmProcessorObject processor,
+    Addr loAddr,
+    Addr hiAddr,
+    const char *vlnvRoot = 0
+);
+
+
+#endif

simulators/ovp/test1/platform/platform.cpp

@@ -0,0 +1,90 @@
+#include <cstdlib>
+
+#include "icm/icmCpuManager.hpp"
+#include "flakyMemory.hpp"
+#include "beforeInstruction.hpp"
+
+// enable relaxed scheduling for maximum performance
+#define SIM_ATTRS (ICM_ATTR_RELAXED_SCHED)
+
+
+icmProcessorObject createPlatform(
+    const char *application,
+    bool gdb,
+    bool flaky=false,
+    Addr lowAddr=0x00,
+    Addr highAddr=0xffffffff
+) {
+    // select library components
+    const char *vlnvRoot = 0; // when null use default library
+    const char *vlnvRoot2 ="/srv/scratch/sirozipp/build/lib/" ; 
+    const char *model = icmGetVlnvString(vlnvRoot,
+                                         "arm.ovpworld.org",
+                                         "processor",
+                                         "armm",
+                                         "1.0",
+                                         "model");
+    const char *semihosting = icmGetVlnvString(vlnvRoot, "arm.ovpworld.org", "semihosting", "armNewlib", "1.0", "model");
+    
+    // set attributes for CPU model
+    icmAttrListObject icmAttr;
+    icmAttr.addAttr("endian",        "little");
+    icmAttr.addAttr("compatibility", "nopBKPT");
+    icmAttr.addAttr("variant",       "Cortex-M3");
+    icmAttr.addAttr("UAL",           "1");
+    
+    icmProcessorObject processor(
+        "cpu-Cortex-M3",             // CPU name
+        "armm",             // CPU type
+        0,                  // CPU cpuId
+        0,                  // CPU model flags
+        32,                 // address bits
+        model,              // model file
+        "modelAttrs",       // morpher attributes
+        gdb?ICM_ATTR_DEFAULT:SIM_ATTRS,   // simulation attributes
+        &icmAttr,                  // user-defined attributes
+        semihosting,        // semi-hosting file
+        "modelAttrs"        // semi-hosting attributes
+    );
+    
+//    if (flaky) {
+        createFlakyMem(processor, lowAddr, highAddr, vlnvRoot2);
+ //   }
+    
+    if (gdb) {
+        processor.debugThisProcessor();
+    }
+    
+    // load the processor object file
+    processor.loadLocalMemory(application, true, true, true);
+    
+    return processor;
+}
+
+
+// Main simulation routine
+int main(int argc, char ** argv) {
+    const char *application = "application.elf";
+    bool gdb = false;
+    Uns32 portNum = (Uns32)-1;
+    
+    if(argc >= 2) {
+        application = argv[1];
+        if(argc >= 3) {
+            gdb = true;
+            portNum = (Uns32)atoi(argv[2]);
+        }
+    }
+    
+    icmPlatform platform(
+        "fiPlatformCpp",
+        ICM_VERBOSE | ICM_STOP_ON_CTRLC,
+        gdb ? "rsp" : 0,
+        gdb ? portNum : 0
+    );
+    icmProcessorObject processor = createPlatform(application, gdb);
+    
+    simulateUntilBP(processor);
+    
+    return 0;
+}