Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
15
simulators/ovp/cortexM3/CMakeLists.txt
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15
simulators/ovp/cortexM3/CMakeLists.txt
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@ -0,0 +1,15 @@
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add_definitions(" -m32 ${IMPERAS_VMIINC} ")
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set(SRCS
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$ENV{IMPERAS_HOME}/ImpPublic/source/host/icm/icmCpuManager.cpp
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platform/platform.cc
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../OVPPlatform.cc
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)
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add_executable(ovp_cortexM3 ${SRCS})
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add_dependencies(ovp_cortexM3 ovpstatusmessages )
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target_link_libraries(ovp_cortexM3 ${SIM_LDFLAGS} sal cpn comm efw util ovpstatusmessages)
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## OVP links all needed shared libraries via a runtimeloader
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set_target_properties(ovp_cortexM3 PROPERTIES LINK_FLAGS "-L${CMAKE_BINARY_DIR}/lib -lpcl -lprotobuf -m32 ")
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415
simulators/ovp/cortexM3/platform/platform.cc
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415
simulators/ovp/cortexM3/platform/platform.cc
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@ -0,0 +1,415 @@
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/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <iostream>
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#include "platform.hpp"
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#include "statreg.hpp"
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#include "sal/SALInst.hpp"
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#include "icm/icmCpuManager.h"
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#include "icm/icmQuery.h"
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// enable relaxed scheduling for maximum performance
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//#define SIM_ATTRS (ICM_ATTR_RELAXED_SCHED|ICM_ATTR_TRACE)
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#define SIM_ATTRS (ICM_ATTR_RELAXED_SCHED)
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// GDB port
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#define GDB_PORT 1234
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// Variables set by arguments
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const char *variant = "Cortex-M3"; // the model variant
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using namespace std;
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ARM_Cortex_M3 arm;
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ARM_Cortex_M3::ARM_Cortex_M3() {
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}
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ARM_Cortex_M3::~ARM_Cortex_M3() {
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delete platform;
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delete cpu;
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delete attrList;
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}
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void ARM_Cortex_M3::init(bool gdb=false) {
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// initialize OVPsim, enabling verbose mode to get statistics at end of execution
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platform = new icmPlatform("CortexM3Platform", //name
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ICM_VERBOSE|ICM_STOP_ON_CTRLC, //attributes
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gdb ? "rsp" : 0, // optional protocol
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gdb ? GDB_PORT : 0); // optional port number
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// const char *armModel = icmGetVlnvString(NULL, "arm.ovpworld.org", "processor", "armm", "1.0", "model");
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const char *armModel = "/srv/scratch/hoffmann/test/build/lib/libarmmModel.so";
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const char *armSemihost = icmGetVlnvString(NULL, "arm.ovpworld.org", "semihosting", "armNewlib", "1.0", "model");
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attrList = new icmAttrListObject();
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attrList->addAttr("endian", "little");
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attrList->addAttr("compatibility", "nopBKPT");
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attrList->addAttr("variant", variant);
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attrList->addAttr("UAL", "1");
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attrList->addAttr("fail_salp", &fail::simulator);
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char cpuname[64];
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sprintf(cpuname,"cpu-%s", variant);
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// create a processor instance
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cpu = new icmProcessorObject(
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cpuname, // CPU name
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"armm", // CPU type
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0, // CPU cpuId
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0, // CPU model flags
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32, // address bits
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armModel, // model file
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"modelAttrs", // morpher attributes
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SIM_ATTRS, // attributes
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attrList, // user-defined attributes
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armSemihost, // semi-hosting file
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"modelAttrs" // semi-hosting attributes
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);
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// Nominate this processor to be attached to a debugger
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if(gdb) cpu->debugThisProcessor();
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processorP = cpu->getProcessorP();
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}
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void ARM_Cortex_M3::createFullMMC(const char *vlnRoot=0) {
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// TODO: ELF Groesse auslesen per OVP (hat funktionen) und dann den Bereich als MMC einrichten...
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/* const char *mmc_model = icmGetVlnvString("/srv/scratch/sirozipp/build/lib", "ovpworld.org", "mmc", "failMMC", "1.0", "model");
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if(mmc_model == NULL) {
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std::cerr << "mmc_model not found!" << std::endl;
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exit(1);
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}
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*/
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const char *mmc_model = "/srv/scratch/sirozipp/build/lib/libflaky.so";
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// create full MMCs
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mmcInstr = new icmMmcObject("mmci", mmc_model, "modelAttrs", 0, False);
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mmcData = new icmMmcObject("mmcd", mmc_model, "modelAttrs", 0, False);
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// create processor instruction and data bus
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instrBus = new icmBusObject("instrbus", 32);
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dataBus = new icmBusObject("databus", 32);
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// create processor main bus
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mainBus = new icmBusObject("mainbus", 32);
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// connect processor ports to their buses
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cpu->connect(*instrBus, *dataBus);
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// connect mmcs to buses
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mmcInstr->connect(*instrBus, "sp1", False);
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mmcData->connect(*dataBus, "sp1", False);
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// connet master ports of mmc to main bus
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mmcInstr->connect(*mainBus, "mp1", True);
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mmcData->connect(*mainBus, "mp1", True);
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// create simulated memory
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Addr appHighAddr, appLowAddr;
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appHighAddr = 0xFFFFFFFF;
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appLowAddr = 0x0;
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icmMem0 = new icmMemoryObject("mem1", ICM_PRIV_RWX, appHighAddr-appLowAddr);
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// connect memory to main bus
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icmMem0->connect("mp1", *mainBus, 0);
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}
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static ICM_MEM_READ_FN(extMemRead) {
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unsigned char res[4];
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// Int32 tmpres = *(Int32*)value;
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// icmPrintf("EXTERNAL MEMORY: Reading 0x%08x from 0x%08x\n", *(Int32*)value, (Int32)address);
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// *(Int32*) value = (Int32)arm.mem[(address-arm.offset)>>2];
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fail::simulator.onMemoryAccessEvent(address, 4, false, ovpplatform.getPC());
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res[0] = arm.mem[(address-arm.offset)+0];
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res[1] = arm.mem[(address-arm.offset)+1];
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res[2] = arm.mem[(address-arm.offset)+2];
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res[3] = arm.mem[(address-arm.offset)+3];
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// icmPrintf("Reading [0] 0x%08x, [1] 0x%08x, [2] 0x%08x, [3] 0x%08x\n", arm.mem[(address-arm.offset)+0], arm.mem[(address-arm.offset)+1], arm.mem[(address-arm.offset)+2], arm.mem[(address-arm.offset)+3]);
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*(Int32*)value = (res[3] << 24) | (res[2] << 16) | (res[1] << 8) | res[0];
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//
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// icmPrintf("Reading: 0x%08x\n", (res[3] << 24) | (res[2] << 16) | (res[1] << 8) | res[0]);
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// icmPrintf("Callback: Reading 0x%08x from mem[0x%08x] should be 0x%08x from [0x%08x]\n", *(Int32*)value, (Int32)(address-arm.offset), tmpres, (Int32) address);
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}
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static ICM_MEM_WRITE_FN(extMemWrite) {
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// icmPrintf("EXTERNAL MEMORY: Writing 0x%08x to 0x%08x\n", (Int32)value, (Int32)address);
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// icmPrintf("Callback: Writing 0x%08x to mem[0x%08x] should be 0x%08x from [0x%08x]\n", *(Int32*)value, (Int32)(address-arm.offset), *(Int32*) value, (Int32) address);
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fail::simulator.onMemoryAccessEvent(address, 4, true, ovpplatform.getPC());
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Int32 val = *(Int32*)value;
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arm.mem[(address-arm.offset) + 0] = val & 0xFF;
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arm.mem[(address-arm.offset) + 1] = (val >> 8) & 0xFF;
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arm.mem[(address-arm.offset) + 2] = (val >> 16) & 0xFF;
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arm.mem[(address-arm.offset) + 3] = (val >> 24) & 0xFF;
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// icmPrintf("Writing [0] 0x%08x, [1] 0x%08x, [2] 0x%08x, [3] 0x%08x\n", val & 0xFF, (val >> 8) & 0xFF, (val >> 16) & 0xFF, (val >> 24) & 0xFF);
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// icmPrintf("Writing [0] 0x%08x, [1] 0x%08x, [2] 0x%08x, [3] 0x%08x\n", arm.mem[(address-arm.offset)+0], arm.mem[(address-arm.offset)+1], arm.mem[(address-arm.offset)+2], arm.mem[(address-arm.offset)+3]);
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// Int32 res = arm.mem[(address-arm.offset)+0] | arm.mem[(address-arm.offset)+1] << 8 | arm.mem[(address-arm.offset)+2] << 16 | arm.mem[(address-arm.offset)+3] << 24;
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// icmPrintf("Callback: Writing 0x%08x to mem[0x%08x] should be 0x%08x to [0x%08x]\n", res, (Int32)(address-arm.offset), *(Int32*) value, (Int32) address);
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// arm.mem[(address-arm.offset) >> 2] = *(Int32*) value;
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}
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static ICM_MEM_READ_FN(extTextRead) {
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// Int16 val = *(Int16*)value;
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*(Int16*) value = (Int16)arm.textmem[(address-arm.textOffset)>>1];
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// icmPrintf("Callback: Reading 0x%04x from textmem[0x%08x] should be 0x%04x from [0x%08x]\n", *(Int16*)value, (Int32)(address-arm.textOffset), val, (Int32) address);
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}
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static ICM_MEM_WRITE_FN(extTextWrite) {
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arm.textmem[(address-arm.textOffset) >> 1] = *(Int16*) value;
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}
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void ARM_Cortex_M3::mapMemToCallback() {
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// create processor bus
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mainBus = new icmBusObject("mainbus", 32);
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// connect the processor bus
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cpu->connect(*mainBus, *mainBus);
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// create simulated memory
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Addr appHighAddr, appLowAddr, textLowAddr, textHighAddr, LowAddr, LowAddrH, HighAddr, HighAddrL;
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appLowAddr = offset;
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appHighAddr = appLowAddr + memSize - 1;
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textLowAddr = textOffset;
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textHighAddr = textLowAddr + textMemSize - 1;
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// check which section is first
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if(appLowAddr < textLowAddr) {
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LowAddr = appLowAddr;
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LowAddrH = appHighAddr;
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HighAddr = textHighAddr;
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HighAddrL = textLowAddr;
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} else {
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LowAddr = textLowAddr;
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LowAddrH = textHighAddr;
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HighAddr = appHighAddr;
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HighAddrL = appLowAddr;
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}
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// Memory from 0x0 to LowAddr
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icmMem0 = new icmMemoryObject("mem0", ICM_PRIV_RWX, LowAddr - 1);
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// Memory after callback mem to end
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icmMem1 = new icmMemoryObject("mem1", ICM_PRIV_RWX, 0xFFFFFFFF - HighAddr - 1);
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// Memory between text and other sections
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icmMem2 = new icmMemoryObject("mem2", ICM_PRIV_RWX, HighAddrL - LowAddrH - 1 -1);
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// map the adress range appLowAddr:appHighAddr externally to the processor
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mainBus->mapExternalMemory("external", ICM_PRIV_RWX, appLowAddr, appHighAddr,
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extMemRead, // read callback
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extMemWrite, // write callback
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0);
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mainBus->mapExternalMemory("exttext", ICM_PRIV_RWX, textLowAddr, textHighAddr,
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extTextRead,
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extTextWrite,
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0);
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// just build memory before external memory if it's not at the beginning
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if(LowAddr > 0x0) {
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icmMem0->connect("mp1", *mainBus, 0x0);
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}
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if(HighAddr < 0xffffffff) {
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icmMem1->connect("mp2", *mainBus, HighAddr+1);
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}
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if(LowAddrH != HighAddrL) {
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icmMem2->connect("mp3", *mainBus, LowAddrH+1);
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}
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mainBus->printConnections();
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}
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|
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void ARM_Cortex_M3::makeGPRegister() {
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const string names[] = {"r0", "r1", "r2", "r3", "r4", "r5",
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"r6", "r7", "r8", "r9", "r10", "r11", "r12"};
|
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for(int i = 0; i <= 12; ++i) {
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icmRegInfoP reg = icmGetRegByIndex(processorP, i);
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fail::simulator.makeGPRegister(32, (void *)reg, names[i]);
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}
|
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// set SP pointer
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||||
// ARM Cortex M3: SP pointer is ID 13
|
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icmRegInfoP sp_reg = icmGetRegByIndex(processorP, 13);
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setSPReg(sp_reg);
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}
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|
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void ARM_Cortex_M3::makeSTRegister() {
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OVPStatusRegister *streg = new CortexM3StatusRegister();
|
||||
|
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fail::simulator.makeSTRegister(streg, "sp");
|
||||
}
|
||||
|
||||
void ARM_Cortex_M3::makePCRegister() {
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// ARM Cortex M3: PC pointer is ID 15
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icmRegInfoP pc_reg = icmGetRegByIndex(processorP, 15);
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fail::simulator.makePCRegister(32, (void *)pc_reg, "PC");
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||||
}
|
||||
|
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int ARM_Cortex_M3::startSimulation(const char *app) {
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||||
bool loadPhysical = true;
|
||||
bool verbose = true;
|
||||
bool useEntry = true;
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||||
if(!cpu->loadLocalMemory(app, loadPhysical, verbose, useEntry))
|
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return -1;
|
||||
|
||||
// application is loaded, now fill the callback memory with program data
|
||||
fillCallbackMemory();
|
||||
|
||||
// icmSimulatePlatform();
|
||||
|
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while(1) {
|
||||
// save PC
|
||||
Addr pc_ptr = cpu->getPC();
|
||||
|
||||
fail::simulator.onInstrPtrChanged(pc_ptr);
|
||||
|
||||
// simulate the platform
|
||||
icmStopReason stopreason = cpu->simulate(1);
|
||||
|
||||
if(stopreason!=0x00) {
|
||||
// was simulation interrupted or did it complete
|
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if(stopreason==ICM_SR_INTERRUPT) {
|
||||
icmPrintf("*** simulation interrupted\n");
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
//icmTerminate();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ARM_Cortex_M3::makeCallbackMemory(size_t sizeText, size_t offText, size_t sizeMem, size_t offMem) {
|
||||
mem = new unsigned char[sizeMem];
|
||||
//mem = new Int32[sizeMem>>2];
|
||||
textmem = new Int16[sizeText>>1];
|
||||
offset = offMem;
|
||||
textOffset = offText;
|
||||
memSize = sizeMem;
|
||||
textMemSize = sizeText;
|
||||
}
|
||||
|
||||
void ARM_Cortex_M3::save(const string& path) {
|
||||
OVPStatusMessage ovpstat;
|
||||
|
||||
// save registers
|
||||
// FIXME: what about reg with id 16? should be status register
|
||||
for(unsigned int i = 0; i < 16; ++i) {
|
||||
uint32_t tmp = 0;
|
||||
icmRegInfoP reg = icmGetRegByIndex(processorP, i);
|
||||
icmReadRegInfoValue(processorP, reg, (void *)&tmp);
|
||||
OVPStatusMessage::Register *msgReg = ovpstat.add_reg();
|
||||
|
||||
switch(i) {
|
||||
case 13: msgReg->set_name("sp");
|
||||
break;
|
||||
case 14: msgReg->set_name("lr");
|
||||
break;
|
||||
case 15: msgReg->set_name("pc");
|
||||
break;
|
||||
case 16: msgReg->set_name("sr");
|
||||
break;
|
||||
default: char num[3];
|
||||
sprintf(num, "r%d", i);
|
||||
msgReg->set_name(num);
|
||||
}
|
||||
|
||||
msgReg->set_value(tmp);
|
||||
// std::cerr << "save " << i << ": " << tmp << std::endl;
|
||||
}
|
||||
|
||||
|
||||
string stmp;
|
||||
ovpstat.SerializeToString(&stmp);
|
||||
ofstream file;
|
||||
file.open(path.c_str(), ios::out);
|
||||
file << stmp;
|
||||
file.close();
|
||||
/* ofstream file(path.c_str(), ios::out | ios::trunc);
|
||||
if(!ovpstat.SerializeToOstream(&file)) {
|
||||
std::cerr << "Error writing to file " << path << "!" << std::endl;
|
||||
}*/
|
||||
}
|
||||
|
||||
void ARM_Cortex_M3::restore(const string& path) {
|
||||
fstream input(path.c_str(), ios::in);
|
||||
OVPStatusMessage ovpstat;
|
||||
ovpstat.ParseFromIstream(&input);
|
||||
|
||||
for(int i = 0; i < ovpstat.reg_size(); ++i) {
|
||||
const OVPStatusMessage::Register& ovpreg = ovpstat.reg(i);
|
||||
uint32_t val = ovpreg.value();
|
||||
// std::cerr << "restore "<<ovpreg.name()<<": " << val << std::endl;
|
||||
icmRegInfoP reg = icmGetRegByIndex(processorP, i);
|
||||
icmWriteRegInfoValue(processorP, reg, (void *)&val);
|
||||
}
|
||||
}
|
||||
|
||||
int main(int argc, char **argv) {
|
||||
if(argc != 2) {
|
||||
std::cerr << "Usage: " << argv[0] << " application" << std::endl;
|
||||
exit(1);
|
||||
}
|
||||
|
||||
arm.init(false);
|
||||
|
||||
// arm.createFullMMC();
|
||||
|
||||
// arm.makeCallbackMemory(0x100, 0x20000000);
|
||||
// arm.makeCallbackMemory(0x8034, 0x0, 0x11c, 0x82e8);
|
||||
// arm.makeCallbackMemory(0x8034, 0x0, 0x940, 0x8040);
|
||||
arm.makeCallbackMemory(0x802c, 0x0, 0x930, 0x8038);
|
||||
arm.mapMemToCallback();
|
||||
|
||||
|
||||
ovpplatform.setCpu((void *) &arm);
|
||||
|
||||
arm.makeGPRegister();
|
||||
arm.makeSTRegister();
|
||||
arm.makePCRegister();
|
||||
|
||||
arm.startSimulation(argv[1]);
|
||||
}
|
||||
36
simulators/ovp/cortexM3/platform/platform.hpp
Normal file
36
simulators/ovp/cortexM3/platform/platform.hpp
Normal file
@ -0,0 +1,36 @@
|
||||
#ifndef _armCortexM3_HPP_
|
||||
#define _armCortexM3_HPP_
|
||||
|
||||
|
||||
#include "../../OVPCpu.hpp"
|
||||
#include "ovp/statusmsg/OVPStatusMessage.pb.h"
|
||||
|
||||
using namespace icmCpuManager;
|
||||
|
||||
/**
|
||||
* \class ARM_Cortex_M3
|
||||
* Implements the OVP platform for ARM Cortex M3 with callback memory
|
||||
*/
|
||||
class ARM_Cortex_M3 : public OVPCpu {
|
||||
private:
|
||||
|
||||
public:
|
||||
ARM_Cortex_M3();
|
||||
~ARM_Cortex_M3();
|
||||
void init(bool);
|
||||
int startSimulation(const char*);
|
||||
void createFullMMC(const char *);
|
||||
void mapMemToCallback();
|
||||
|
||||
void makeGPRegister();
|
||||
void makeSTRegister();
|
||||
void makePCRegister();
|
||||
|
||||
void makeCallbackMemory(size_t, size_t, size_t, size_t);
|
||||
|
||||
void save(const string&);
|
||||
void restore(const string&);
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
92
simulators/ovp/cortexM3/platform/statreg.hpp
Normal file
92
simulators/ovp/cortexM3/platform/statreg.hpp
Normal file
@ -0,0 +1,92 @@
|
||||
#include "platform.hpp"
|
||||
#include "../../OVPStatusRegister.hpp"
|
||||
|
||||
extern ARM_Cortex_M3 arm;
|
||||
|
||||
/**
|
||||
* \class CortexM3StatusRegister
|
||||
* Status register for ARM Cortex M3
|
||||
*/
|
||||
class CortexM3StatusRegister : public OVPStatusRegister {
|
||||
|
||||
private:
|
||||
icmRegInfoP cpsr; //!< pointer to status register
|
||||
icmProcessorP cpuP;
|
||||
|
||||
public:
|
||||
CortexM3StatusRegister() : OVPStatusRegister(32, icmGetRegByIndex(arm.getProcessorP(), 16)) {
|
||||
cpuP = arm.getProcessorP();
|
||||
|
||||
// status register is index 16
|
||||
cpsr = icmGetRegByIndex(cpuP, 16);
|
||||
}
|
||||
|
||||
~CortexM3StatusRegister() {}
|
||||
|
||||
bool getFlag(int pos) const {
|
||||
uint32_t val;
|
||||
uint32_t bit;
|
||||
icmReadRegInfoValue(cpuP, cpsr, (void *)&val);
|
||||
|
||||
// put bit to correct place
|
||||
bit = 1 << pos;
|
||||
|
||||
// Flag at position pos
|
||||
val = val & bit;
|
||||
val = val >> pos;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
void setFlag(int pos, bool newval) {
|
||||
uint32_t val;
|
||||
uint32_t bit = 1 << pos;
|
||||
|
||||
icmReadRegInfoValue(cpuP, cpsr, (void *)&val);
|
||||
|
||||
if(newval == 0) {
|
||||
// AND with 0xFFFEFFFF (e.g.)
|
||||
bit = ~bit; // invert bits
|
||||
|
||||
val = val & bit;
|
||||
} else {
|
||||
// OR with 0x00010000 (e.g.)
|
||||
val = val | bit;
|
||||
}
|
||||
|
||||
icmWriteRegInfoValue(cpuP, cpsr, (void *)&val);
|
||||
}
|
||||
|
||||
bool getSignFlag() const {
|
||||
return getFlag(31);
|
||||
}
|
||||
|
||||
bool getZeroFlag() const {
|
||||
return getFlag(30);
|
||||
}
|
||||
|
||||
bool getCarryFlag() const {
|
||||
return getFlag(29);
|
||||
}
|
||||
|
||||
bool getOverflowFlag() const {
|
||||
return getFlag(28);
|
||||
}
|
||||
|
||||
void setSignFlag(bool b) {
|
||||
setFlag(31, b);
|
||||
}
|
||||
|
||||
void setZeroFlag(bool b) {
|
||||
setFlag(30, b);
|
||||
}
|
||||
|
||||
void setCarryFlag(bool b) {
|
||||
setFlag(29, b);
|
||||
}
|
||||
|
||||
void setOverflowFlag(bool b) {
|
||||
setFlag(28, b);
|
||||
}
|
||||
|
||||
};
|
||||
Reference in New Issue
Block a user