Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
509
simulators/ovp/armmModel/armmUtils.c
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509
simulators/ovp/armmModel/armmUtils.c
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@ -0,0 +1,509 @@
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/*
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||||
* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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||||
*
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||||
* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
|
||||
* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
|
||||
* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
|
||||
* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
|
||||
* PARTY PATENTS.
|
||||
*
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||||
* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
|
||||
* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
|
||||
* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
|
||||
* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
|
||||
* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
|
||||
* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
|
||||
* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
|
||||
* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
|
||||
*
|
||||
* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
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||||
* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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||||
*
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||||
* Unless required by applicable law or agreed to in writing, software
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||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
* either express or implied.
|
||||
*
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
*/
|
||||
|
||||
// VMI header files
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||||
#include "vmi/vmiCxt.h"
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||||
#include "vmi/vmiRt.h"
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#include "vmi/vmiMessage.h"
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||||
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// model header files
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#include "armDecode.h"
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||||
#include "armExceptions.h"
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||||
#include "armFunctions.h"
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#include "armStructure.h"
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#include "armSysRegisters.h"
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#include "armUtils.h"
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#include "armVM.h"
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//
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// Return the version of the instruction set implemented by the processor
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//
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inline static Uns32 getInstructionVersion(armP arm) {
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return ARM_INSTRUCTION_VERSION(arm->configInfo.arch);
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}
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//
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// Return endianness of the processor, public routine
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//
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VMI_ENDIAN_FN(armGetEndian) {
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armP arm = (armP)processor;
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if(isFetch) {
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return arm->instructionEndian;
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} else if(SCS_FIELD(arm, AIRCR, ENDIANNESS)) {
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return MEM_ENDIAN_BIG;
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} else {
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return MEM_ENDIAN_LITTLE;
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}
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}
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//
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// Set the initial endianness for the model
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//
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void armSetInitialEndian(armP arm, Bool isBigEndian) {
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SCS_FIELD(arm, AIRCR, ENDIANNESS) = isBigEndian;
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}
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//
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// Return the next instruction address after 'thisPC'.
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//
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VMI_NEXT_PC_FN(armNextInstruction) {
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return (Uns32)(thisPC + armGetInstructionSize((armP)processor, thisPC));
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}
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//
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// Return the name of a GPR
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//
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const char *armGetGPRName(armP arm, Uns32 index) {
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static const char *gprNames[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"
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};
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return gprNames[index];
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}
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//
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// Return the name of a CPR
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||||
//
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const char *armGetCPRName(armP arm, Uns32 index) {
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static const char *cprNames[] = {
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"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
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"cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
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||||
};
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return cprNames[index];
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}
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#define SWAP_REG(_R1, _R2) {Uns32 _V = _R1; _R1= _R2; _R2 = _V;}
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#define SWAP_GPR(_N, _SET) SWAP_REG(arm->regs[_N], arm->bank.R##_N##_##_SET)
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//
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// Switch banked registers on switch to the passed mode
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||||
//
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inline static void switchRegs(armP arm, Bool useSPProcess) {
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if(useSPProcess) {
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SWAP_GPR(13, process);
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}
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}
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//
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// Switch banked registers on switch between the passed modes
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//
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void armSwitchRegs(armP arm, Bool oldUseSPProcess, Bool newUseSPProcess) {
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switchRegs(arm, oldUseSPProcess);
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switchRegs(arm, newUseSPProcess);
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}
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//
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// Return current processor block mask
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//
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static armBlockMask getBlockMask(armP arm) {
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armBlockMask blockMask = 0;
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// get blockmask component selecting register bank
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if(USE_SP_PROCESS(arm)) {
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blockMask |= ARM_BM_USE_SP_PROCESS;
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}
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// include component for endianness
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if(SCS_FIELD(arm, AIRCR, ENDIANNESS)) {
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blockMask |= ARM_BM_BIG_ENDIAN;
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}
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// include component for alignment checking
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if(DO_UNALIGNED(arm)) {
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blockMask |= ARM_BM_UNALIGNED;
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}
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// include component for cp10 (and cp11) enable checking
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// NOTE: arm documentation specifies behavior is undefined if cp10 enable
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// differs from cp11 enable, so only cp10 enable is checked here
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Uns32 cp10Enable = SCS_FIELD(arm, CPACR, cp10);
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if(IN_USER_MODE(arm)) {
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if(cp10Enable&2) {blockMask |= ARM_BM_CP10;}
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} else {
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if(cp10Enable&1) {blockMask |= ARM_BM_CP10;}
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}
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// include CONTROL.FPCA bit
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if(CONTROL_FIELD(arm, FPCA)) {
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blockMask |= ARM_BM_FPCA;
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}
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// include FPCCR.ASPEN bit
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if(SCS_FIELD(arm, FPCCR, ASPEN)) {
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blockMask |= ARM_BM_ASPEN;
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}
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// include FPCCR.LSPACT bit
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if(SCS_FIELD(arm, FPCCR, LSPACT)) {
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blockMask |= ARM_BM_LSPACT;
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}
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||||
return blockMask;
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||||
}
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||||
//
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||||
// Update processor block mask
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//
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void armSetBlockMask(armP arm) {
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vmirtSetBlockMask((vmiProcessorP)arm, getBlockMask(arm));
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}
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||||
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//
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||||
// Update processor mode when system state that affects it has been written
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||||
//
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||||
static void updateMode(armP arm) {
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// update block mask
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armSetBlockMask(arm);
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// switch mode if required
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armSwitchMode(arm);
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}
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//
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// Write CONTROL.SP_PROCESS field
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//
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void armWriteSPProcess(armP arm, Bool newUseSPProcess) {
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Bool oldUseSPProcess = USE_SP_PROCESS(arm);
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if(oldUseSPProcess!=newUseSPProcess) {
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// update CONTROL.SP_PROCESS
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USE_SP_PROCESS(arm) = newUseSPProcess;
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// switch banked registers
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armSwitchRegs(arm, oldUseSPProcess, newUseSPProcess);
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// update block mask
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armSetBlockMask(arm);
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}
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}
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//
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// Read CPSR register
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//
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Uns32 armReadCPSR(armP arm) {
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// seed flag fields from flag structure
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PSR_FIELD(arm, Z) = arm->aflags.ZF;
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PSR_FIELD(arm, N) = arm->aflags.NF;
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PSR_FIELD(arm, C) = arm->aflags.CF;
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PSR_FIELD(arm, V) = arm->aflags.VF;
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PSR_FIELD(arm, Q) = arm->oflags.QF;
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// seed if-then state fields
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PSR_FIELD(arm, IT10) = arm->itStateRT & 0x3;
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PSR_FIELD(arm, IT72) = arm->itStateRT >> 2;
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// return derived value
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return arm->sregs.PSR.reg;
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}
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//
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// Read CONTROL register
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//
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Uns32 armReadCONTROL(armP arm) {
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// return value
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return arm->sregs.CONTROL.reg;
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}
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//
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// Write CPSR register
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//
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void armWriteCPSR(armP arm, Uns32 value, Uns32 mask) {
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// save current processor mode
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Bool oldHandlerMode = IN_HANDLER_MODE(arm);
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||||
Bool oldCPSRT = PSR_FIELD(arm, T);
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if (!DSP_PRESENT(arm)) {
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// GE fields reserved when DSP not implemented
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mask &= ~PSR_GE;
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}
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// set new register value (writable bits only)
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arm->sregs.PSR.reg = (value & mask) | (arm->sregs.PSR.reg & ~mask);
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// get new processor mode
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Bool newHandlerMode = IN_HANDLER_MODE(arm);
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Bool newCPSRT = PSR_FIELD(arm, T);
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// update arithmetic flag fields if required
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if(mask & PSR_FLAGS) {
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arm->aflags.ZF = PSR_FIELD(arm, Z);
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arm->aflags.NF = PSR_FIELD(arm, N);
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arm->aflags.CF = PSR_FIELD(arm, C);
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arm->aflags.VF = PSR_FIELD(arm, V);
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arm->oflags.QF = PSR_FIELD(arm, Q);
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}
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// update if-then state if required
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if(mask & PSR_IT) {
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arm->itStateRT = (PSR_FIELD(arm, IT10) | (PSR_FIELD(arm, IT72<<2)));
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}
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||||
// update processor mode if required
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||||
if((oldHandlerMode!=newHandlerMode) || (oldCPSRT!=newCPSRT)) {
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updateMode(arm);
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}
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}
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//
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// Write PRIMASK register
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//
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||||
void armWritePRIMASK(armP arm, Uns32 value) {
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||||
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value &= PRIMASK_MASK;
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||||
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||||
if(arm->sregs.PRIMASK != value) {
|
||||
arm->sregs.PRIMASK = value;
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armRefreshExecutionPriority(arm);
|
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}
|
||||
}
|
||||
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||||
//
|
||||
// Write BASEPRI register
|
||||
//
|
||||
void armWriteBASEPRI(armP arm, Uns32 value) {
|
||||
|
||||
value &= (BASEPRI_MASK & arm->priorityMask);
|
||||
|
||||
if(arm->sregs.BASEPRI != value) {
|
||||
arm->sregs.BASEPRI = value;
|
||||
armRefreshExecutionPriority(arm);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Write BASEPRI register (using BASEPRI_MAX semantics)
|
||||
//
|
||||
void armWriteBASEPRI_MAX(armP arm, Uns32 value) {
|
||||
|
||||
value &= (BASEPRI_MASK & arm->priorityMask);
|
||||
|
||||
if(value && ((value<arm->sregs.BASEPRI) || !arm->sregs.BASEPRI)) {
|
||||
arm->sregs.BASEPRI = value;
|
||||
armRefreshExecutionPriority(arm);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Write FAULTMASK register
|
||||
//
|
||||
void armWriteFAULTMASK(armP arm, Uns32 value) {
|
||||
|
||||
value &= FAULTMASK_MASK;
|
||||
|
||||
if((arm->executionPriority>-1) && (value!=arm->sregs.FAULTMASK)) {
|
||||
arm->sregs.FAULTMASK = value;
|
||||
armRefreshExecutionPriority(arm);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// update the CONTROL.FPCA bit to the value. If it changes then set the block mask
|
||||
//
|
||||
void armUpdateFPCA(armP arm, Bool value) {
|
||||
|
||||
// if CONTROL.FPCA changes set new value and set the block mask
|
||||
if (CONTROL_FIELD(arm, FPCA) != value) {
|
||||
|
||||
CONTROL_FIELD(arm, FPCA) = value;
|
||||
armSetBlockMask(arm);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// update the FPCCR.LSPACT bit to the value. If it changes then set the block mask
|
||||
//
|
||||
void armUpdateLSPACT(armP arm, Bool value) {
|
||||
|
||||
// if FPCCR.LSPACT changes set new value and set the block mask
|
||||
if (SCS_FIELD(arm, FPCCR, LSPACT) != value) {
|
||||
|
||||
SCS_FIELD(arm, FPCCR, LSPACT) = value;
|
||||
armSetBlockMask(arm);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Write CONTROL register
|
||||
//
|
||||
void armWriteCONTROL(armP arm, Uns32 value) {
|
||||
|
||||
armCONTROL u = {reg:value};
|
||||
|
||||
// update CONTROL.FPCA (FPCA is only implemented if FPU is present)
|
||||
if (FPU_PRESENT(arm)) {
|
||||
armUpdateFPCA(arm, u.fields.FPCA);
|
||||
}
|
||||
|
||||
// update CONTROL.threadUnpriv
|
||||
Bool oldUserMode = IN_USER_MODE(arm);
|
||||
CONTROL_FIELD(arm, threadUnpriv) = u.fields.threadUnpriv;
|
||||
Bool newUserMode = IN_USER_MODE(arm);
|
||||
|
||||
// handle any switch to user mode
|
||||
if(oldUserMode!=newUserMode) {
|
||||
updateMode(arm);
|
||||
}
|
||||
|
||||
// CONTROL.useSP_Process may only be modified in Thread mode
|
||||
if(!IN_HANDLER_MODE(arm)) {
|
||||
armWriteSPProcess(arm, u.fields.useSP_Process);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Write SP register
|
||||
//
|
||||
void armWriteSP(armP arm, Uns32 value) {
|
||||
arm->regs[ARM_REG_SP] = value & ~3;
|
||||
}
|
||||
|
||||
//
|
||||
// Switch processor mode if required
|
||||
//
|
||||
void armSwitchMode(armP arm) {
|
||||
|
||||
armMode mode;
|
||||
|
||||
if(!IN_THUMB_MODE(arm)) {
|
||||
|
||||
// invalid mode
|
||||
mode = ARM_MODE_ARM;
|
||||
SCS_FIELD(arm, CFSR, INVSTATE) = 1;
|
||||
|
||||
} else {
|
||||
|
||||
mode = 0;
|
||||
|
||||
// user/kernel mode mask
|
||||
if(IN_USER_MODE(arm)) {
|
||||
mode |= ARM_MODE_U;
|
||||
}
|
||||
|
||||
// add MPU enable mask
|
||||
if(!MPU_ENABLED(arm)) {
|
||||
// no action
|
||||
} else if(arm->executionPriority>=0) {
|
||||
mode |= ARM_MODE_MPU;
|
||||
} else if(SCS_FIELD(arm, MPU_CONTROL, HFNMIENA)) {
|
||||
mode |= ARM_MODE_MPU;
|
||||
}
|
||||
}
|
||||
|
||||
// switch mode if required
|
||||
if(mode != arm->mode) {
|
||||
vmirtSetMode((vmiProcessorP)arm, mode);
|
||||
arm->mode = mode;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// PROCESSOR RUN STATE TRANSITION HANDLING
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// If this memory access callback is triggered, abort any active load linked
|
||||
//
|
||||
static VMI_MEM_WATCH_FN(abortEA) {
|
||||
armAbortExclusiveAccess((armP)userData);
|
||||
}
|
||||
|
||||
//
|
||||
// Install or remove the exclusive access monitor callback
|
||||
//
|
||||
static void updateExclusiveAccessCallback(armP arm, Bool install) {
|
||||
|
||||
memDomainP domain = vmirtGetProcessorDataDomain((vmiProcessorP)arm);
|
||||
Uns32 simLow = arm->exclusiveTag;
|
||||
Uns32 simHigh = simLow + ~arm->exclusiveTagMask;
|
||||
|
||||
// install or remove a watchpoint on the current exclusive access address
|
||||
if(install) {
|
||||
vmirtAddWriteCallback(domain, simLow, simHigh, abortEA, arm);
|
||||
} else {
|
||||
vmirtRemoveWriteCallback(domain, simLow, simHigh, abortEA, arm);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Abort any active exclusive access
|
||||
//
|
||||
void armAbortExclusiveAccess(armP arm) {
|
||||
|
||||
if(arm->exclusiveTag != ARM_NO_TAG) {
|
||||
|
||||
// remove callback on exclusive access monitor region
|
||||
updateExclusiveAccessCallback(arm, False);
|
||||
|
||||
// clear exclusive tag (AFTER updateExclusiveAccessCallback)
|
||||
arm->exclusiveTag = ARM_NO_TAG;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// This is called on simulator context switch (when this processor is either
|
||||
// about to start or about to stop simulation)
|
||||
//
|
||||
VMI_IASSWITCH_FN(armContextSwitchCB) {
|
||||
|
||||
armP arm = (armP)processor;
|
||||
|
||||
// establish a watchpoint on a pending exclusive address to detect if that
|
||||
// address is written elsewhere.
|
||||
if(arm->exclusiveTag != ARM_NO_TAG) {
|
||||
updateExclusiveAccessCallback(arm, state==RS_SUSPEND);
|
||||
}
|
||||
|
||||
// if a processor is about to be run, make state consistent with any changes
|
||||
// that may have occurred while the processor was suspended
|
||||
if(state==RS_RUN) {
|
||||
armSetBlockMask(arm);
|
||||
}
|
||||
}
|
||||
|
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Reference in New Issue
Block a user