Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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adrian
284
simulators/ovp/armmModel/armmMain.c
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284
simulators/ovp/armmModel/armmMain.c
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/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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// standard header files
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#include <string.h>
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// VMI header files
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#include "vmi/vmiAttrs.h"
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#include "vmi/vmiCommand.h"
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#include "vmi/vmiMessage.h"
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#include "vmi/vmiRt.h"
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// model header files
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#include "armConfig.h"
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#include "armDecode.h"
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#include "armDebug.h"
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#include "armmDoc.h"
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#include "armExceptions.h"
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#include "armFunctions.h"
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#include "armMode.h"
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#include "armmParameters.h"
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#include "armStructure.h"
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#include "armSys.h"
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#include "armSysRegisters.h"
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#include "armUtils.h"
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#include "armVM.h"
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#include "armVFP.h"
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#include <stdio.h>
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//
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// Prefix for messages from this module
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//
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#define CPU_PREFIX "ARM_MAIN"
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////////////////////////////////////////////////////////////////////////////////
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// PARSING CONFIGURATION OPTIONS
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////////////////////////////////////////////////////////////////////////////////
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//
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// Return processor configuration variant argument
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//
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static armConfigCP getConfigVariantArg(armP arm, armParamValuesP params) {
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armConfigCP match;
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if(params->SETBIT(variant)) {
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match = &armConfigTable[params->variant];
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} else {
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match = armConfigTable;
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if(arm->verbose) {
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// report the value specified for an option in verbose mode
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vmiMessage("I", CPU_PREFIX"_ANS1",
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"Attribute '%s' not specified; defaulting to '%s'",
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"variant",
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match->name
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);
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}
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}
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// return matching configuration
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return match;
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}
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////////////////////////////////////////////////////////////////////////////////
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// CONSTRUCTOR AND DESTRUCTOR
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////////////////////////////////////////////////////////////////////////////////
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// specify default value for entire system register
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#define SET_SCS_REG_DEFAULT(_R, _V) \
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union {Uns32 u32; SCS_REG_DECL(_R);} _U = {_V}; \
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SCS_REG_STRUCT_DEFAULT(arm, _R) = _U._R
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//
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// Initialize processor exclusiveTagMask
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//
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static void setExclusiveTagMask(armP arm) {
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arm->exclusiveTagMask = (-1 << (arm->configInfo.ERG+2));
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}
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void failSALset(unsigned int pointer);
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//
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// ARM processor constructor
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//
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VMI_CONSTRUCTOR_FN(armConstructor) {
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armP arm = (armP)processor;
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armParamValuesP params = (armParamValuesP)parameterValues;
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// initialize exclusive tag
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arm->exclusiveTag = ARM_NO_TAG;
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// save flags on processor structure
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arm->flags = vmirtProcessorFlags(processor);
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unsigned int failp = params->fail_salp;
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failSALset(failp);
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// get string configuration options
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arm->simEx = simulateExceptions;
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arm->verbose = params->verbose;
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arm->compatMode = params->compatibility;
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arm->showHiddenRegs = params->showHiddenRegs;
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arm->UAL = params->UAL;
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arm->disableBitBand = params->disableBitBand;
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// get default variant information
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arm->configInfo = *getConfigVariantArg(arm, params);
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// override data endianness
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armSetInitialEndian(arm, params->endian);
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// override instruction endianness
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arm->instructionEndian = params->instructionEndian;
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// override other configuration values
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if(params->SETBIT(override_debugMask)) {
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arm->flags = params->override_debugMask;
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}
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if(params->SETBIT(override_CPUID)) {
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SET_SCS_REG_DEFAULT(CPUID, params->override_CPUID);
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}
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if(params->SETBIT(override_MPU_TYPE)) {
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SET_SCS_REG_DEFAULT(MPU_TYPE, params->override_MPU_TYPE);
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}
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if(params->SETBIT(override_InstructionAttributes0)) {
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SET_SCS_REG_DEFAULT(ID_ISAR0, params->override_InstructionAttributes0);
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}
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if(params->SETBIT(override_InstructionAttributes1)) {
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SET_SCS_REG_DEFAULT(ID_ISAR1, params->override_InstructionAttributes1);
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}
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if(params->SETBIT(override_InstructionAttributes2)) {
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SET_SCS_REG_DEFAULT(ID_ISAR2, params->override_InstructionAttributes2);
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}
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if(params->SETBIT(override_InstructionAttributes3)) {
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SET_SCS_REG_DEFAULT(ID_ISAR3, params->override_InstructionAttributes3);
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}
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if(params->SETBIT(override_InstructionAttributes4)) {
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SET_SCS_REG_DEFAULT(ID_ISAR4, params->override_InstructionAttributes4);
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}
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if(params->SETBIT(override_InstructionAttributes5)) {
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SET_SCS_REG_DEFAULT(ID_ISAR5, params->override_InstructionAttributes5);
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}
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if(params->SETBIT(override_MVFR0)) {
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SET_SCS_REG_DEFAULT(MVFR0, params->override_MVFR0);
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}
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if(params->SETBIT(override_MVFR1)) {
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SET_SCS_REG_DEFAULT(MVFR1, params->override_MVFR1);
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}
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if(params->SETBIT(override_rotateUnaligned)) {
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arm->configInfo.rotateUnaligned = params->override_rotateUnaligned;
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}
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if(params->SETBIT(override_align64as32)) {
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arm->configInfo.align64as32 = params->override_align64as32;
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}
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if(params->SETBIT(override_STRoffsetPC12)) {
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arm->configInfo.STRoffsetPC12 = params->override_STRoffsetPC12;
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}
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if(params->SETBIT(override_ERG)) {
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arm->configInfo.ERG = params->override_ERG;
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}
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if(params->SETBIT(override_priorityBits)) {
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arm->configInfo.priorityBitsM1 = params->override_priorityBits-1;
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}
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if(params->SETBIT(override_numInterrupts)) {
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NUM_INTERRUPTS(arm) = params->override_numInterrupts;
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}
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// set read-only registers to their initial state (AFTER applying overrides)
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armSysInitialize(arm);
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// register view objects and event handlers (AFTER armSysInitialize)
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vmiViewObjectP viewObject = vmirtGetProcessorViewObject(processor);
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armAddSysRegistersView(arm, viewObject);
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// Initialize FPU if present
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armFPInitialize(arm);
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// Check for user enable of VFP instructions at reset?
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if (params->SETBIT(enableVFPAtReset) && params->enableVFPAtReset) {
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SCS_FIELD_DEFAULT(arm, CPACR, cp10) = 3;
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SCS_FIELD_DEFAULT(arm, CPACR, cp11) = 3;
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}
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// initialize exclusiveTagMask
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setExclusiveTagMask(arm);
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// initialize priority mask
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Uns32 priorityBits = PRIORITY_BITS(arm);
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arm->priorityMask = ((1<<priorityBits)-1) << (8-priorityBits);
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arm->priorityMask |= arm->priorityMask << 8;
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arm->priorityMask |= arm->priorityMask << 16;
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// ensure number of external interrupts is in bounds
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if(NUM_INTERRUPTS(arm)>ARM_INTERRUPT_NUM) {
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NUM_INTERRUPTS(arm) = ARM_INTERRUPT_NUM;
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}
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// initialize exception mask number and top mask
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arm->exceptNum = NUM_INTERRUPTS(arm) + AEN_ExternalInt0;
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arm->exceptMaskNum = (arm->exceptNum+31)/32;
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// indicate reset exception is pending; otherwise, force into Thumb mode
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// (default is ARM mode)
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if(!ARM_DISASSEMBLE(arm) && params->resetAtTime0) {
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armRaise(arm, AEN_Reset);
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} else {
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IN_THUMB_MODE(arm) = 1;
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}
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// reset stack pointer (and banked variants) in gdb compatibility mode
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if(arm->compatMode==COMPAT_GDB) {
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arm->regs[ARM_REG_SP] = 0x800;
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arm->bank.R13_process = 0x800;
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}
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// force into thumb mode if required
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if(ARM_THUMB(arm)) {
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IN_THUMB_MODE(arm) = 1;
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}
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// set callbacks (for intercept libraries)
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arm->decoderCB = armDecode;
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arm->isizeCB = armGetInstructionSizeMode;
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// create port specifications
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armNewPortSpecs(arm);
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// install documentation
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armmDoc(processor, parameterValues);
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}
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//
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// ARM processor destructor
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//
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VMI_DESTRUCTOR_FN(armDestructor) {
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armP arm = (armP)processor;
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// free port specifications
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armFreePortSpecs(arm);
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// free virtual memory structures
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armVMFree(arm);
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}
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