Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
488
simulators/ovp/armmModel/armmConfigList.c
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488
simulators/ovp/armmModel/armmConfigList.c
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@ -0,0 +1,488 @@
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/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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||||
* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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||||
* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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||||
* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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||||
* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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||||
* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
|
||||
* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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||||
* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
|
||||
* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
|
||||
* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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||||
* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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||||
*
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||||
* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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||||
* you may not use this file except in compliance with the License.
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||||
* You may obtain a copy of the License at
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||||
*
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||||
* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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||||
* distributed under the License is distributed on an "AS IS" BASIS,
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||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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||||
* either express or implied.
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||||
*
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||||
* See the License for the specific language governing permissions and
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||||
* limitations under the License.
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||||
*
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||||
*/
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||||
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||||
// model header files
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#include "armConfig.h"
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#include "armVariant.h"
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const struct armConfigS armConfigTable[] = {
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////////////////////////////////////////////////////////////////////////////
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// ISA CONFIGURATIONS
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////////////////////////////////////////////////////////////////////////////
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{.name = "ARMv7-M", .arch = ARM_V7, .rotateUnaligned = True},
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////////////////////////////////////////////////////////////////////////////
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// PROCESSOR MODEL CONFIGURATIONS
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////////////////////////////////////////////////////////////////////////////
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{
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.name = "Cortex-M3",
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.arch = ARM_V7,
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.numInterrupts = 16,
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.rotateUnaligned = False,
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.align64as32 = True, // ARMv7-M has no 64-bit load/stores
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.STRoffsetPC12 = False, // required value for ARMv7 on
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.priorityBitsM1 = 2, // number of priority bits (minus 1)
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||||
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.regDefaults = {
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||||
.CPUID = {
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.REVISION = 0,
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.PARTNO = 0xc23,
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.ARCHITECTURE = 0xf,
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.VARIANT = 0x2,
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.IMPLEMENTER = AI_ARM
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},
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||||
.ID_PFR0 = {
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.State0 = 0, // 32-bit ARM instruction set support
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||||
.State1 = 3, // Thumb encoding support
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.State2 = 0, // Jazelle support
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||||
.State3 = 0 // ThumbEE support
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},
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||||
.ID_PFR1 = {
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.ProgrammersModel = 0, // ARM programmer's model
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||||
.SecurityExtension = 0, // Security Extensions support
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||||
.MicroProgrammersModel = 2 // Microcontroller programmer's model
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||||
},
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||||
.ID_DFR0 = {
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||||
.CoreDebug = 0, // Core debug model
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||||
.SecureDebug = 0, // Secure debug model
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||||
.EmbeddedDebug = 0, // Embedded debug model
|
||||
.TraceDebugCP = 0, // Trace debug model, coprocessor-based
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||||
.TraceDebugMM = 0, // Trace debug model, memory mapped
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||||
.MicroDebug = 0, // Microcontroller debug model
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||||
},
|
||||
.ID_MMFR0 = {
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||||
.VMSA = 0, // VMSA support
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||||
.PMSA = 3, // PMSA support
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||||
.Cache_Agent = 0, // Cache coherency + CPU agent
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||||
.Cache_DMA = 0, // Cache coherency + associated DMA
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||||
.TCM_DMA = 0, // TCM + associated DMA
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||||
.AuxControl = 0, // ARMv6 Auxillary Control register
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||||
.FCSE = 0, // FCSE support
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},
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.ID_MMFR1 = {
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||||
.L1VAHarvard = 0, // L1 maintainence by VA, Harvard
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||||
.L1VAUnified = 0, // L1 maintainence by VA, unified
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||||
.L1SWHarvard = 0, // L1 maintainence by Set/Way, Harvard
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||||
.L1SWUnified = 0, // L1 maintainence by Set/Way, unified
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||||
.L1Harvard = 0, // L1 maintainence, Harvard
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||||
.L1Unified = 0, // L1 maintainence, unified
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||||
.L1TestClean = 0, // L1 test and clean
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||||
.BTB = 0 // Branch target buffer
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||||
},
|
||||
.ID_MMFR2 = {
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||||
.L1FgndPrefetchHarvard = 0, // L1 F/ground cache p/fetch range, Harvard
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||||
.L1BgndPrefetchHarvard = 0, // L1 B/ground cache p/fetch range, Harvard
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||||
.L1MaintRangeHarvard = 0, // L1 maintanence range, Harvard
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||||
.TLBMaintHarvard = 0, // TLB maintanence, Harvard
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||||
.TLBMaintUnified = 0, // TLB maintanence, Unified
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||||
.MemoryBarrierCP15 = 0, // Memory Barrier, CP15 based
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||||
.WaitForInterruptStall = 0, // Wait-for-interrupt stalling
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||||
.HWAccessFlag = 0 // hardware access flag support
|
||||
},
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||||
.ID_MMFR3 = {
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||||
.HierMaintSW = 0, // Hierarchical cache maintainence, set/way
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||||
.HierMaintMVA = 0, // Hierarchical cache maintainence, MVA
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||||
.BPMaint = 0, // Branch predictor maintainence
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||||
},
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||||
.ID_ISAR0 = {
|
||||
.Swap_instrs = 0, // Atomic instructions
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||||
.BitCount_instrs = 1, // BitCount instructions
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||||
.BitField_instrs = 1, // BitField instructions
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||||
.CmpBranch_instrs = 1, // CmpBranch instructions
|
||||
.Coproc_instrs = 4, // Coprocessor instructions
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||||
.Debug_instrs = 1, // Debug instructions
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||||
.Divide_instrs = 1, // Divide instructions
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||||
},
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||||
.ID_ISAR1 = {
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||||
.Endian_instrs = 0, // Endian instructions
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||||
.Except_instrs = 0, // Exception instructions
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||||
.Except_AR_instrs = 0, // A/R profile exception instructions
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||||
.Extend_instrs = 1, // Extend instructions
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||||
.IfThen_instrs = 1, // IfThen instructions
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.Immediate_instrs = 1, // Immediate instructions
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||||
.Interwork_instrs = 2, // Interwork instructions
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||||
.Jazelle_instrs = 0 // Jazelle instructions
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||||
},
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||||
.ID_ISAR2 = {
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||||
.LoadStore_instrs = 1, // LoadStore instructions
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||||
.MemHint_instrs = 3, // MemoryHint instructions
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||||
.MultiAccessInt_instrs = 2, // Multi-access interruptible instructions
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||||
.Mult_instrs = 2, // Multiply instructions
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||||
.MultS_instrs = 1, // Multiply instructions, advanced signed
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||||
.MultU_instrs = 1, // Multiply instructions, advanced unsigned
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||||
.PSR_AR_instrs = 1, // A/R profile PSR instructions
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||||
.Reversal_instrs = 2 // Reversal instructions
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||||
},
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||||
.ID_ISAR3 = {
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||||
.Saturate_instrs = 0, // Saturate instructions
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||||
.SIMD_instrs = 1, // SIMD instructions
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||||
.SVC_instrs = 1, // SVC instructions
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||||
.SynchPrim_instrs = 1, // SynchPrim instructions
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||||
.TabBranch_instrs = 1, // TableBranch instructions
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||||
.ThumbCopy_instrs = 1, // ThumbCopy instructions
|
||||
.TrueNOP_instrs = 1, // TrueNOP instructions
|
||||
.T2ExeEnvExtn_instrs = 0 // Thumb-2 Execution env extensions
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||||
},
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||||
.ID_ISAR4 = {
|
||||
.Unpriv_instrs = 2, // Unprivileged instructions
|
||||
.WithShifts_instrs = 0, // Shift instructions
|
||||
.Writeback_instrs = 1, // Writeback instructions
|
||||
.SMI_instrs = 0, // SMI instructions
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||||
.Barrier_instrs = 1, // Barrier instructions
|
||||
.SynchPrim_instrs_frac = 3, // Fractional support for sync primitive instructions
|
||||
.PSR_M_instrs = 1, // M-profile forms of PSR instructions
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||||
.SWP_frac = 0 // memory system bus locking
|
||||
},
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||||
.ICTR = {
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||||
.INTLINESNUM = 0 // number of interrupt lines supported
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||||
},
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.ACTLR = {0}, // auxillary control register
|
||||
.MPU_TYPE = {
|
||||
.SEPARATE = 0, // unified MPU
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||||
.DREGION = 8, // number of data/unified memory regions
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||||
.IREGION = 0 // number of instruction memory regions
|
||||
},
|
||||
.SYST_CALIB = {
|
||||
.NOREF = 0, // reference clock provided
|
||||
.SKEW = 0, // whether calibration value inexact
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||||
.TENMS = 0 // 10ms reload value
|
||||
}
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},
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.regMasks = {
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}
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},
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{
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||||
.name = "Cortex-M4",
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.arch = ARM_V7,
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||||
.numInterrupts = 16,
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||||
.rotateUnaligned = False,
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||||
.align64as32 = True, // ARMv7-M has no 64-bit load/stores
|
||||
.STRoffsetPC12 = False, // required value for ARMv7 on
|
||||
.priorityBitsM1 = 2, // number of priority bits (minus 1)
|
||||
|
||||
.regDefaults = {
|
||||
.CPUID = {
|
||||
.REVISION = 1,
|
||||
.PARTNO = 0xc24,
|
||||
.ARCHITECTURE = 0xf,
|
||||
.VARIANT = 0x0,
|
||||
.IMPLEMENTER = AI_ARM
|
||||
},
|
||||
.ID_PFR0 = {
|
||||
.State0 = 0, // 32-bit ARM instruction set support
|
||||
.State1 = 3, // Thumb encoding support
|
||||
.State2 = 0, // Jazelle support
|
||||
.State3 = 0 // ThumbEE support
|
||||
},
|
||||
.ID_PFR1 = {
|
||||
.ProgrammersModel = 0, // ARM programmer's model
|
||||
.SecurityExtension = 0, // Security Extensions support
|
||||
.MicroProgrammersModel = 2 // Microcontroller programmer's model
|
||||
},
|
||||
.ID_DFR0 = {
|
||||
.CoreDebug = 0, // Core debug model
|
||||
.SecureDebug = 0, // Secure debug model
|
||||
.EmbeddedDebug = 0, // Embedded debug model
|
||||
.TraceDebugCP = 0, // Trace debug model, coprocessor-based
|
||||
.TraceDebugMM = 0, // Trace debug model, memory mapped
|
||||
.MicroDebug = 0, // Microcontroller debug model
|
||||
},
|
||||
.ID_MMFR0 = {
|
||||
.VMSA = 0, // VMSA support
|
||||
.PMSA = 3, // PMSA support
|
||||
.Cache_Agent = 0, // Cache coherency + CPU agent
|
||||
.Cache_DMA = 0, // Cache coherency + associated DMA
|
||||
.TCM_DMA = 0, // TCM + associated DMA
|
||||
.AuxControl = 0, // ARMv6 Auxillary Control register
|
||||
.FCSE = 0, // FCSE support
|
||||
},
|
||||
.ID_MMFR1 = {
|
||||
.L1VAHarvard = 0, // L1 maintainence by VA, Harvard
|
||||
.L1VAUnified = 0, // L1 maintainence by VA, unified
|
||||
.L1SWHarvard = 0, // L1 maintainence by Set/Way, Harvard
|
||||
.L1SWUnified = 0, // L1 maintainence by Set/Way, unified
|
||||
.L1Harvard = 0, // L1 maintainence, Harvard
|
||||
.L1Unified = 0, // L1 maintainence, unified
|
||||
.L1TestClean = 0, // L1 test and clean
|
||||
.BTB = 0 // Branch target buffer
|
||||
},
|
||||
.ID_MMFR2 = {
|
||||
.L1FgndPrefetchHarvard = 0, // L1 F/ground cache p/fetch range, Harvard
|
||||
.L1BgndPrefetchHarvard = 0, // L1 B/ground cache p/fetch range, Harvard
|
||||
.L1MaintRangeHarvard = 0, // L1 maintanence range, Harvard
|
||||
.TLBMaintHarvard = 0, // TLB maintanence, Harvard
|
||||
.TLBMaintUnified = 0, // TLB maintanence, Unified
|
||||
.MemoryBarrierCP15 = 0, // Memory Barrier, CP15 based
|
||||
.WaitForInterruptStall = 0, // Wait-for-interrupt stalling
|
||||
.HWAccessFlag = 0 // hardware access flag support
|
||||
},
|
||||
.ID_MMFR3 = {
|
||||
.HierMaintSW = 0, // Hierarchical cache maintainence, set/way
|
||||
.HierMaintMVA = 0, // Hierarchical cache maintainence, MVA
|
||||
.BPMaint = 0, // Branch predictor maintainence
|
||||
},
|
||||
.ID_ISAR0 = {
|
||||
.Swap_instrs = 0, // Atomic instructions
|
||||
.BitCount_instrs = 1, // BitCount instructions
|
||||
.BitField_instrs = 1, // BitField instructions
|
||||
.CmpBranch_instrs = 1, // CmpBranch instructions
|
||||
.Coproc_instrs = 4, // Coprocessor instructions
|
||||
.Debug_instrs = 1, // Debug instructions
|
||||
.Divide_instrs = 1, // Divide instructions
|
||||
},
|
||||
.ID_ISAR1 = {
|
||||
.Endian_instrs = 0, // Endian instructions
|
||||
.Except_instrs = 0, // Exception instructions
|
||||
.Except_AR_instrs = 0, // A/R profile exception instructions
|
||||
.Extend_instrs = 2, // Extend instructions
|
||||
.IfThen_instrs = 1, // IfThen instructions
|
||||
.Immediate_instrs = 1, // Immediate instructions
|
||||
.Interwork_instrs = 2, // Interwork instructions
|
||||
.Jazelle_instrs = 0 // Jazelle instructions
|
||||
},
|
||||
.ID_ISAR2 = {
|
||||
.LoadStore_instrs = 1, // LoadStore instructions
|
||||
.MemHint_instrs = 3, // MemoryHint instructions
|
||||
.MultiAccessInt_instrs = 2, // Multi-access interruptible instructions
|
||||
.Mult_instrs = 2, // Multiply instructions
|
||||
.MultS_instrs = 3, // Multiply instructions, advanced signed
|
||||
.MultU_instrs = 2, // Multiply instructions, advanced unsigned
|
||||
.PSR_AR_instrs = 1, // A/R profile PSR instructions
|
||||
.Reversal_instrs = 2 // Reversal instructions
|
||||
},
|
||||
.ID_ISAR3 = {
|
||||
.Saturate_instrs = 1, // Saturate instructions
|
||||
.SIMD_instrs = 3, // SIMD instructions
|
||||
.SVC_instrs = 1, // SVC instructions
|
||||
.SynchPrim_instrs = 1, // SynchPrim instructions
|
||||
.TabBranch_instrs = 1, // TableBranch instructions
|
||||
.ThumbCopy_instrs = 1, // ThumbCopy instructions
|
||||
.TrueNOP_instrs = 1, // TrueNOP instructions
|
||||
.T2ExeEnvExtn_instrs = 0 // Thumb-2 Execution env extensions
|
||||
},
|
||||
.ID_ISAR4 = {
|
||||
.Unpriv_instrs = 2, // Unprivileged instructions
|
||||
.WithShifts_instrs = 3, // Shift instructions
|
||||
.Writeback_instrs = 1, // Writeback instructions
|
||||
.SMI_instrs = 0, // SMI instructions
|
||||
.Barrier_instrs = 1, // Barrier instructions
|
||||
.SynchPrim_instrs_frac = 3, // Fractional support for sync primitive instructions
|
||||
.PSR_M_instrs = 1, // M-profile forms of PSR instructions
|
||||
.SWP_frac = 0 // memory system bus locking
|
||||
},
|
||||
.ICTR = {
|
||||
.INTLINESNUM = 0 // number of interrupt lines supported
|
||||
},
|
||||
.ACTLR = {0}, // auxillary control register
|
||||
.MPU_TYPE = {
|
||||
.SEPARATE = 0, // unified MPU
|
||||
.DREGION = 8, // number of data/unified memory regions
|
||||
.IREGION = 0 // number of instruction memory regions
|
||||
},
|
||||
.SYST_CALIB = {
|
||||
.NOREF = 0, // reference clock provided
|
||||
.SKEW = 0, // whether calibration value inexact
|
||||
.TENMS = 0 // 10ms reload value
|
||||
},
|
||||
},
|
||||
|
||||
.regMasks = {
|
||||
}
|
||||
},
|
||||
|
||||
{
|
||||
.name = "Cortex-M4F",
|
||||
.arch = ARM_V7,
|
||||
.numInterrupts = 16,
|
||||
.rotateUnaligned = False,
|
||||
.align64as32 = True, // ARMv7-M has no 64-bit load/stores
|
||||
.STRoffsetPC12 = False, // required value for ARMv7 on
|
||||
.priorityBitsM1 = 2, // number of priority bits (minus 1)
|
||||
|
||||
.regDefaults = {
|
||||
.CPUID = {
|
||||
.REVISION = 1,
|
||||
.PARTNO = 0xc24,
|
||||
.ARCHITECTURE = 0xf,
|
||||
.VARIANT = 0x0,
|
||||
.IMPLEMENTER = AI_ARM
|
||||
},
|
||||
.ID_PFR0 = {
|
||||
.State0 = 0, // 32-bit ARM instruction set support
|
||||
.State1 = 3, // Thumb encoding support
|
||||
.State2 = 0, // Jazelle support
|
||||
.State3 = 0 // ThumbEE support
|
||||
},
|
||||
.ID_PFR1 = {
|
||||
.ProgrammersModel = 0, // ARM programmer's model
|
||||
.SecurityExtension = 0, // Security Extensions support
|
||||
.MicroProgrammersModel = 2 // Microcontroller programmer's model
|
||||
},
|
||||
.ID_DFR0 = {
|
||||
.CoreDebug = 0, // Core debug model
|
||||
.SecureDebug = 0, // Secure debug model
|
||||
.EmbeddedDebug = 0, // Embedded debug model
|
||||
.TraceDebugCP = 0, // Trace debug model, coprocessor-based
|
||||
.TraceDebugMM = 0, // Trace debug model, memory mapped
|
||||
.MicroDebug = 0, // Microcontroller debug model
|
||||
},
|
||||
.ID_MMFR0 = {
|
||||
.VMSA = 0, // VMSA support
|
||||
.PMSA = 3, // PMSA support
|
||||
.Cache_Agent = 0, // Cache coherency + CPU agent
|
||||
.Cache_DMA = 0, // Cache coherency + associated DMA
|
||||
.TCM_DMA = 0, // TCM + associated DMA
|
||||
.AuxControl = 0, // ARMv6 Auxillary Control register
|
||||
.FCSE = 0, // FCSE support
|
||||
},
|
||||
.ID_MMFR1 = {
|
||||
.L1VAHarvard = 0, // L1 maintainence by VA, Harvard
|
||||
.L1VAUnified = 0, // L1 maintainence by VA, unified
|
||||
.L1SWHarvard = 0, // L1 maintainence by Set/Way, Harvard
|
||||
.L1SWUnified = 0, // L1 maintainence by Set/Way, unified
|
||||
.L1Harvard = 0, // L1 maintainence, Harvard
|
||||
.L1Unified = 0, // L1 maintainence, unified
|
||||
.L1TestClean = 0, // L1 test and clean
|
||||
.BTB = 0 // Branch target buffer
|
||||
},
|
||||
.ID_MMFR2 = {
|
||||
.L1FgndPrefetchHarvard = 0, // L1 F/ground cache p/fetch range, Harvard
|
||||
.L1BgndPrefetchHarvard = 0, // L1 B/ground cache p/fetch range, Harvard
|
||||
.L1MaintRangeHarvard = 0, // L1 maintanence range, Harvard
|
||||
.TLBMaintHarvard = 0, // TLB maintanence, Harvard
|
||||
.TLBMaintUnified = 0, // TLB maintanence, Unified
|
||||
.MemoryBarrierCP15 = 0, // Memory Barrier, CP15 based
|
||||
.WaitForInterruptStall = 0, // Wait-for-interrupt stalling
|
||||
.HWAccessFlag = 0 // hardware access flag support
|
||||
},
|
||||
.ID_MMFR3 = {
|
||||
.HierMaintSW = 0, // Hierarchical cache maintainence, set/way
|
||||
.HierMaintMVA = 0, // Hierarchical cache maintainence, MVA
|
||||
.BPMaint = 0, // Branch predictor maintainence
|
||||
},
|
||||
.ID_ISAR0 = {
|
||||
.Swap_instrs = 0, // Atomic instructions
|
||||
.BitCount_instrs = 1, // BitCount instructions
|
||||
.BitField_instrs = 1, // BitField instructions
|
||||
.CmpBranch_instrs = 1, // CmpBranch instructions
|
||||
.Coproc_instrs = 4, // Coprocessor instructions
|
||||
.Debug_instrs = 1, // Debug instructions
|
||||
.Divide_instrs = 1, // Divide instructions
|
||||
},
|
||||
.ID_ISAR1 = {
|
||||
.Endian_instrs = 0, // Endian instructions
|
||||
.Except_instrs = 0, // Exception instructions
|
||||
.Except_AR_instrs = 0, // A/R profile exception instructions
|
||||
.Extend_instrs = 2, // Extend instructions
|
||||
.IfThen_instrs = 1, // IfThen instructions
|
||||
.Immediate_instrs = 1, // Immediate instructions
|
||||
.Interwork_instrs = 2, // Interwork instructions
|
||||
.Jazelle_instrs = 0 // Jazelle instructions
|
||||
},
|
||||
.ID_ISAR2 = {
|
||||
.LoadStore_instrs = 1, // LoadStore instructions
|
||||
.MemHint_instrs = 3, // MemoryHint instructions
|
||||
.MultiAccessInt_instrs = 2, // Multi-access interruptible instructions
|
||||
.Mult_instrs = 2, // Multiply instructions
|
||||
.MultS_instrs = 3, // Multiply instructions, advanced signed
|
||||
.MultU_instrs = 2, // Multiply instructions, advanced unsigned
|
||||
.PSR_AR_instrs = 1, // A/R profile PSR instructions
|
||||
.Reversal_instrs = 2 // Reversal instructions
|
||||
},
|
||||
.ID_ISAR3 = {
|
||||
.Saturate_instrs = 1, // Saturate instructions
|
||||
.SIMD_instrs = 3, // SIMD instructions
|
||||
.SVC_instrs = 1, // SVC instructions
|
||||
.SynchPrim_instrs = 1, // SynchPrim instructions
|
||||
.TabBranch_instrs = 1, // TableBranch instructions
|
||||
.ThumbCopy_instrs = 1, // ThumbCopy instructions
|
||||
.TrueNOP_instrs = 1, // TrueNOP instructions
|
||||
.T2ExeEnvExtn_instrs = 0 // Thumb-2 Execution env extensions
|
||||
},
|
||||
.ID_ISAR4 = {
|
||||
.Unpriv_instrs = 2, // Unprivileged instructions
|
||||
.WithShifts_instrs = 3, // Shift instructions
|
||||
.Writeback_instrs = 1, // Writeback instructions
|
||||
.SMI_instrs = 0, // SMI instructions
|
||||
.Barrier_instrs = 1, // Barrier instructions
|
||||
.SynchPrim_instrs_frac = 3, // Fractional support for sync primitive instructions
|
||||
.PSR_M_instrs = 1, // M-profile forms of PSR instructions
|
||||
.SWP_frac = 0 // memory system bus locking
|
||||
},
|
||||
.ICTR = {
|
||||
.INTLINESNUM = 0 // number of interrupt lines supported
|
||||
},
|
||||
.ACTLR = {0}, // auxillary control register
|
||||
.MPU_TYPE = {
|
||||
.SEPARATE = 0, // unified MPU
|
||||
.DREGION = 8, // number of data/unified memory regions
|
||||
.IREGION = 0 // number of instruction memory regions
|
||||
},
|
||||
.SYST_CALIB = {
|
||||
.NOREF = 0, // reference clock provided
|
||||
.SKEW = 0, // whether calibration value inexact
|
||||
.TENMS = 0 // 10ms reload value
|
||||
},
|
||||
.MVFR0 = {
|
||||
.A_SIMD_Registers = 1, // 16x64-bit media register bank
|
||||
.SinglePrecision = 2, // single precision supported
|
||||
.DoublePrecision = 0, // double precision not supported
|
||||
.VFP_ExceptionTrap = 0, // trapped exceptions not supported
|
||||
.Divide = 1, // VFP hardware divide supported
|
||||
.SquareRoot = 1, // VFP hardware square root supported
|
||||
.ShortVectors = 0, // VFP short vector not supported
|
||||
.VFP_RoundingModes = 1 // all VFP rounding modes supported
|
||||
},
|
||||
.MVFR1 = {
|
||||
.FlushToZeroMode = 1, // VFP denormal arithmetic supported
|
||||
.DefaultNaNMode = 1, // VFP NaN propagation supported
|
||||
.VFP_HalfPrecision = 1, // VFP half-precision not supported
|
||||
.VFP_FusedMAC = 1, // Fused multiply accumulate supported
|
||||
}
|
||||
},
|
||||
|
||||
.regMasks = {
|
||||
}
|
||||
},
|
||||
|
||||
|
||||
// null terminator
|
||||
{0}
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user