Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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adrian
240
simulators/ovp/armmModel/armMorphFunctions.h
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240
simulators/ovp/armmModel/armMorphFunctions.h
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/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_MORPH_FUNCTIONS_H
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#define ARM_MORPH_FUNCTIONS_H
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// model header files
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#include "armMode.h"
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#include "armMorph.h"
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// unop instructions
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ARM_MORPH_FN(armEmitUnopI);
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ARM_MORPH_FN(armEmitUnopR);
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ARM_MORPH_FN(armEmitUnopRSI);
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ARM_MORPH_FN(armEmitUnopRSR);
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ARM_MORPH_FN(armEmitUnopRSRT);
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ARM_MORPH_FN(armEmitUnopRX);
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// binop instructions
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ARM_MORPH_FN(armEmitBinopI);
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ARM_MORPH_FN(armEmitBinopR);
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ARM_MORPH_FN(armEmitBinopRT);
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ARM_MORPH_FN(armEmitBinopIT);
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ARM_MORPH_FN(armEmitBinopADR);
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ARM_MORPH_FN(armEmitBinopRSI);
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ARM_MORPH_FN(armEmitBinopRSR);
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ARM_MORPH_FN(armEmitBinopRX);
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// cmpop instructions
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ARM_MORPH_FN(armEmitCmpopI);
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ARM_MORPH_FN(armEmitCmpopR);
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ARM_MORPH_FN(armEmitCmpopRSI);
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ARM_MORPH_FN(armEmitCmpopRX);
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// multiply and divide instructions
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ARM_MORPH_FN(armEmitMUL);
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ARM_MORPH_FN(armEmitMLA);
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ARM_MORPH_FN(armEmitMLS);
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ARM_MORPH_FN(armEmitDIV);
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ARM_MORPH_FN(armEmitMULL);
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ARM_MORPH_FN(armEmitMLAL);
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// branch instructions
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ARM_MORPH_FN(armEmitBranchC);
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ARM_MORPH_FN(armEmitBranchR);
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ARM_MORPH_FN(armEmitBLX);
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// miscellaneous instructions
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ARM_MORPH_FN(armEmitCLZ);
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ARM_MORPH_FN(armEmitBKPT);
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ARM_MORPH_FN(armEmitSWI);
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// load and store instructions
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ARM_MORPH_FN(armEmitLDRI);
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ARM_MORPH_FN(armEmitLDRR);
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ARM_MORPH_FN(armEmitLDRRSI);
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ARM_MORPH_FN(armEmitLDM1);
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ARM_MORPH_FN(armEmitSTRI);
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ARM_MORPH_FN(armEmitSTRR);
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ARM_MORPH_FN(armEmitSTRRSI);
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ARM_MORPH_FN(armEmitSTM1);
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// coprocessor instructions
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ARM_MORPH_FN(armEmitUsageFaultCP);
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// status register access instructions
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ARM_MORPH_FN(armEmitMRS);
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ARM_MORPH_FN(armEmitMSR);
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// DSP data processing instructions
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ARM_MORPH_FN(armEmitQADD);
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ARM_MORPH_FN(armEmitQSUB);
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ARM_MORPH_FN(armEmitQDADD);
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ARM_MORPH_FN(armEmitQDSUB);
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// DSP multiply instructions
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ARM_MORPH_FN(armEmitSMLABB);
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ARM_MORPH_FN(armEmitSMLABT);
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ARM_MORPH_FN(armEmitSMLATB);
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ARM_MORPH_FN(armEmitSMLATT);
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ARM_MORPH_FN(armEmitSMLALBB);
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ARM_MORPH_FN(armEmitSMLALBT);
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ARM_MORPH_FN(armEmitSMLALTB);
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ARM_MORPH_FN(armEmitSMLALTT);
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ARM_MORPH_FN(armEmitSMLAWB);
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ARM_MORPH_FN(armEmitSMLAWT);
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ARM_MORPH_FN(armEmitSMULBB);
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ARM_MORPH_FN(armEmitSMULBT);
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ARM_MORPH_FN(armEmitSMULTB);
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ARM_MORPH_FN(armEmitSMULTT);
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ARM_MORPH_FN(armEmitSMULWB);
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ARM_MORPH_FN(armEmitSMULWT);
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// hint instructions
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ARM_MORPH_FN(armEmitNOP);
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ARM_MORPH_FN(armEmitWFE);
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ARM_MORPH_FN(armEmitWFI);
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ARM_MORPH_FN(armEmitSEV);
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// move instructions
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ARM_MORPH_FN(armEmitMOVW);
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ARM_MORPH_FN(armEmitMOVT);
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// multiply instructions
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ARM_MORPH_FN(armEmitMAAL);
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// synchronization instructions
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ARM_MORPH_FN(armEmitLDREX);
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ARM_MORPH_FN(armEmitSTREX);
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ARM_MORPH_FN(armEmitCLREX);
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// miscellaneous instructions
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ARM_MORPH_FN(armEmitCPS);
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// branch instructions
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ARM_MORPH_FN(armEmitCBZ);
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ARM_MORPH_FN(armEmitTB);
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// basic media instructions
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ARM_MORPH_FN(armEmitUSAD8);
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ARM_MORPH_FN(armEmitUSADA8);
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ARM_MORPH_FN(armEmitSBFX);
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ARM_MORPH_FN(armEmitBFC);
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ARM_MORPH_FN(armEmitBFI);
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ARM_MORPH_FN(armEmitUBFX);
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// parallel add/subtract instructions
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ARM_MORPH_FN(armEmitParallelBinop8);
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ARM_MORPH_FN(armEmitParallelBinop16);
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// packing, unpacking, saturation and reversal instructions
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ARM_MORPH_FN(armEmitPKHBT);
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ARM_MORPH_FN(armEmitPKHTB);
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ARM_MORPH_FN(armEmitSSAT);
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ARM_MORPH_FN(armEmitSSAT16);
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ARM_MORPH_FN(armEmitUSAT);
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ARM_MORPH_FN(armEmitUSAT16);
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ARM_MORPH_FN(armEmitSXTAB);
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ARM_MORPH_FN(armEmitUXTAB);
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ARM_MORPH_FN(armEmitSXTAB16);
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ARM_MORPH_FN(armEmitUXTAB16);
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ARM_MORPH_FN(armEmitSXTAH);
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ARM_MORPH_FN(armEmitUXTAH);
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ARM_MORPH_FN(armEmitSXTB);
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ARM_MORPH_FN(armEmitUXTB);
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ARM_MORPH_FN(armEmitSXTB16);
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ARM_MORPH_FN(armEmitUXTB16);
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ARM_MORPH_FN(armEmitSXTH);
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ARM_MORPH_FN(armEmitUXTH);
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ARM_MORPH_FN(armEmitSEL);
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ARM_MORPH_FN(armEmitREV);
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ARM_MORPH_FN(armEmitREV16);
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ARM_MORPH_FN(armEmitRBIT);
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ARM_MORPH_FN(armEmitREVSH);
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// signed multiply instructions
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ARM_MORPH_FN(armEmitSMLXD);
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ARM_MORPH_FN(armEmitSMUXD);
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ARM_MORPH_FN(armEmitSMLXLD);
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ARM_MORPH_FN(armEmitSMMLX);
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// VFP data processing instructions
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ARM_MORPH_FN(armEmitVFPUnop);
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ARM_MORPH_FN(armEmitVFPBinop);
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ARM_MORPH_FN(armEmitVMulAcc_VFP);
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ARM_MORPH_FN(armEmitVFusedMAC);
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ARM_MORPH_FN(armEmitVMOVI_VFP);
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ARM_MORPH_FN(armEmitVMOVR_VFP);
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ARM_MORPH_FN(armEmitVABS_VFP);
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ARM_MORPH_FN(armEmitVNEG_VFP);
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ARM_MORPH_FN(armEmitVCMP_VFP);
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ARM_MORPH_FN(armEmitVCMP0_VFP);
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ARM_MORPH_FN(armEmitVCVT_SD_VFP);
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ARM_MORPH_FN(armEmitVCVT_SH_VFP);
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ARM_MORPH_FN(armEmitVCVT_HS_VFP);
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ARM_MORPH_FN(armEmitVCVT_XF_VFP);
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ARM_MORPH_FN(armEmitVCVT_FX_VFP);
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ARM_MORPH_FN(armEmitVCVT_IF_VFP);
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ARM_MORPH_FN(armEmitVCVT_FI_VFP);
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// VFP Extension register load/store instructions
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ARM_MORPH_FN(armEmitVLDR);
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ARM_MORPH_FN(armEmitVSTR);
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ARM_MORPH_FN(armEmitVLDM);
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ARM_MORPH_FN(armEmitVSTM);
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// VFP 8, 16 and 32-bit transfer instructions
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ARM_MORPH_FN(armEmitVMRS);
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ARM_MORPH_FN(armEmitVMSR);
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ARM_MORPH_FN(armEmitVMOVRS);
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ARM_MORPH_FN(armEmitVMOVSR);
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ARM_MORPH_FN(armEmitVMOVRZ);
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ARM_MORPH_FN(armEmitVMOVZR);
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ARM_MORPH_FN(armEmitVDUPR);
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// VFP 64-bit transfer instructions
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ARM_MORPH_FN(armEmitVMOVRRD);
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ARM_MORPH_FN(armEmitVMOVDRR);
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ARM_MORPH_FN(armEmitVMOVRRSS);
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ARM_MORPH_FN(armEmitVMOVSSRR);
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//
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// If the register index specifies a banked register, return a vmiReg structure
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// for the banked register; otherwise, return VMI_NOREG. Also, validate the
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// current block mode for banked registers.
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//
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vmiReg armGetBankedRegMode(Bool useSPProcess, Uns32 r);
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#endif
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