Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/ovp/armmModel/armMessage.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
+ *
+ * YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
+ * UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
+ * TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
+ * IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
+ * PARTY PATENTS.
+ *
+ * THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
+ * MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
+ * A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
+ * FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
+ * YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
+ * PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
+ * AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
+ * MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
+ *
+ * Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+ * either express or implied.
+ *
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef ARM_MESSAGE_H
+#define ARM_MESSAGE_H
+
+// VMI header files
+#include "vmi/vmiRt.h"
+
+// model header files
+#include "armFunctions.h"
+
+//
+// Macros for emission of source references
+//
+#define SRCREF_FMT  "CPU '%s' 0x%08x %s: "
+#define SRCREF_ARGS(_A, _PC) \
+    vmirtProcessorName((vmiProcessorP)(_A)),    \
+    _PC,                                        \
+    armDisassemble((vmiProcessorP)(_A), _PC)
+
+#endif