Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
540
simulators/ovp/armmModel/armEmit.h
Normal file
540
simulators/ovp/armmModel/armEmit.h
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@ -0,0 +1,540 @@
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/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_EMIT_H
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#define ARM_EMIT_H
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// VMI header files
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#include "vmi/vmiTypes.h"
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// model header files
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#include "armMode.h"
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#include "armTypeRefs.h"
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////////////////////////////////////////////////////////////////////////////////
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// INTERWORKING
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////////////////////////////////////////////////////////////////////////////////
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//
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// Emit code to interwork if required, depending on LSB of target address
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//
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void armEmitInterworkLSB(armMorphStateP state, vmiReg ra);
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////////////////////////////////////////////////////////////////////////////////
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// INTEGER OPCODES
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////////////////////////////////////////////////////////////////////////////////
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//
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// rd = simPC (true)
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//
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void armEmitGetTruePC(armMorphStateP state, vmiReg rd);
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//
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// r15 = simPC (accoring to ARM pipeline)
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//
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void armEmitGetPC(armMorphStateP state);
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//
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// rd = c
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//
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void armEmitMoveRC(
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armMorphStateP state,
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Uns32 bits,
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vmiReg rd,
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Uns64 c
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);
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//
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// rd = ra
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//
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void armEmitMoveRR(
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armMorphStateP state,
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Uns32 bits,
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vmiReg rd,
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vmiReg ra
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);
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//
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// rd<destBits> = ra<srcBits>
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//
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void armEmitMoveExtendRR(
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armMorphStateP state,
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Uns32 destBits,
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vmiReg rd,
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Uns32 srcBits,
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vmiReg ra,
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Bool signExtend
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);
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//
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// rd = (flag==select1) ? c1 : c2
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//
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void armEmitCondMoveRCC(
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armMorphStateP state,
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Uns32 bits,
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vmiReg flag,
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Bool select1,
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vmiReg rd,
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Uns64 c1,
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Uns64 c2
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);
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//
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// rd = <unop> ra
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//
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void armEmitUnopRR(
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armMorphStateP state,
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Uns32 bits,
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vmiUnop op,
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vmiReg rd,
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vmiReg ra,
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vmiFlagsCP flags
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);
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//
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// rd = <unop> c
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//
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void armEmitUnopRC(
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armMorphStateP state,
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Uns32 bits,
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vmiUnop op,
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vmiReg rd,
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Uns64 c,
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vmiFlagsCP flags
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);
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//
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// rd = rd <binop> ra
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//
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void armEmitBinopRR(
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armMorphStateP state,
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Uns32 bits,
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vmiBinop op,
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vmiReg rd,
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vmiReg ra,
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vmiFlagsCP flags
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);
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//
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// rd = rd <binop> c
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//
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void armEmitBinopRC(
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armMorphStateP state,
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Uns32 bits,
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vmiBinop op,
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vmiReg rd,
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Uns64 c,
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vmiFlagsCP flags
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);
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//
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// rd = ra <binop> rb
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//
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void armEmitBinopRRR(
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armMorphStateP state,
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Uns32 bits,
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vmiBinop op,
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vmiReg rd,
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vmiReg ra,
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vmiReg rb,
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vmiFlagsCP flags
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);
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//
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// rd = ra <binop> c
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//
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void armEmitBinopRRC(
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armMorphStateP state,
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Uns32 bits,
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vmiBinop op,
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vmiReg rd,
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vmiReg ra,
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Uns64 c,
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vmiFlagsCP flags
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);
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//
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// Generate shift mask prefix (sets mask to 255)
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//
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void armEmitSetShiftMask(void);
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//
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// rdh:rdl = ra*rb
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//
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void armEmitMulopRRR(
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armMorphStateP state,
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Uns32 bits,
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vmiBinop op,
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vmiReg rdh,
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vmiReg rdl,
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vmiReg ra,
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vmiReg rb,
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vmiFlagsCP flags
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);
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////////////////////////////////////////////////////////////////////////////////
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// FLOATING POINT OPCODES
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////////////////////////////////////////////////////////////////////////////////
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//
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// fd = fa <fp ternnop> fb fc
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//
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void armEmitFTernopSimdRRRR(
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armMorphStateP state,
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vmiFType type,
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Uns32 num,
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vmiFTernop op,
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vmiReg fd,
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vmiReg fa,
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vmiReg fb,
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vmiReg fc,
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Bool roundInt
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);
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//
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// fd = fa <binop> fb
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//
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void armEmitFBinopSimdRRR(
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armMorphStateP state,
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vmiFType type,
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Uns32 num,
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vmiFBinop op,
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vmiReg fd,
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vmiReg fa,
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vmiReg fb
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);
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//
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// fd = <unop> fa
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//
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void armEmitFUnopSimdRR(
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armMorphStateP state,
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vmiFType type,
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Uns32 num,
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vmiFUnop op,
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vmiReg fd,
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vmiReg fa
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);
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//
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// fd = <fp convert> fa
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//
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void armEmitFConvertRR(
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armMorphStateP state,
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vmiFType destType,
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vmiReg fd,
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vmiFType srcType,
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vmiReg fa,
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vmiFPRC round
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);
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//
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// compare fa to fb, setting relation and flags
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//
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void armEmitFCompareRR(
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armMorphStateP state,
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vmiFType type,
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vmiReg relation,
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vmiReg fa,
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vmiReg fb,
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Bool allowQNaN,
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Bool setSticky
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);
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////////////////////////////////////////////////////////////////////////////////
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// LOAD AND STORE OPCODES
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////////////////////////////////////////////////////////////////////////////////
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//
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// mem[ra+offset] = rb (when ra!=VMI_NOREG)
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// mem[offset] = rb (when ra==VMI_NOREG)
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//
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void armEmitStoreRRO(
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armMorphStateP state,
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Uns32 bits,
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Uns32 offset,
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vmiReg ra,
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vmiReg rb
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);
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//
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// mem[ra+offset] = rbH:rbL (when ra!=VMI_NOREG)
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// mem[offset] = rbH:rbL (when ra==VMI_NOREG)
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//
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void armEmitStoreRRRO(
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armMorphStateP state,
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Uns32 bits,
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Uns32 offset,
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vmiReg ra,
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vmiReg rbL,
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vmiReg rbH
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);
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//
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// rd = mem[ra+offset] (when ra!=VMI_NOREG)
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// rd = mem[offset] (when ra==VMI_NOREG)
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//
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void armEmitLoadRRO(
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armMorphStateP state,
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Uns32 bits,
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Uns32 offset,
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vmiReg rd,
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vmiReg ra,
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Bool signExtend,
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Bool isReturn
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);
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//
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// rdH:rdL = mem[ra+offset] (when ra!=VMI_NOREG)
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// rdH:rdL = mem[offset] (when ra==VMI_NOREG)
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//
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void armEmitLoadRRRO(
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armMorphStateP state,
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Uns32 bits,
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Uns32 offset,
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vmiReg rdL,
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vmiReg rdH,
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vmiReg ra,
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vmiReg rt,
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Bool signExtend,
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Bool isReturn
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);
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//
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// trystore mem[ra+offset] (when ra!=VMI_NOREG)
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// trystore mem[offset] (when ra==VMI_NOREG)
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//
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void armEmitTryStoreRC(
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armMorphStateP state,
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Uns32 bits,
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Addr offset,
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vmiReg ra
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);
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////////////////////////////////////////////////////////////////////////////////
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// COMPARE OPERATIONS
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////////////////////////////////////////////////////////////////////////////////
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//
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// flag = ra <cond> rb
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//
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void armEmitCompareRR(
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armMorphStateP state,
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Uns32 bits,
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vmiCondition cond,
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vmiReg ra,
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vmiReg rb,
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vmiReg flag
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);
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//
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// flag = ra <cond> c
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//
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void armEmitCompareRC(
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armMorphStateP state,
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Uns32 bits,
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vmiCondition cond,
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vmiReg ra,
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Uns64 c,
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vmiReg flag
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);
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////////////////////////////////////////////////////////////////////////////////
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// INTER-INSTRUCTION CONDITIONAL AND UNCONDITIONAL JUMPS
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////////////////////////////////////////////////////////////////////////////////
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//
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// Structure holding information about a jump
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//
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typedef struct armJumpInfoS {
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vmiReg linkReg; // link register
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vmiJumpHint hint; // call hint
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Uns32 linkPC; // address to put in link register
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} armJumpInfo, *armJumpInfoP;
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//
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// Perform an unconditional direct jump.
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//
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void armEmitUncondJump(
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armMorphStateP state,
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armJumpInfoP ji
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);
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//
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// Perform an unconditional indirect jump.
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//
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void armEmitUncondJumpReg(
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armMorphStateP state,
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armJumpInfoP ji,
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vmiReg toReg
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);
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//
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// Perform a conditional direct jump if the condition flag is non-zero
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// (jumpIfTrue) or zero (not jumpIfTrue).
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//
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void armEmitCondJump(
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armMorphStateP state,
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armJumpInfoP ji,
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vmiReg flag,
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Bool jumpIfTrue
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);
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//
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// Perform an implicit unconditional direct jump if required
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//
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void armEmitImplicitUncondJump(armMorphStateP state);
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////////////////////////////////////////////////////////////////////////////////
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// INTRA-INSTRUCTION CONDITIONAL AND UNCONDITIONAL JUMPS
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////////////////////////////////////////////////////////////////////////////////
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//
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// Create and return a new label.
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//
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vmiLabelP armEmitNewLabel(void);
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//
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// Insert a label previously created by vmimtNewLabel at the current location.
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//
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void armEmitInsertLabel(vmiLabelP label);
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//
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// Perform an unconditional jump to the passed local label.
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//
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void armEmitUncondJumpLabel(vmiLabelP toLabel);
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//
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// Perform a conditional jump if the condition flag is non-zero (jumpIfTrue)
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// or zero (not jumpIfTrue). The target location is the passed local label.
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//
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void armEmitCondJumpLabel(vmiReg flag, Bool jumpIfTrue, vmiLabelP toLabel);
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//
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// Test the register value by performing bitwise AND with the passed constant
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// value, and jump to 'toLabel' if condition 'cond' is satisfied.
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//
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void armEmitTestRCJumpLabel(
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Uns32 bits,
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vmiCondition cond,
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vmiReg r,
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Uns64 c,
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vmiLabelP toLabel
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);
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//
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// Compare the register value by performing subtraction of the passed constant
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// value, and jump to 'toLabel' if condition 'cond' is satisfied.
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//
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void armEmitCompareRCJumpLabel(
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Uns32 bits,
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vmiCondition cond,
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vmiReg r,
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Uns64 c,
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vmiLabelP toLabel
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);
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////////////////////////////////////////////////////////////////////////////////
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//// CALLBACK FUNCTION INTERFACE
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////////////////////////////////////////////////////////////////////////////////
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//
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// Add processor argument to the stack frame
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//
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void armEmitArgProcessor(armMorphStateP state);
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//
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// Add Uns32 argument to the stack frame
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//
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void armEmitArgUns32(armMorphStateP state, Uns32 arg);
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//
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// Add register argument to the stack frame
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//
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void armEmitArgReg(armMorphStateP state, Uns32 bits, vmiReg r);
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//
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// Add program counter argument to the stack frame
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//
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void armEmitArgSimPC(armMorphStateP state, Uns32 bits);
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//
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// Make a call with all current stack frame arguments
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//
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void armEmitCall(armMorphStateP state, vmiCallFn arg);
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//
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// As above but generate a function result (placed in rd)
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//
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void armEmitCallResult(
|
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armMorphStateP state,
|
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vmiCallFn arg,
|
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Uns32 bits,
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vmiReg rd
|
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);
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////////////////////////////////////////////////////////////////////////////////
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// SIMULATOR CONTROL
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||||
////////////////////////////////////////////////////////////////////////////////
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//
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// Stop simulation of the current processor
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//
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void armEmitExit(void);
|
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|
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//
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// Emit code to wait for the passed reason
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//
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void armEmitWait(armMorphStateP state, armDisable reason);
|
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//
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// Terminate the current block
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//
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void armEmitEndBlock(void);
|
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//
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// Emit code to validate the current block mode
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//
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void armEmitValidateBlockMask(armBlockMask blockMask);
|
||||
|
||||
#endif
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Block a user