Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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adrian
146
simulators/ovp/armmModel/armConfig.h
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146
simulators/ovp/armmModel/armConfig.h
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/*
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* Copyright (c) 2005-2011 Imperas Software Ltd., www.imperas.com
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*
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* YOUR ACCESS TO THE INFORMATION IN THIS MODEL IS CONDITIONAL
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* UPON YOUR ACCEPTANCE THAT YOU WILL NOT USE OR PERMIT OTHERS
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* TO USE THE INFORMATION FOR THE PURPOSES OF DETERMINING WHETHER
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* IMPLEMENTATIONS OF THE ARM ARCHITECTURE INFRINGE ANY THIRD
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* PARTY PATENTS.
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*
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* THE LICENSE BELOW EXTENDS ONLY TO USE OF THE SOFTWARE FOR
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* MODELING PURPOSES AND SHALL NOT BE CONSTRUED AS GRANTING
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* A LICENSE TO CREATE A HARDWARE IMPLEMENTATION OF THE
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* FUNCTIONALITY OF THE SOFTWARE LICENSED HEREUNDER.
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* YOU MAY USE THE SOFTWARE SUBJECT TO THE LICENSE TERMS BELOW
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* PROVIDED THAT YOU ENSURE THAT THIS NOTICE IS REPLICATED UNMODIFIED
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* AND IN ITS ENTIRETY IN ALL DISTRIBUTIONS OF THE SOFTWARE,
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* MODIFIED OR UNMODIFIED, IN SOURCE CODE OR IN BINARY FORM.
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*
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* Licensed under an Imperas Modfied Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.ovpworld.org/licenses/OVP_MODIFIED_1.0_APACHE_OPEN_SOURCE_LICENSE_2.0.pdf
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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* either express or implied.
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*
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef ARM_CONFIG_H
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#define ARM_CONFIG_H
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// basic number types
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#include "hostapi/impTypes.h"
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// model header files
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#include "armSysRegisters.h"
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#include "armTypeRefs.h"
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#include "armVariant.h"
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//
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// Use this to define a write mask entry in the structure below
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//
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#define SCS_MASK_DECL(_N) union { \
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Uns32 value32; \
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SCS_REG_STRUCT_DECL(_N) fields; \
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} _N
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//
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// This structure hold configuration information about an ARM variant
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//
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typedef struct armConfigS {
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// name of configuration
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const char *name;
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// configuration not held in system registers
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armArchitecture arch :16; // specific ISA supported
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Uns32 numInterrupts :16; // number of external interrupt lines
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Uns32 ERG : 4; // exclusives reservation granule
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Bool rotateUnaligned: 1; // rotate unaligned LDR/LDRT/SWP?
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Bool align64as32 : 1; // align 64-bit load/store on 32-bit
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Bool STRoffsetPC12 : 1; // STR/STM store PC with offset 12?
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Uns32 priorityBitsM1 : 3; // number of priority bits, minus 1
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// default values for system registers
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struct {
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SCS_REG_DECL(ICTR);
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SCS_REG_DECL(ACTLR);
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SCS_REG_DECL(CPUID);
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SCS_REG_DECL(CPACR);
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SCS_REG_DECL(SYST_CALIB);
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SCS_REG_DECL(ID_PFR0);
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SCS_REG_DECL(ID_PFR1);
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SCS_REG_DECL(ID_DFR0);
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SCS_REG_DECL(ID_AFR0);
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SCS_REG_DECL(ID_MMFR0);
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SCS_REG_DECL(ID_MMFR1);
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SCS_REG_DECL(ID_MMFR2);
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SCS_REG_DECL(ID_MMFR3);
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SCS_REG_DECL(ID_ISAR0);
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SCS_REG_DECL(ID_ISAR1);
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SCS_REG_DECL(ID_ISAR2);
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SCS_REG_DECL(ID_ISAR3);
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SCS_REG_DECL(ID_ISAR4);
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SCS_REG_DECL(ID_ISAR5);
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SCS_REG_DECL(MVFR0);
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SCS_REG_DECL(MVFR1);
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SCS_REG_DECL(MPU_TYPE);
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} regDefaults;
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// write masks for system registers
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struct {
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SCS_MASK_DECL(CPACR);
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} regMasks;
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} armConfig;
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DEFINE_CS(armConfig);
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//
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// This specifies configuration information for each supported variant
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//
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extern const struct armConfigS armConfigTable[];
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//
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// Predicates for system features
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//
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// is MPU enabled?
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#define MPU_ENABLED(_A) SCS_FIELD(_A, MPU_CONTROL, ENABLE)
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// is MPU unified?
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#define MPU_UNIFIED(_A) (!SCS_FIELD(_A, MPU_TYPE, SEPARATE))
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// is MPU present?
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#define MPU_PRESENT(_A) SCS_FIELD(_A, MPU_TYPE, DREGION)
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#define MPUS_PRESENT(_A) (MPU_PRESENT(_A) && !MPU_UNIFIED(_A))
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// is alignment checking enabled?
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#define ALIGN_ENABLED(_A) SCS_FIELD(_A, CCR, UNALIGN_TRP)
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#define DO_UNALIGNED(_A) !ALIGN_ENABLED(_A)
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// is Jazelle present?
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#define JAZELLE_PRESENT(_A) ARM_SUPPORT((_A)->configInfo.arch, ARM_J)
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// get number of priority bits supported
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#define PRIORITY_BITS(_A) ((_A)->configInfo.priorityBitsM1+1)
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// get number of interrupt lines
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#define NUM_INTERRUPTS(_A) ((_A)->configInfo.numInterrupts)
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// is FPU present?
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#define FPU_PRESENT(_A) SCS_FIELD((_A), MVFR0, A_SIMD_Registers)
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// is DSP present?
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#define DSP_PRESENT(_A) (SCS_FIELD((_A), ID_ISAR3, SIMD_instrs)>2)
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#endif
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