Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
552
simulators/bochs/cpu/shift64.cc
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552
simulators/bochs/cpu/shift64.cc
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@ -0,0 +1,552 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001-2010 The Bochs Project
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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||||
// Lesser General Public License for more details.
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//
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||||
// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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#if BX_SUPPORT_X86_64
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->b1() == 0xa4) // 0x1a4
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count = i->Ib();
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else // 0x1a5
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count = CL;
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count &= 0x3f; // use only 6 LSB's
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if (!count) return;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
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write_RMW_virtual_qword(result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHLD_EqGqR(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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if (i->b1() == 0xa4) // 0x1a4
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count = i->Ib();
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else // 0x1a5
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count = CL;
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count &= 0x3f; // use only 6 LSB's
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if (!count) return;
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op1_64 = BX_READ_64BIT_REG(i->rm());
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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result_64 = (op1_64 << count) | (op2_64 >> (64 - count));
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqM(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->b1() == 0xac) // 0x1ac
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count = i->Ib();
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else // 0x1ad
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count = CL;
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count &= 0x3f; // use only 6 LSB's
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if (!count) return;
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
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write_RMW_virtual_qword(result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHRD_EqGqR(bxInstruction_c *i)
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{
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Bit64u op1_64, op2_64, result_64;
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unsigned count;
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unsigned cf, of;
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if (i->b1() == 0xac) // 0x1ac
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count = i->Ib();
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else // 0x1ad
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count = CL;
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count &= 0x3f; // use only 6 LSB's
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if (!count) return;
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op1_64 = BX_READ_64BIT_REG(i->rm());
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op2_64 = BX_READ_64BIT_REG(i->nnn());
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result_64 = (op2_64 << (64 - count)) | (op1_64 >> count);
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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SET_FLAGS_OSZAPC_LOGIC_64(result_64);
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cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63; // of = result62 ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EqM(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned bit0, bit63;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->b1() == 0xd3)
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count = CL;
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else // 0xc1 or 0xd1
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count = i->Ib();
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count &= 0x3f;
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if (! count) return;
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result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
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write_RMW_virtual_qword(result_64);
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bit0 = (result_64 & 0x1);
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bit63 = (result_64 >> 63);
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// of = cf ^ result63
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SET_FLAGS_OxxxxC(bit0 ^ bit63, bit0);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROL_EqR(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned bit0, bit63;
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if (i->b1() == 0xd3)
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count = CL;
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else // 0xc1 or 0xd1
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count = i->Ib();
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count &= 0x3f;
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if (! count) return;
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op1_64 = BX_READ_64BIT_REG(i->rm());
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result_64 = (op1_64 << count) | (op1_64 >> (64 - count));
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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bit0 = (result_64 & 0x1);
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bit63 = (result_64 >> 63);
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// of = cf ^ result63
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SET_FLAGS_OxxxxC(bit0 ^ bit63, bit0);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EqM(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned bit62, bit63;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->b1() == 0xd3)
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count = CL;
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else // 0xc1 or 0xd1
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count = i->Ib();
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count &= 0x3f;
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if (! count) return;
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result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
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write_RMW_virtual_qword(result_64);
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bit63 = (result_64 >> 63) & 1;
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bit62 = (result_64 >> 62) & 1;
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// of = result62 ^ result63
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SET_FLAGS_OxxxxC(bit62 ^ bit63, bit63);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::ROR_EqR(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned bit62, bit63;
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if (i->b1() == 0xd3)
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count = CL;
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else // 0xc1 or 0xd1
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count = i->Ib();
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count &= 0x3f;
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if (! count) return;
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op1_64 = BX_READ_64BIT_REG(i->rm());
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result_64 = (op1_64 >> count) | (op1_64 << (64 - count));
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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bit63 = (result_64 >> 63) & 1;
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bit62 = (result_64 >> 62) & 1;
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// of = result62 ^ result63
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SET_FLAGS_OxxxxC(bit62 ^ bit63, bit63);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EqM(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned cf, of;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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if (i->b1() == 0xd3)
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count = CL;
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else // 0xc1 or 0xd1
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count = i->Ib();
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count &= 0x3f;
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if (!count) return;
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if (count==1) {
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result_64 = (op1_64 << 1) | getB_CF();
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}
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else {
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result_64 = (op1_64 << count) | (getB_CF() << (count - 1)) |
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(op1_64 >> (65 - count));
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}
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write_RMW_virtual_qword(result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCL_EqR(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned cf, of;
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if (i->b1() == 0xd3)
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count = CL;
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else // 0xc1 or 0xd1
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count = i->Ib();
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count &= 0x3f;
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if (!count) return;
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op1_64 = BX_READ_64BIT_REG(i->rm());
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if (count==1) {
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result_64 = (op1_64 << 1) | getB_CF();
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}
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else {
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result_64 = (op1_64 << count) | (getB_CF() << (count - 1)) |
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(op1_64 >> (65 - count));
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}
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BX_WRITE_64BIT_REG(i->rm(), result_64);
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cf = (op1_64 >> (64 - count)) & 0x1;
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of = cf ^ (result_64 >> 63); // of = cf ^ result63
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SET_FLAGS_OxxxxC(of, cf);
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}
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EqM(bxInstruction_c *i)
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{
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Bit64u op1_64, result_64;
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unsigned count;
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unsigned of, cf;
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bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
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/* pointer, segment address pair */
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op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
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|
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if (i->b1() == 0xd3)
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count = CL;
|
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else // 0xc1 or 0xd1
|
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count = i->Ib();
|
||||
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||||
count &= 0x3f;
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if (!count) return;
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||||
|
||||
if (count==1) {
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result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
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||||
}
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else {
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result_64 = (op1_64 >> count) | (getB_CF() << (64 - count)) |
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(op1_64 << (65 - count));
|
||||
}
|
||||
|
||||
write_RMW_virtual_qword(result_64);
|
||||
|
||||
cf = (op1_64 >> (count - 1)) & 0x1;
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of = ((result_64 << 1) ^ result_64) >> 63;
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SET_FLAGS_OxxxxC(of, cf);
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}
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||||
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void BX_CPP_AttrRegparmN(1) BX_CPU_C::RCR_EqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
unsigned of, cf;
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
|
||||
if (count==1) {
|
||||
result_64 = (op1_64 >> 1) | (((Bit64u) getB_CF()) << 63);
|
||||
}
|
||||
else {
|
||||
result_64 = (op1_64 >> count) | (getB_CF() << (64 - count)) |
|
||||
(op1_64 << (65 - count));
|
||||
}
|
||||
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
|
||||
cf = (op1_64 >> (count - 1)) & 0x1;
|
||||
of = ((result_64 << 1) ^ result_64) >> 63;
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
/* count < 64, since only lower 6 bits used */
|
||||
result_64 = (op1_64 << count);
|
||||
cf = (op1_64 >> (64 - count)) & 0x1;
|
||||
of = cf ^ (result_64 >> 63);
|
||||
|
||||
write_RMW_virtual_qword(result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHL_EqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
/* count < 64, since only lower 6 bits used */
|
||||
result_64 = (op1_64 << count);
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
|
||||
cf = (op1_64 >> (64 - count)) & 0x1;
|
||||
of = cf ^ (result_64 >> 63);
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
result_64 = (op1_64 >> count);
|
||||
|
||||
write_RMW_virtual_qword(result_64);
|
||||
|
||||
cf = (op1_64 >> (count - 1)) & 0x1;
|
||||
// note, that of == result63 if count == 1 and
|
||||
// of == 0 if count >= 2
|
||||
of = ((result_64 << 1) ^ result_64) >> 63;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SHR_EqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
unsigned cf, of;
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
result_64 = (op1_64 >> count);
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
|
||||
cf = (op1_64 >> (count - 1)) & 0x1;
|
||||
// note, that of == result63 if count == 1 and
|
||||
// of == 0 if count >= 2
|
||||
of = ((result_64 << 1) ^ result_64) >> 63;
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
||||
SET_FLAGS_OxxxxC(of, cf);
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqM(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
|
||||
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
||||
|
||||
/* pointer, segment address pair */
|
||||
op1_64 = read_RMW_virtual_qword_64(i->seg(), eaddr);
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
/* count < 64, since only lower 6 bits used */
|
||||
result_64 = ((Bit64s) op1_64) >> count;
|
||||
|
||||
write_RMW_virtual_qword(result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
||||
set_CF((op1_64 >> (count - 1)) & 1);
|
||||
clear_OF(); /* signed overflow cannot happen in SAR instruction */
|
||||
}
|
||||
|
||||
void BX_CPP_AttrRegparmN(1) BX_CPU_C::SAR_EqR(bxInstruction_c *i)
|
||||
{
|
||||
Bit64u op1_64, result_64;
|
||||
unsigned count;
|
||||
|
||||
if (i->b1() == 0xd3)
|
||||
count = CL;
|
||||
else // 0xc1 or 0xd1
|
||||
count = i->Ib();
|
||||
|
||||
count &= 0x3f;
|
||||
if (!count) return;
|
||||
|
||||
op1_64 = BX_READ_64BIT_REG(i->rm());
|
||||
|
||||
/* count < 64, since only lower 6 bits used */
|
||||
result_64 = ((Bit64s) op1_64) >> count;
|
||||
|
||||
BX_WRITE_64BIT_REG(i->rm(), result_64);
|
||||
|
||||
SET_FLAGS_OSZAPC_LOGIC_64(result_64);
|
||||
set_CF((op1_64 >> (count - 1)) & 1);
|
||||
clear_OF(); /* signed overflow cannot happen in SAR instruction */
|
||||
}
|
||||
|
||||
#endif /* if BX_SUPPORT_X86_64 */
|
||||
Reference in New Issue
Block a user