Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
269
simulators/bochs/cpu/icache.cc
Executable file
269
simulators/bochs/cpu/icache.cc
Executable file
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/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2007-2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#include "cpu.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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// Make code more tidy with a few macros.
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#if BX_SUPPORT_X86_64==0
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#define RIP EIP
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#endif
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bxPageWriteStampTable pageWriteStampTable;
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void flushICaches(void)
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{
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for (unsigned i=0; i<BX_SMP_PROCESSORS; i++) {
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BX_CPU(i)->iCache.flushICacheEntries();
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#if BX_SUPPORT_TRACE_CACHE
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BX_CPU(i)->async_event |= BX_ASYNC_EVENT_STOP_TRACE;
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#endif
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}
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pageWriteStampTable.resetWriteStamps();
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}
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void handleSMC(bx_phy_address pAddr, Bit32u mask)
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{
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for (unsigned i=0; i<BX_SMP_PROCESSORS; i++) {
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#if BX_SUPPORT_TRACE_CACHE
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BX_CPU(i)->async_event |= BX_ASYNC_EVENT_STOP_TRACE;
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#endif
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BX_CPU(i)->iCache.handleSMC(pAddr, mask);
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}
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}
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#if BX_SUPPORT_TRACE_CACHE
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void BX_CPU_C::serveICacheMiss(bxICacheEntry_c *entry, Bit32u eipBiased, bx_phy_address pAddr)
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{
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BX_CPU_THIS_PTR iCache.alloc_trace(entry);
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// Cache miss. We weren't so lucky, but let's be optimistic - try to build
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// trace from incoming instruction bytes stream !
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entry->pAddr = pAddr;
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entry->traceMask = 0;
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unsigned remainingInPage = BX_CPU_THIS_PTR eipPageWindowSize - eipBiased;
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const Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
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int ret;
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bxInstruction_c *i = entry->i;
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Bit32u pageOffset = PAGE_OFFSET((Bit32u) pAddr);
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Bit32u traceMask = 0;
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for (unsigned n=0;n<BX_MAX_TRACE_LENGTH;n++)
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{
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
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ret = fetchDecode64(fetchPtr, i, remainingInPage);
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else
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#endif
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ret = fetchDecode32(fetchPtr, i, remainingInPage);
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if (ret < 0) {
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// Fetching instruction on segment/page boundary
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if (n > 0) {
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// The trace is already valid, it has several instructions inside,
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// in this case just drop the boundary instruction and stop
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// tracing.
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break;
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}
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// First instruction is boundary fetch, leave the trace cache entry
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// invalid for now because boundaryFetch() can fault
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entry->pAddr = ~entry->pAddr;
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entry->tlen = 1;
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boundaryFetch(fetchPtr, remainingInPage, i);
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// Add the instruction to trace cache
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entry->pAddr = ~entry->pAddr;
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entry->traceMask = 0x80000000; /* last line in page */
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pageWriteStampTable.markICacheMask(entry->pAddr, entry->traceMask);
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pageWriteStampTable.markICacheMask(BX_CPU_THIS_PTR pAddrPage, 0x1);
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BX_CPU_THIS_PTR iCache.commit_page_split_trace(BX_CPU_THIS_PTR pAddrPage, entry);
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return;
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}
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// add instruction to the trace
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unsigned iLen = i->ilen();
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entry->tlen++;
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BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, iLen,
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, long64_mode());
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traceMask |= 1 << (pageOffset >> 7);
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traceMask |= 1 << ((pageOffset + iLen - 1) >> 7);
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// continue to the next instruction
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remainingInPage -= iLen;
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if (ret != 0 /* stop trace indication */ || remainingInPage == 0) break;
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pAddr += iLen;
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pageOffset += iLen;
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fetchPtr += iLen;
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i++;
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// try to find a trace starting from current pAddr and merge
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if (remainingInPage >= 15) // avoid merging with page split trace
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if (mergeTraces(entry, i, pAddr)) break;
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}
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//BX_INFO(("commit trace %08x len=%d mask %08x", (Bit32u) entry->pAddr, entry->tlen, pageWriteStampTable.getFineGranularityMapping(entry->pAddr)));
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entry->traceMask |= traceMask;
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pageWriteStampTable.markICacheMask(pAddr, entry->traceMask);
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BX_CPU_THIS_PTR iCache.commit_trace(entry->tlen);
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}
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bx_bool BX_CPU_C::mergeTraces(bxICacheEntry_c *entry, bxInstruction_c *i, bx_phy_address pAddr)
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{
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bxICacheEntry_c *e = BX_CPU_THIS_PTR iCache.get_entry(pAddr, BX_CPU_THIS_PTR fetchModeMask);
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if (e->pAddr == pAddr)
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{
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// determine max amount of instruction to take from another entry
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unsigned max_length = e->tlen;
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if (max_length + entry->tlen > BX_MAX_TRACE_LENGTH)
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max_length = BX_MAX_TRACE_LENGTH - entry->tlen;
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if(max_length == 0) return 0;
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memcpy(i, e->i, sizeof(bxInstruction_c)*max_length);
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entry->tlen += max_length;
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BX_ASSERT(entry->tlen <= BX_MAX_TRACE_LENGTH);
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entry->traceMask |= e->traceMask;
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return 1;
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}
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return 0;
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}
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#else // BX_SUPPORT_TRACE_CACHE == 0
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bx_bool BX_CPU_C::fetchInstruction(bxInstruction_c *iStorage, Bit32u eipBiased)
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{
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unsigned remainingInPage = BX_CPU_THIS_PTR eipPageWindowSize - eipBiased;
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const Bit8u *fetchPtr = BX_CPU_THIS_PTR eipFetchPtr + eipBiased;
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int ret;
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
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ret = fetchDecode64(fetchPtr, iStorage, remainingInPage);
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else
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#endif
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ret = fetchDecode32(fetchPtr, iStorage, remainingInPage);
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if (ret < 0) {
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// handle instrumentation callback inside boundaryFetch
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boundaryFetch(fetchPtr, remainingInPage, iStorage);
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return 0;
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}
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#if BX_INSTRUMENTATION
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BX_INSTR_OPCODE(BX_CPU_ID, fetchPtr, iStorage->ilen(),
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, long64_mode());
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#endif
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return 1;
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}
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void BX_CPU_C::serveICacheMiss(bxICacheEntry_c *entry, Bit32u eipBiased, bx_phy_address pAddr)
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{
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// The entry will be marked valid if fetchdecode will succeed
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if (fetchInstruction(entry->i, eipBiased)) {
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entry->pAddr = pAddr;
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pageWriteStampTable.markICache(pAddr, entry->i->ilen());
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}
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else {
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entry->pAddr = BX_ICACHE_INVALID_PHY_ADDRESS;
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}
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}
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#endif
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void BX_CPU_C::boundaryFetch(const Bit8u *fetchPtr, unsigned remainingInPage, bxInstruction_c *i)
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{
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unsigned j, k;
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Bit8u fetchBuffer[32];
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int ret;
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if (remainingInPage >= 15) {
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BX_ERROR(("boundaryFetch #GP(0): too many instruction prefixes"));
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exception(BX_GP_EXCEPTION, 0);
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}
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// Read all leftover bytes in current page up to boundary.
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for (j=0; j<remainingInPage; j++) {
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fetchBuffer[j] = *fetchPtr++;
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}
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// The 2nd chunk of the instruction is on the next page.
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// Set RIP to the 0th byte of the 2nd page, and force a
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// prefetch so direct access of that physical page is possible, and
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// all the associated info is updated.
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RIP += remainingInPage;
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prefetch();
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unsigned fetchBufferLimit = 15;
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if (BX_CPU_THIS_PTR eipPageWindowSize < 15) {
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BX_DEBUG(("boundaryFetch: small window size after prefetch=%d bytes, remainingInPage=%d bytes", BX_CPU_THIS_PTR eipPageWindowSize, remainingInPage));
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fetchBufferLimit = BX_CPU_THIS_PTR eipPageWindowSize;
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}
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// We can fetch straight from the 0th byte, which is eipFetchPtr;
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fetchPtr = BX_CPU_THIS_PTR eipFetchPtr;
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// read leftover bytes in next page
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for (k=0; k<fetchBufferLimit; k++, j++) {
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fetchBuffer[j] = *fetchPtr++;
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}
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#if BX_SUPPORT_X86_64
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
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ret = fetchDecode64(fetchBuffer, i, remainingInPage+fetchBufferLimit);
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else
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#endif
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ret = fetchDecode32(fetchBuffer, i, remainingInPage+fetchBufferLimit);
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if (ret < 0) {
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BX_INFO(("boundaryFetch #GP(0): failed to complete instruction decoding"));
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exception(BX_GP_EXCEPTION, 0);
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}
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// Restore EIP since we fudged it to start at the 2nd page boundary.
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RIP = BX_CPU_THIS_PTR prev_rip;
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// Since we cross an instruction boundary, note that we need a prefetch()
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// again on the next instruction. Perhaps we can optimize this to
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// eliminate the extra prefetch() since we do it above, but have to
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// think about repeated instructions, etc.
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// invalidate_prefetch_q();
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BX_INSTR_OPCODE(BX_CPU_ID, fetchBuffer, i->ilen(),
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b, long64_mode());
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}
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