Adding some code to the L4-Sys experiment, and making it compile again.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1385 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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unzner
230
src/experiments/l4-sys/aluinstr.hpp
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230
src/experiments/l4-sys/aluinstr.hpp
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#ifndef __L4SYS_ALUINSTR_HPP__
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#define __L4SYS_ALUINSTR_HPP__
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/**
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* Forward declaration of the Bochs instruction decode table.
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* This is necessary because, inconveniently, it is not declared in a header file.
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*/
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#include "cpu/fetchdecode.h"
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static const BxOpcodeInfo_t *BxOpcodeInfo32;
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/**
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* Trying to order X86 ALU instructions.
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* Each instruction class contains instructions
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* of roughly equal length and operands, so that
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* all the bxInstruction_c structures residing within
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* one class contain the same member fields.
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*/
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enum X86AluClass {
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ALU_UNDEF = 0,
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ALU_RM8,
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ALU_RM16,
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ALU_RM32,
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ALU_RM8_ONE,
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ALU_RM16_ONE,
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ALU_RM32_ONE,
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ALU_REG,
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ALU_IMM8_REG,
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ALU_IMM16_REG,
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ALU_IMM32_REG,
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ALU_IMM8_RM8,
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ALU_IMM8_RM16,
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ALU_IMM8_RM32,
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ALU_IMM16_RM16,
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ALU_IMM32_RM32,
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ALU_REG_RM8,
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ALU_REG_RM16,
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ALU_REG_RM32
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};
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/**
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* A struct describing a specific x86
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* ALU instruction in terms of Bochs.
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*/
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struct BochsALUInstr {
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/**
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* the Bochs operation ID (confusingly called ia_opcode
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* in bxInstruction_c), pointing to several bits of information,
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* for instance what simulator function to execute
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*/
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Bit16u bochs_operation;
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/**
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* the x86 opcode (known as b1 in bxInstruction_c)
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*/
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Bit8u opcode;
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/**
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* the reg part of the modr/m field (known as nnn in bxInstruction_c)
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* A value of 8 or higher marks this field unused.
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*/
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Bit8u reg;
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/**
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* the register offset of the instruction byte of this instruction
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* Some x86 instructions, like INC register, add a register offset
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* to their opcode. It is necessary to store this separately for
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* several reasons, one being the ability to separate
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* ALU input latch faults from ALU instruction latch faults.
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* A value of 8 or higher marks this field unused.
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*/
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Bit8u opcodeRegisterOffset;
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/**
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* the ALU class this instruction belongs to
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*/
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X86AluClass aluClass;
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};
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/**
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* Array containing most (all?) Bochs ALU commands.
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* Attention: here, \a reg and \a opcodeRegisterOffset, if less than 8,
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* define the maximum value possible in this field,
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* according to the Bochs instruction decoder function.
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* (see the BxOpcodeInfoG... arrays in cpu/fetchdecode.h)
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*/
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const BochsALUInstr aluInstructions [] = {
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// Now is a great time to open Volume 2 of Intel's IA-32 documentation.
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/* --- /// UNARY OPERATIONS \\\ --- */
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// 8-bit
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{ BX_IA_INC_Eb, 0xFE, 0, 8, ALU_RM8},
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{ BX_IA_DEC_Eb, 0xFE, 1, 8, ALU_RM8},
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{ BX_IA_NOT_Eb, 0xF6, 2, 8, ALU_RM8},
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{ BX_IA_NEG_Eb, 0xF6, 3, 8, ALU_RM8},
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// 16-bit
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{ BX_IA_INC_Ew, 0xFF, 0, 8, ALU_RM16},
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{ BX_IA_DEC_Ew, 0xFF, 1, 8, ALU_RM16},
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{ BX_IA_NOT_Ew, 0xF7, 2, 8, ALU_RM16},
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{ BX_IA_NEG_Ew, 0xF7, 3, 8, ALU_RM16},
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// 32-bit
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{ BX_IA_INC_Ed, 0xFF, 0, 8, ALU_RM32},
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{ BX_IA_DEC_Ed, 0xFF, 1, 8, ALU_RM32},
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{ BX_IA_NOT_Ed, 0xF7, 2, 8, ALU_RM32},
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{ BX_IA_NEG_Ed, 0xF7, 3, 8, ALU_RM32},
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// register
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{ BX_IA_INC_RX, 0x40, 8, 7, ALU_REG},
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{ BX_IA_DEC_RX, 0x48, 8, 7, ALU_REG},
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{ BX_IA_INC_ERX, 0x40, 8, 7, ALU_REG},
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{ BX_IA_DEC_ERX, 0x48, 8, 7, ALU_REG},
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/* --- \\\ UNARY OPERATIONS /// --- */
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/* --- /// SHIFT OPERATIONS \\\ --- */
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// a macro to reduce copy-paste overhead
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#define SHIFTOPS(OPCODE, WD, CLASS) \
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{ BX_IA_RCL_E##WD, OPCODE, 2, 8, CLASS }, \
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{ BX_IA_RCR_E##WD, OPCODE, 3, 8, CLASS }, \
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{ BX_IA_ROL_E##WD, OPCODE, 0, 8, CLASS }, \
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{ BX_IA_ROR_E##WD, OPCODE, 1, 8, CLASS }, \
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{ BX_IA_SHL_E##WD, OPCODE, 4, 8, CLASS }, \
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{ BX_IA_SAR_E##WD, OPCODE, 7, 8, CLASS }, \
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{ BX_IA_SHL_E##WD, OPCODE, 6, 8, CLASS }, \
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{ BX_IA_SHR_E##WD, OPCODE, 5, 8, CLASS }
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// first shifting by one bit
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SHIFTOPS(0xD0, b, ALU_RM8_ONE),
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SHIFTOPS(0xD1, w, ALU_RM16_ONE),
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SHIFTOPS(0xD1, d, ALU_RM32_ONE),
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// then shifting by CL bits
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SHIFTOPS(0xD2, b, ALU_REG_RM8),
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SHIFTOPS(0xD3, w, ALU_REG_RM16),
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SHIFTOPS(0xD3, d, ALU_REG_RM32),
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// then shifting by a number of bits given via an immediate value
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SHIFTOPS(0xC0, b, ALU_IMM8_RM8),
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SHIFTOPS(0xC1, w, ALU_IMM8_RM16),
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SHIFTOPS(0xC1, d, ALU_IMM8_RM32),
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#undef SHIFTOPS
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/* --- \\\ SHIFT OPERATIONS /// --- */
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/**
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*
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* The remaining instructions, roughly ordered,
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* in the form of a (probably obsolete) experiment method
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* /**
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* Assigns a given opcode a class of ALU instructions
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* @param opcode the opcode to examine
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* @returns an enum AluClass object
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X86AluClass isALUInstruction(unsigned opcode);
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*
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* X86AluClass L4SysExperiment::isALUInstruction(unsigned opcode) {
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switch (opcode) {
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case BX_IA_ADC_EbGb:
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case BX_IA_ADC_EdGd:
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case BX_IA_ADC_EwGw:
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case BX_IA_ADD_EbGb:
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case BX_IA_ADD_EdGd:
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case BX_IA_ADD_EwGw:
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case BX_IA_AND_EbGb:
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case BX_IA_AND_EdGd:
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case BX_IA_AND_EwGw:
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case BX_IA_CMP_EbGb:
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case BX_IA_CMP_EdGd:
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case BX_IA_CMP_EwGw:
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case BX_IA_OR_EbGb:
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case BX_IA_OR_EdGd:
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case BX_IA_OR_EwGw:
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case BX_IA_SBB_EbGb:
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case BX_IA_SBB_EdGd:
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case BX_IA_SBB_EwGw:
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case BX_IA_SUB_EbGb:
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case BX_IA_SUB_EdGd:
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case BX_IA_SUB_EwGw:
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case BX_IA_XOR_EbGb:
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case BX_IA_XOR_EdGd:
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case BX_IA_XOR_EwGw:
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case BX_IA_ADC_ALIb:
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case BX_IA_ADC_AXIw:
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case BX_IA_ADC_EAXId:
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case BX_IA_ADD_EbIb:
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case BX_IA_OR_EbIb:
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case BX_IA_ADC_EbIb:
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case BX_IA_SBB_EbIb:
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case BX_IA_AND_EbIb:
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case BX_IA_SUB_EbIb:
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case BX_IA_XOR_EbIb:
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case BX_IA_CMP_EbIb:
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case BX_IA_ADD_EwIw:
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case BX_IA_OR_EwIw:
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case BX_IA_ADC_EwIw:
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case BX_IA_SBB_EwIw:
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case BX_IA_AND_EwIw:
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case BX_IA_SUB_EwIw:
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case BX_IA_XOR_EwIw:
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case BX_IA_CMP_EwIw:
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case BX_IA_ADD_EdId:
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case BX_IA_OR_EdId:
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case BX_IA_ADC_EdId:
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case BX_IA_SBB_EdId:
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case BX_IA_AND_EdId:
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case BX_IA_SUB_EdId:
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case BX_IA_XOR_EdId:
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case BX_IA_CMP_EdId:
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case BX_IA_ADC_GbEb:
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case BX_IA_ADC_GwEw:
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case BX_IA_ADC_GdEd:
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case BX_IA_ADD_ALIb:
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case BX_IA_ADD_AXIw:
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case BX_IA_ADD_EAXId:
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case BX_IA_ADD_GbEb:
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case BX_IA_ADD_GwEw:
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case BX_IA_ADD_GdEd:
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case BX_IA_AND_ALIb:
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case BX_IA_AND_AXIw:
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case BX_IA_AND_EAXId:
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case BX_IA_AND_GbEb:
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case BX_IA_AND_GwEw:
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case BX_IA_AND_GdEd:
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default:
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return ALU_UNDEF;
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}
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}
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*
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*/
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};
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#endif // __L4SYS_ALUINSTR_HPP__
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