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core/sal: add x86 control and segment registers

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new register type RT_CONTROL:
CR0, CR2, CR3, CR4

new register type RT_SEGMENT:
CS, DS, ES, FS, GS, SS

Reading/writing is mostly untested except for CR3...

Change-Id: I0d0fba4a1669153ab2577e82ab64a04cf2bbfb94
This commit is contained in:
Florian Lukas
2014-02-26 14:10:44 +01:00
parent 396e00ce59
commit 21f5f681e0
4 changed files with 168 additions and 1 deletions
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110
src/core/sal/bochs/BochsCPU.cc
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@ -14,6 +14,55 @@ regdata_t BochsCPU::getRegisterContent(const Register* reg) const
return static_cast<regdata_t>(BX_CPU(id)->read_eflags());
}
// untested
if (reg->getId() == RID_CR0) { // CR0 register?
return static_cast<regdata_t>(BX_CPU(id)->read_CR0());
}
// untested
if (reg->getId() == RID_CR2) { // CR2 register?
return static_cast<regdata_t>(BX_CPU(id)->cr2);
}
if (reg->getId() == RID_CR3) { // CR3 register?
return static_cast<regdata_t>(BX_CPU(id)->cr3);
}
// untested
if (reg->getId() == RID_CR4) { // CR4 register?
return static_cast<regdata_t>(BX_CPU(id)->read_CR4());
}
// untested
if (reg->getId() == RID_CS) { // CS register?
return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_CS].selector.value);
}
// untested
if (reg->getId() == RID_DS) { // DS register?
return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_DS].selector.value);
}
// untested
if (reg->getId() == RID_ES) { // ES register?
return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_ES].selector.value);
}
// untested
if (reg->getId() == RID_FS) { // FS register?
return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_FS].selector.value);
}
// untested
if (reg->getId() == RID_GS) { // GS register?
return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_GS].selector.value);
}
// untested
if (reg->getId() == RID_SS) { // SS register?
return static_cast<regdata_t>(BX_CPU(id)->sregs[BX_SEG_REG_SS].selector.value);
}
#ifdef SIM_SUPPORT_64
if (reg->getId() == RID_PC) // program counter?
return static_cast<regdata_t>(BX_CPU(id)->gen_reg[BX_64BIT_REG_RIP].rrx);
@ -45,6 +94,67 @@ void BochsCPU::setRegisterContent(const Register* reg, regdata_t value)
return;
}
#ifndef __puma
// untested
if (reg->getId() == RID_CR0) { // CR0 register?
BX_CPU(id)->SetCR0(value);
return;
}
// untested
if (reg->getId() == RID_CR2) { // CR2 register?
BX_CPU(id)->cr2 = value;
return;
}
if (reg->getId() == RID_CR3) { // CR3 register?
BX_CPU(id)->SetCR3(value);
return;
}
// untested
if (reg->getId() == RID_CR4) { // CR4 register?
BX_CPU(id)->SetCR4(value);
return;
}
// untested
if (reg->getId() == RID_CS) { // CS register?
BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_CS], value);
return;
}
// untested
if (reg->getId() == RID_DS) { // DS register?
BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_DS], value);
return;
}
// untested
if (reg->getId() == RID_ES) { // ES register?
BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_ES], value);
return;
}
// untested
if (reg->getId() == RID_FS) { // FS register?
BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_FS], value);
return;
}
// untested
if (reg->getId() == RID_GS) { // GS register?
BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_GS], value);
return;
}
// untested
if (reg->getId() == RID_SS) { // SS register?
BX_CPU(id)->load_seg_reg(&BX_CPU(id)->sregs[BX_SEG_REG_SS], value);
return;
}
#endif
regdata_t* pData;
#ifdef SIM_SUPPORT_64
if (reg->getId() == RID_PC) // program counter?